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Fri, 11 Sep 2026 21:12:27 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, johan.almbladh@anyfinetworks.com, paulburton@kernel.org, tsbogend@alpha.franken.de Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, bpf@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH bpf-next v3 1/2] bpf, mips: Factor register moves into helpers Date: Sat, 12 Sep 2026 00:12:19 -0400 Message-ID: <20260912041220.444715-2-main.kalliope@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260912041220.444715-1-main.kalliope@gmail.com> References: <20260912041220.444715-1-main.kalliope@gmail.com> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Factor ALU32 and ALU64 register moves into backend-local helpers, keeping register-pair handling and zero extension with the move. This prepares for decoding the MOVSX width in those helpers. Keep the verifier-inserted zero-extension marker on its existing path. No functional change intended. Assisted-by: Codex:gpt-6 Signed-off-by: Nicholas Dudar --- arch/mips/net/bpf_jit_comp32.c | 22 ++++++++++++++++++---- arch/mips/net/bpf_jit_comp64.c | 18 +++++++++++++++--- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c index 6619182b5ef..6d603d9eeb1 100644 --- a/arch/mips/net/bpf_jit_comp32.c +++ b/arch/mips/net/bpf_jit_comp32.c @@ -190,6 +190,22 @@ static void emit_zext_ver(struct jit_context *ctx, const u8 dst[]) } } +/* Register move operation (32-bit) */ +static void emit_mov_r32(struct jit_context *ctx, const u8 dst[], + const u8 src[]) +{ + emit_mov_r(ctx, lo(dst), lo(src)); + emit_zext_ver(ctx, dst); +} + +/* Register move operation (64-bit) */ +static void emit_mov_r64(struct jit_context *ctx, const u8 dst[], + const u8 src[]) +{ + emit_mov_r(ctx, lo(dst), lo(src)); + emit_mov_r(ctx, hi(dst), hi(src)); +} + /* Load delay slot, if ISA mandates it */ static void emit_load_delay(struct jit_context *ctx) { @@ -1494,8 +1510,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) /* Special mov32 for zext */ emit_mov_i(ctx, hi(dst), 0); } else { - emit_mov_r(ctx, lo(dst), lo(src)); - emit_zext_ver(ctx, dst); + emit_mov_r32(ctx, dst, src); } break; /* dst = -dst */ @@ -1564,8 +1579,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) break; /* dst = src (64-bit) */ case BPF_ALU64 | BPF_MOV | BPF_X: - emit_mov_r(ctx, lo(dst), lo(src)); - emit_mov_r(ctx, hi(dst), hi(src)); + emit_mov_r64(ctx, dst, src); break; /* dst = -dst (64-bit) */ case BPF_ALU64 | BPF_NEG: diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c index db027c2d922..92df2eba139 100644 --- a/arch/mips/net/bpf_jit_comp64.c +++ b/arch/mips/net/bpf_jit_comp64.c @@ -120,6 +120,19 @@ static void emit_zext_ver(struct jit_context *ctx, u8 dst) emit_zext(ctx, dst); } +/* Register move operation (32-bit) */ +static void emit_mov_r32(struct jit_context *ctx, u8 dst, u8 src) +{ + emit_mov_r(ctx, dst, src); + emit_zext_ver(ctx, dst); +} + +/* Register move operation (64-bit) */ +static void emit_mov_r64(struct jit_context *ctx, u8 dst, u8 src) +{ + emit_mov_r(ctx, dst, src); +} + /* dst = imm (64-bit) */ static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64) { @@ -681,8 +694,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) /* Special mov32 for zext */ emit_zext(ctx, dst); } else { - emit_mov_r(ctx, dst, src); - emit_zext_ver(ctx, dst); + emit_mov_r32(ctx, dst, src); } break; /* dst = -dst */ @@ -767,7 +779,7 @@ int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) break; /* dst = src (64-bit) */ case BPF_ALU64 | BPF_MOV | BPF_X: - emit_mov_r(ctx, dst, src); + emit_mov_r64(ctx, dst, src); break; /* dst = -dst (64-bit) */ case BPF_ALU64 | BPF_NEG: