[PATCH 2/3] dwarf_loader: Do not align the argument register index for FP arguments

[Yonghong Song <yonghong.song@linux.dev>]

The arm64 ABI aligns a general purpose argument that occupies two registers
to an even register number, leaving a hole when the next free register is an
odd one.  parameter__abi_reg_align() applies that rule to every argument
wider than a pointer, but floating point and vector arguments are allocated
from a register bank of their own -- v0-v7 on arm64, xmm0-xmm7 on x86-64 --
so a wide one never takes a general purpose register pair and must not
trigger the rule:

  u64 f_fp(u64 a, long double v, u64 b);

Recognize floating point and vector arguments and leave the general purpose
register index alone for them.

This does not change the BTF that is emitted today: such an argument still
advances the general purpose register index by its own size, so the
alignment is not the only thing standing between the model and the ABI.  It
does keep parameter__abi_reg_align() honest about which bank the rule
applies to.

Signed-off-by: Yonghong Song <yonghong.song@linux.dev>
---
 dwarf_loader.c | 21 ++++++++++++++++++++-
 dwarves.h      | 10 ++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/dwarf_loader.c b/dwarf_loader.c
index 81c2076..1e5363a 100644
--- a/dwarf_loader.c
+++ b/dwarf_loader.c
@@ -3651,6 +3651,25 @@ static int parameter__abi_slots(const struct parameter *parm, const struct cu *c
 	return slots > 0 ? slots : 1;
 }
 
+/*
+ * Floating point and vector arguments are allocated from a register bank of
+ * their own -- v0-v7 on arm64, xmm0-xmm7 on x86-64 -- so a wide one does not
+ * take a general purpose register pair and must not trigger the even-register
+ * alignment rule, which applies to the general purpose bank only.
+ */
+static bool tag__uses_gpr_bank(const struct tag *type, const struct cu *cu)
+{
+	/* Scalars represented by FP/SIMD registers have their own allocation bank. */
+	if (tag__is_base_type(type, cu) && base_type__is_float(tag__base_type(type)))
+		return false;
+
+	/* Also exclude vector/SIMD types if dwarves represents them distinctly. */
+	if (tag__is_vector(type))
+		return false;
+
+	return true;
+}
+
 static int parameter__abi_reg_align(const struct parameter *parm, const struct cu *cu)
 {
 	struct tag *type;
@@ -3659,7 +3678,7 @@ static int parameter__abi_reg_align(const struct parameter *parm, const struct c
 		return 1;
 
 	type = tag__strip_typedefs_and_modifiers(&parm->tag, cu);
-	if (type == NULL)
+	if (type == NULL || !tag__uses_gpr_bank(type, cu))
 		return 1;
 
 	return tag__natural_alignment(type, cu) > cu->addr_size ? 2 : 1;
diff --git a/dwarves.h b/dwarves.h
index 70adbbf..f3453ed 100644
--- a/dwarves.h
+++ b/dwarves.h
@@ -1607,6 +1607,11 @@ static inline uint16_t base_type__size(const struct tag *tag)
 	return tag__base_type(tag)->bit_size / 8;
 }
 
+static inline bool base_type__is_float(const struct base_type *bt)
+{
+	return bt->float_type != 0;
+}
+
 const char *__base_type__name(const struct base_type *bt);
 
 const char *base_type__name(const struct base_type *btype, char *bf, size_t len);
@@ -1625,6 +1630,11 @@ static inline struct array_type *tag__array_type(const struct tag *tag)
 	return (struct array_type *)tag;
 }
 
+static inline bool tag__is_vector(const struct tag *tag)
+{
+	return tag->tag == DW_TAG_array_type && tag__array_type(tag)->is_vector;
+}
+
 struct string_type {
 	struct tag      tag;
 	uint32_t        nr_entries;
-- 
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