[PATCH bpf-next 0/7] Support cpu v4 instructions for arm64

[PATCH bpf-next 0/7] Support cpu v4 instructions for arm64

[Xu Kuohai]

From: Xu Kuohai <xukuohai@huawei.com>

This series adds arm64 support for cpu v4 instructions [1].

[1] https://lore.kernel.org/all/20230728011143.3710005-1-yonghong.song@linux.dev/

Xu Kuohai (7):
  arm64: insn: Add encoders for LDRSB/LDRSH/LDRSW
  bpf, arm64: Support sign-extension load instructions
  bpf, arm64: Support sign-extension mov instructions
  bpf, arm64: Support unconditional bswap
  bpf, arm64: Support 32-bit offset jmp instruction
  bpf, arm64: Support signed div/mod instructions
  selftests/bpf: Enable cpu v4 tests for arm64

 arch/arm64/include/asm/insn.h                 |  4 +
 arch/arm64/lib/insn.c                         |  6 ++
 arch/arm64/net/bpf_jit.h                      | 12 +++
 arch/arm64/net/bpf_jit_comp.c                 | 91 +++++++++++++++----
 .../selftests/bpf/progs/test_ldsx_insn.c      |  2 +-
 .../selftests/bpf/progs/verifier_bswap.c      |  2 +-
 .../selftests/bpf/progs/verifier_gotol.c      |  2 +-
 .../selftests/bpf/progs/verifier_ldsx.c       |  2 +-
 .../selftests/bpf/progs/verifier_movsx.c      |  2 +-
 .../selftests/bpf/progs/verifier_sdiv.c       |  2 +-
 10 files changed, 103 insertions(+), 22 deletions(-)

-- 
2.30.2

[PATCH bpf-next 1/7] arm64: insn: Add encoders for LDRSB/LDRSH/LDRSW

[Xu Kuohai]

From: Xu Kuohai <xukuohai@huawei.com>

To support BPF sign-extend load instructions, add encoders for
LDRSB/LDRSH/LDRSW.

LDRSB/LDRSH/LDRSW (immediate) is encoded as follows:

     3     2 2   2   2                       1         0         0
     0     7 6   4   2                       0         5         0
  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  | sz|1 1 1|0|0 1|opc|        imm12          |    Rn   |    Rt   |
  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

LDRSB/LDRSH/LDRSW (register) is encoded as follows:

     3     2 2   2   2 2         1     1 1   1         0         0
     0     7 6   4   2 1         6     3 2   0         5         0
  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  | sz|1 1 1|0|0 0|opc|1|    Rm   | opt |S|1 0|    Rn   |    Rt   |
  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

where:

   - sz
     indicates whether 8-bit, 16-bit or 32-bit data is to be loaded

   - opc
     opc[1] (bit 23) is always 1 and opc[0] == 1 indicates regsize
     is 32-bit. Since BPF signed load instructions always exend the
     sign bit to bit 63 regardless of whether it loads an 8-bit,
     16-bit or 32-bit data. So only 64-bit register size is required.
     That is, it's sufficient to set field opc fixed to 0x2.

   - opt
     Indicates whether to sign extend the offset register Rm and the
     effective bits of Rm. We set opt to 0x7 (SXTX) since we'll use
     Rm as a sgined 64-bit value in BPF.

   - S
     Optional only when opt field is 0x3 (LSL)

In short, the above fields are encoded to the values listed below.

                   sz   opc  opt   S
LDRSB (immediate)  0x0  0x2  na    na
LDRSH (immediate)  0x1  0x2  na    na
LDRSW (immediate)  0x2  0x2  na    na
LDRSB (register)   0x0  0x2  0x7   0
LDRSH (register)   0x1  0x2  0x7   0
LDRSW (register)   0x2  0x2  0x7   0

Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
---
 arch/arm64/include/asm/insn.h | 4 ++++
 arch/arm64/lib/insn.c         | 6 ++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 139a88e4e852..db1aeacd4cd9 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -186,6 +186,8 @@ enum aarch64_insn_ldst_type {
 	AARCH64_INSN_LDST_LOAD_ACQ_EX,
 	AARCH64_INSN_LDST_STORE_EX,
 	AARCH64_INSN_LDST_STORE_REL_EX,
+	AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET,
+	AARCH64_INSN_LDST_SIGNED_LOAD_REG_OFFSET,
 };
 
 enum aarch64_insn_adsb_type {
@@ -324,6 +326,7 @@ __AARCH64_INSN_FUNCS(prfm,	0x3FC00000, 0x39800000)
 __AARCH64_INSN_FUNCS(prfm_lit,	0xFF000000, 0xD8000000)
 __AARCH64_INSN_FUNCS(store_imm,	0x3FC00000, 0x39000000)
 __AARCH64_INSN_FUNCS(load_imm,	0x3FC00000, 0x39400000)
+__AARCH64_INSN_FUNCS(signed_load_imm, 0X3FC00000, 0x39800000)
 __AARCH64_INSN_FUNCS(store_pre,	0x3FE00C00, 0x38000C00)
 __AARCH64_INSN_FUNCS(load_pre,	0x3FE00C00, 0x38400C00)
 __AARCH64_INSN_FUNCS(store_post,	0x3FE00C00, 0x38000400)
@@ -337,6 +340,7 @@ __AARCH64_INSN_FUNCS(ldset,	0x3F20FC00, 0x38203000)
 __AARCH64_INSN_FUNCS(swp,	0x3F20FC00, 0x38208000)
 __AARCH64_INSN_FUNCS(cas,	0x3FA07C00, 0x08A07C00)
 __AARCH64_INSN_FUNCS(ldr_reg,	0x3FE0EC00, 0x38606800)
+__AARCH64_INSN_FUNCS(signed_ldr_reg, 0X3FE0FC00, 0x38A0E800)
 __AARCH64_INSN_FUNCS(ldr_imm,	0x3FC00000, 0x39400000)
 __AARCH64_INSN_FUNCS(ldr_lit,	0xBF000000, 0x18000000)
 __AARCH64_INSN_FUNCS(ldrsw_lit,	0xFF000000, 0x98000000)
diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
index 924934cb85ee..a635ab83fee3 100644
--- a/arch/arm64/lib/insn.c
+++ b/arch/arm64/lib/insn.c
@@ -385,6 +385,9 @@ u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
 	case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
 		insn = aarch64_insn_get_ldr_reg_value();
 		break;
+	case AARCH64_INSN_LDST_SIGNED_LOAD_REG_OFFSET:
+		insn = aarch64_insn_get_signed_ldr_reg_value();
+		break;
 	case AARCH64_INSN_LDST_STORE_REG_OFFSET:
 		insn = aarch64_insn_get_str_reg_value();
 		break;
@@ -430,6 +433,9 @@ u32 aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,
 	case AARCH64_INSN_LDST_LOAD_IMM_OFFSET:
 		insn = aarch64_insn_get_ldr_imm_value();
 		break;
+	case AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET:
+		insn = aarch64_insn_get_signed_load_imm_value();
+		break;
 	case AARCH64_INSN_LDST_STORE_IMM_OFFSET:
 		insn = aarch64_insn_get_str_imm_value();
 		break;
-- 
2.30.2

[PATCH bpf-next 2/7] bpf, arm64: Support sign-extension load instructions

[Xu Kuohai]

From: Xu Kuohai <xukuohai@huawei.com>

Add jit support for sign-extension load instructions.

Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
---
 arch/arm64/net/bpf_jit.h      |  6 +++++
 arch/arm64/net/bpf_jit_comp.c | 45 ++++++++++++++++++++++++++++-------
 2 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h
index c2edadb8ec6a..086ffbad0eb5 100644
--- a/arch/arm64/net/bpf_jit.h
+++ b/arch/arm64/net/bpf_jit.h
@@ -59,10 +59,13 @@
 		AARCH64_INSN_LDST_##type##_REG_OFFSET)
 #define A64_STRB(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 8, STORE)
 #define A64_LDRB(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 8, LOAD)
+#define A64_LDRSB(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 8, SIGNED_LOAD)
 #define A64_STRH(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 16, STORE)
 #define A64_LDRH(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 16, LOAD)
+#define A64_LDRSH(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 16, SIGNED_LOAD)
 #define A64_STR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, STORE)
 #define A64_LDR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, LOAD)
+#define A64_LDRSW(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 32, SIGNED_LOAD)
 #define A64_STR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, STORE)
 #define A64_LDR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, LOAD)
 
@@ -73,10 +76,13 @@
 		AARCH64_INSN_LDST_##type##_IMM_OFFSET)
 #define A64_STRBI(Wt, Xn, imm)  A64_LS_IMM(Wt, Xn, imm, 8, STORE)
 #define A64_LDRBI(Wt, Xn, imm)  A64_LS_IMM(Wt, Xn, imm, 8, LOAD)
+#define A64_LDRSBI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 8, SIGNED_LOAD)
 #define A64_STRHI(Wt, Xn, imm)  A64_LS_IMM(Wt, Xn, imm, 16, STORE)
 #define A64_LDRHI(Wt, Xn, imm)  A64_LS_IMM(Wt, Xn, imm, 16, LOAD)
+#define A64_LDRSHI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 16, SIGNED_LOAD)
 #define A64_STR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, STORE)
 #define A64_LDR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, LOAD)
+#define A64_LDRSWI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 32, SIGNED_LOAD)
 #define A64_STR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, STORE)
 #define A64_LDR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, LOAD)
 
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index ec2174838f2a..22f1b0d5fb3c 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -715,7 +715,8 @@ static int add_exception_handler(const struct bpf_insn *insn,
 		/* First pass */
 		return 0;
 
-	if (BPF_MODE(insn->code) != BPF_PROBE_MEM)
+	if (BPF_MODE(insn->code) != BPF_PROBE_MEM &&
+		BPF_MODE(insn->code) != BPF_PROBE_MEMSX)
 		return 0;
 
 	if (!ctx->prog->aux->extable ||
@@ -779,6 +780,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 	u8 dst_adj;
 	int off_adj;
 	int ret;
+	bool sign_extend;
 
 	switch (code) {
 	/* dst = src */
@@ -1122,7 +1124,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 		return 1;
 	}
 
-	/* LDX: dst = *(size *)(src + off) */
+	/* LDX: dst = (u64)*(unsigned size *)(src + off) */
 	case BPF_LDX | BPF_MEM | BPF_W:
 	case BPF_LDX | BPF_MEM | BPF_H:
 	case BPF_LDX | BPF_MEM | BPF_B:
@@ -1131,6 +1133,13 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 	case BPF_LDX | BPF_PROBE_MEM | BPF_W:
 	case BPF_LDX | BPF_PROBE_MEM | BPF_H:
 	case BPF_LDX | BPF_PROBE_MEM | BPF_B:
+	/* LDXS: dst_reg = (s64)*(signed size *)(src_reg + off) */
+	case BPF_LDX | BPF_MEMSX | BPF_B:
+	case BPF_LDX | BPF_MEMSX | BPF_H:
+	case BPF_LDX | BPF_MEMSX | BPF_W:
+	case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
+	case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
+	case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
 		if (ctx->fpb_offset > 0 && src == fp) {
 			src_adj = fpb;
 			off_adj = off + ctx->fpb_offset;
@@ -1138,29 +1147,49 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 			src_adj = src;
 			off_adj = off;
 		}
+		sign_extend = (BPF_MODE(insn->code) == BPF_MEMSX ||
+				BPF_MODE(insn->code) == BPF_PROBE_MEMSX);
 		switch (BPF_SIZE(code)) {
 		case BPF_W:
 			if (is_lsi_offset(off_adj, 2)) {
-				emit(A64_LDR32I(dst, src_adj, off_adj), ctx);
+				if (sign_extend)
+					emit(A64_LDRSWI(dst, src_adj, off_adj), ctx);
+				else
+					emit(A64_LDR32I(dst, src_adj, off_adj), ctx);
 			} else {
 				emit_a64_mov_i(1, tmp, off, ctx);
-				emit(A64_LDR32(dst, src, tmp), ctx);
+				if (sign_extend)
+					emit(A64_LDRSW(dst, src_adj, off_adj), ctx);
+				else
+					emit(A64_LDR32(dst, src, tmp), ctx);
 			}
 			break;
 		case BPF_H:
 			if (is_lsi_offset(off_adj, 1)) {
-				emit(A64_LDRHI(dst, src_adj, off_adj), ctx);
+				if (sign_extend)
+					emit(A64_LDRSHI(dst, src_adj, off_adj), ctx);
+				else
+					emit(A64_LDRHI(dst, src_adj, off_adj), ctx);
 			} else {
 				emit_a64_mov_i(1, tmp, off, ctx);
-				emit(A64_LDRH(dst, src, tmp), ctx);
+				if (sign_extend)
+					emit(A64_LDRSH(dst, src, tmp), ctx);
+				else
+					emit(A64_LDRH(dst, src, tmp), ctx);
 			}
 			break;
 		case BPF_B:
 			if (is_lsi_offset(off_adj, 0)) {
-				emit(A64_LDRBI(dst, src_adj, off_adj), ctx);
+				if (sign_extend)
+					emit(A64_LDRSBI(dst, src_adj, off_adj), ctx);
+				else
+					emit(A64_LDRBI(dst, src_adj, off_adj), ctx);
 			} else {
 				emit_a64_mov_i(1, tmp, off, ctx);
-				emit(A64_LDRB(dst, src, tmp), ctx);
+				if (sign_extend)
+					emit(A64_LDRSB(dst, src, tmp), ctx);
+				else
+					emit(A64_LDRB(dst, src, tmp), ctx);
 			}
 			break;
 		case BPF_DW:
-- 
2.30.2

[PATCH bpf-next 3/7] bpf, arm64: Support sign-extension mov instructions

[Xu Kuohai]

From: Xu Kuohai <xukuohai@huawei.com>

Add jit support for BPF sign-extension mov instructions with
arm64 SXTB/SXTH/SXTW instructions.

Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
---
 arch/arm64/net/bpf_jit.h      |  5 +++++
 arch/arm64/net/bpf_jit_comp.c | 15 ++++++++++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h
index 086ffbad0eb5..949810a0c48c 100644
--- a/arch/arm64/net/bpf_jit.h
+++ b/arch/arm64/net/bpf_jit.h
@@ -192,6 +192,11 @@
 #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15)
 #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31)
 
+/* Sign extend */
+#define A64_SXTB(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 7)
+#define A64_SXTH(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 15)
+#define A64_SXTW(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 31)
+
 /* Move wide (immediate) */
 #define A64_MOVEW(sf, Rd, imm16, shift, type) \
 	aarch64_insn_gen_movewide(Rd, imm16, shift, \
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 22f1b0d5fb3c..9b796e74ef42 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -786,7 +786,20 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 	/* dst = src */
 	case BPF_ALU | BPF_MOV | BPF_X:
 	case BPF_ALU64 | BPF_MOV | BPF_X:
-		emit(A64_MOV(is64, dst, src), ctx);
+		switch (insn->off) {
+		case 0:
+			emit(A64_MOV(is64, dst, src), ctx);
+			break;
+		case 8:
+			emit(A64_SXTB(is64, dst, src), ctx);
+			break;
+		case 16:
+			emit(A64_SXTH(is64, dst, src), ctx);
+			break;
+		case 32:
+			emit(A64_SXTW(is64, dst, src), ctx);
+			break;
+		}
 		break;
 	/* dst = dst OP src */
 	case BPF_ALU | BPF_ADD | BPF_X:
-- 
2.30.2

[PATCH bpf-next 4/7] bpf, arm64: Support unconditional bswap

[Xu Kuohai]

From: Xu Kuohai <xukuohai@huawei.com>

Add jit support for unconditional bswap instructions.

Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
---
 arch/arm64/net/bpf_jit_comp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 9b796e74ef42..1d35acb880dc 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -855,11 +855,12 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 	/* dst = BSWAP##imm(dst) */
 	case BPF_ALU | BPF_END | BPF_FROM_LE:
 	case BPF_ALU | BPF_END | BPF_FROM_BE:
+	case BPF_ALU64 | BPF_END | BPF_FROM_LE:
 #ifdef CONFIG_CPU_BIG_ENDIAN
-		if (BPF_SRC(code) == BPF_FROM_BE)
+		if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_BE)
 			goto emit_bswap_uxt;
 #else /* !CONFIG_CPU_BIG_ENDIAN */
-		if (BPF_SRC(code) == BPF_FROM_LE)
+		if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_LE)
 			goto emit_bswap_uxt;
 #endif
 		switch (imm) {
-- 
2.30.2

[PATCH bpf-next 5/7] bpf, arm64: Support 32-bit offset jmp instruction

[Xu Kuohai]

From: Xu Kuohai <xukuohai@huawei.com>

Add support for 32-bit offset jmp instructions. Given the arm64
direct jump range is +-128MB, which is large enough for BPF prog,
jumps beyond this range are not supported.

Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
---
 arch/arm64/net/bpf_jit_comp.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 1d35acb880dc..924b8ef2e46a 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -982,7 +982,11 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 
 	/* JUMP off */
 	case BPF_JMP | BPF_JA:
-		jmp_offset = bpf2a64_offset(i, off, ctx);
+	case BPF_JMP32 | BPF_JA:
+		if (BPF_CLASS(code) == BPF_JMP)
+			jmp_offset = bpf2a64_offset(i, off, ctx);
+		else
+			jmp_offset = bpf2a64_offset(i, imm, ctx);
 		check_imm26(jmp_offset);
 		emit(A64_B(jmp_offset), ctx);
 		break;
-- 
2.30.2

[PATCH bpf-next 6/7] bpf, arm64: Support signed div/mod instructions

[Xu Kuohai]

From: Xu Kuohai <xukuohai@huawei.com>

Add jit for signed div/mod instructions.

Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
---
 arch/arm64/net/bpf_jit.h      |  1 +
 arch/arm64/net/bpf_jit_comp.c | 20 ++++++++++++++++----
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h
index 949810a0c48c..23b1b34db088 100644
--- a/arch/arm64/net/bpf_jit.h
+++ b/arch/arm64/net/bpf_jit.h
@@ -234,6 +234,7 @@
 #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \
 	A64_VARIANT(sf), AARCH64_INSN_DATA2_##type)
 #define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)
+#define A64_SDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, SDIV)
 #define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)
 #define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)
 #define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 924b8ef2e46a..150d1c6543f7 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -828,11 +828,17 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 		break;
 	case BPF_ALU | BPF_DIV | BPF_X:
 	case BPF_ALU64 | BPF_DIV | BPF_X:
-		emit(A64_UDIV(is64, dst, dst, src), ctx);
+		if (!off)
+			emit(A64_UDIV(is64, dst, dst, src), ctx);
+		else
+			emit(A64_SDIV(is64, dst, dst, src), ctx);
 		break;
 	case BPF_ALU | BPF_MOD | BPF_X:
 	case BPF_ALU64 | BPF_MOD | BPF_X:
-		emit(A64_UDIV(is64, tmp, dst, src), ctx);
+		if (!off)
+			emit(A64_UDIV(is64, tmp, dst, src), ctx);
+		else
+			emit(A64_SDIV(is64, tmp, dst, src), ctx);
 		emit(A64_MSUB(is64, dst, dst, tmp, src), ctx);
 		break;
 	case BPF_ALU | BPF_LSH | BPF_X:
@@ -959,12 +965,18 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
 	case BPF_ALU | BPF_DIV | BPF_K:
 	case BPF_ALU64 | BPF_DIV | BPF_K:
 		emit_a64_mov_i(is64, tmp, imm, ctx);
-		emit(A64_UDIV(is64, dst, dst, tmp), ctx);
+		if (!off)
+			emit(A64_UDIV(is64, dst, dst, tmp), ctx);
+		else
+			emit(A64_SDIV(is64, dst, dst, tmp), ctx);
 		break;
 	case BPF_ALU | BPF_MOD | BPF_K:
 	case BPF_ALU64 | BPF_MOD | BPF_K:
 		emit_a64_mov_i(is64, tmp2, imm, ctx);
-		emit(A64_UDIV(is64, tmp, dst, tmp2), ctx);
+		if (!off)
+			emit(A64_UDIV(is64, tmp, dst, tmp2), ctx);
+		else
+			emit(A64_SDIV(is64, tmp, dst, tmp2), ctx);
 		emit(A64_MSUB(is64, dst, dst, tmp, tmp2), ctx);
 		break;
 	case BPF_ALU | BPF_LSH | BPF_K:
-- 
2.30.2

[PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for arm64

[Xu Kuohai]

From: Xu Kuohai <xukuohai@huawei.com>

Enable cpu v4 instruction tests for arm64.

Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
---
 tools/testing/selftests/bpf/progs/test_ldsx_insn.c | 2 +-
 tools/testing/selftests/bpf/progs/verifier_bswap.c | 2 +-
 tools/testing/selftests/bpf/progs/verifier_gotol.c | 2 +-
 tools/testing/selftests/bpf/progs/verifier_ldsx.c  | 2 +-
 tools/testing/selftests/bpf/progs/verifier_movsx.c | 2 +-
 tools/testing/selftests/bpf/progs/verifier_sdiv.c  | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
index 321abf862801..916d9435f12c 100644
--- a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
+++ b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
@@ -5,7 +5,7 @@
 #include <bpf/bpf_helpers.h>
 #include <bpf/bpf_tracing.h>
 
-#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
 const volatile int skip = 0;
 #else
 const volatile int skip = 1;
diff --git a/tools/testing/selftests/bpf/progs/verifier_bswap.c b/tools/testing/selftests/bpf/progs/verifier_bswap.c
index 724bb38988b5..770f9d882542 100644
--- a/tools/testing/selftests/bpf/progs/verifier_bswap.c
+++ b/tools/testing/selftests/bpf/progs/verifier_bswap.c
@@ -4,7 +4,7 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("BSWAP, 16")
diff --git a/tools/testing/selftests/bpf/progs/verifier_gotol.c b/tools/testing/selftests/bpf/progs/verifier_gotol.c
index ce48f7757db2..17319a505e87 100644
--- a/tools/testing/selftests/bpf/progs/verifier_gotol.c
+++ b/tools/testing/selftests/bpf/progs/verifier_gotol.c
@@ -4,7 +4,7 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("gotol, small_imm")
diff --git a/tools/testing/selftests/bpf/progs/verifier_ldsx.c b/tools/testing/selftests/bpf/progs/verifier_ldsx.c
index 3c3d1bddd67f..4a2b567c0f69 100644
--- a/tools/testing/selftests/bpf/progs/verifier_ldsx.c
+++ b/tools/testing/selftests/bpf/progs/verifier_ldsx.c
@@ -4,7 +4,7 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("LDSX, S8")
diff --git a/tools/testing/selftests/bpf/progs/verifier_movsx.c b/tools/testing/selftests/bpf/progs/verifier_movsx.c
index be6f69a6b659..d9528d578bd9 100644
--- a/tools/testing/selftests/bpf/progs/verifier_movsx.c
+++ b/tools/testing/selftests/bpf/progs/verifier_movsx.c
@@ -4,7 +4,7 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("MOV32SX, S8")
diff --git a/tools/testing/selftests/bpf/progs/verifier_sdiv.c b/tools/testing/selftests/bpf/progs/verifier_sdiv.c
index f61a9a1058c8..fa3945930e93 100644
--- a/tools/testing/selftests/bpf/progs/verifier_sdiv.c
+++ b/tools/testing/selftests/bpf/progs/verifier_sdiv.c
@@ -4,7 +4,7 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("SDIV32, non-zero imm divisor, check 1")
-- 
2.30.2

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for arm64

[Yonghong Song]

On 8/15/23 8:41 AM, Xu Kuohai wrote:
> From: Xu Kuohai <xukuohai@huawei.com>
> 
> Enable cpu v4 instruction tests for arm64.
> 
> Signed-off-by: Xu Kuohai <xukuohai@huawei.com>

Thanks for adding cpu v4 support for arm64. The CI looks green as well 
for arm64.

https://github.com/kernel-patches/bpf/actions/runs/5868919914/job/15912774884?pr=5525

Ack this patch which enabled cpu v4 tests for arm64.

Acked-by: Yonghong Song <yonghong.song@linux.dev>

> ---
>   tools/testing/selftests/bpf/progs/test_ldsx_insn.c | 2 +-
>   tools/testing/selftests/bpf/progs/verifier_bswap.c | 2 +-
>   tools/testing/selftests/bpf/progs/verifier_gotol.c | 2 +-
>   tools/testing/selftests/bpf/progs/verifier_ldsx.c  | 2 +-
>   tools/testing/selftests/bpf/progs/verifier_movsx.c | 2 +-
>   tools/testing/selftests/bpf/progs/verifier_sdiv.c  | 2 +-
>   6 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
> index 321abf862801..916d9435f12c 100644
> --- a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
> +++ b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
> @@ -5,7 +5,7 @@
>   #include <bpf/bpf_helpers.h>
>   #include <bpf/bpf_tracing.h>
>   
> -#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
> +#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
>   const volatile int skip = 0;
>   #else
>   const volatile int skip = 1;
[...]

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for arm64

[Xu Kuohai]

On 8/16/2023 12:57 AM, Yonghong Song wrote:
> 
> 
> On 8/15/23 8:41 AM, Xu Kuohai wrote:
>> From: Xu Kuohai <xukuohai@huawei.com>
>>
>> Enable cpu v4 instruction tests for arm64.
>>
>> Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
> 
> Thanks for adding cpu v4 support for arm64. The CI looks green as well for arm64.
> 
> https://github.com/kernel-patches/bpf/actions/runs/5868919914/job/15912774884?pr=5525
>

Well, it looks like the CI's clang doesn't support cpu v4 yet:

   #306/1   verifier_bswap/cpuv4 is not supported by compiler or jit, use a dummy test:OK
   #306     verifier_bswap:OK

> Ack this patch which enabled cpu v4 tests for arm64.
> 
> Acked-by: Yonghong Song <yonghong.song@linux.dev>
> 
>> ---
>>   tools/testing/selftests/bpf/progs/test_ldsx_insn.c | 2 +-
>>   tools/testing/selftests/bpf/progs/verifier_bswap.c | 2 +-
>>   tools/testing/selftests/bpf/progs/verifier_gotol.c | 2 +-
>>   tools/testing/selftests/bpf/progs/verifier_ldsx.c  | 2 +-
>>   tools/testing/selftests/bpf/progs/verifier_movsx.c | 2 +-
>>   tools/testing/selftests/bpf/progs/verifier_sdiv.c  | 2 +-
>>   6 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>> index 321abf862801..916d9435f12c 100644
>> --- a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>> +++ b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>> @@ -5,7 +5,7 @@
>>   #include <bpf/bpf_helpers.h>
>>   #include <bpf/bpf_tracing.h>
>> -#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
>> +#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
>>   const volatile int skip = 0;
>>   #else
>>   const volatile int skip = 1;
> [...]
> 
> .

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for arm64

[Yonghong Song]

On 8/15/23 6:28 PM, Xu Kuohai wrote:
> On 8/16/2023 12:57 AM, Yonghong Song wrote:
>>
>>
>> On 8/15/23 8:41 AM, Xu Kuohai wrote:
>>> From: Xu Kuohai <xukuohai@huawei.com>
>>>
>>> Enable cpu v4 instruction tests for arm64.
>>>
>>> Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
>>
>> Thanks for adding cpu v4 support for arm64. The CI looks green as well 
>> for arm64.
>>
>> https://github.com/kernel-patches/bpf/actions/runs/5868919914/job/15912774884?pr=5525
>>
> 
> Well, it looks like the CI's clang doesn't support cpu v4 yet:
> 
>    #306/1   verifier_bswap/cpuv4 is not supported by compiler or jit, 
> use a dummy test:OK
>    #306     verifier_bswap:OK
> 
>> Ack this patch which enabled cpu v4 tests for arm64.

Ah. Sorry. Could you paste your local cpu v4 run results for
these related tests in the commit message then?

>>
>> Acked-by: Yonghong Song <yonghong.song@linux.dev>
>>
>>> ---
>>>   tools/testing/selftests/bpf/progs/test_ldsx_insn.c | 2 +-
>>>   tools/testing/selftests/bpf/progs/verifier_bswap.c | 2 +-
>>>   tools/testing/selftests/bpf/progs/verifier_gotol.c | 2 +-
>>>   tools/testing/selftests/bpf/progs/verifier_ldsx.c  | 2 +-
>>>   tools/testing/selftests/bpf/progs/verifier_movsx.c | 2 +-
>>>   tools/testing/selftests/bpf/progs/verifier_sdiv.c  | 2 +-
>>>   6 files changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c 
>>> b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>>> index 321abf862801..916d9435f12c 100644
>>> --- a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>>> +++ b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>>> @@ -5,7 +5,7 @@
>>>   #include <bpf/bpf_helpers.h>
>>>   #include <bpf/bpf_tracing.h>
>>> -#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
>>> +#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && 
>>> __clang_major__ >= 18
>>>   const volatile int skip = 0;
>>>   #else
>>>   const volatile int skip = 1;
>> [...]
>>
>> .
> 

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for arm64

[Xu Kuohai]

On 8/16/2023 9:57 AM, Yonghong Song wrote:
> 
> 
> On 8/15/23 6:28 PM, Xu Kuohai wrote:
>> On 8/16/2023 12:57 AM, Yonghong Song wrote:
>>>
>>>
>>> On 8/15/23 8:41 AM, Xu Kuohai wrote:
>>>> From: Xu Kuohai <xukuohai@huawei.com>
>>>>
>>>> Enable cpu v4 instruction tests for arm64.
>>>>
>>>> Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
>>>
>>> Thanks for adding cpu v4 support for arm64. The CI looks green as well for arm64.
>>>
>>> https://github.com/kernel-patches/bpf/actions/runs/5868919914/job/15912774884?pr=5525
>>>
>>
>> Well, it looks like the CI's clang doesn't support cpu v4 yet:
>>
>>    #306/1   verifier_bswap/cpuv4 is not supported by compiler or jit, use a dummy test:OK
>>    #306     verifier_bswap:OK
>>
>>> Ack this patch which enabled cpu v4 tests for arm64.
> 
> Ah. Sorry. Could you paste your local cpu v4 run results for
> these related tests in the commit message then?
> 

Sure. The results are as follows. I'll post these in the commit message.

# ./test_progs -t ldsx_insn,verifier_sdiv,verifier_movsx,verifier_ldsx,verifier_gotol,verifier_bswap
#115/1   ldsx_insn/map_val and probed_memory:OK
#115/2   ldsx_insn/ctx_member_sign_ext:OK
#115/3   ldsx_insn/ctx_member_narrow_sign_ext:OK
#115     ldsx_insn:OK
#302/1   verifier_bswap/BSWAP, 16:OK
#302/2   verifier_bswap/BSWAP, 16 @unpriv:OK
#302/3   verifier_bswap/BSWAP, 32:OK
#302/4   verifier_bswap/BSWAP, 32 @unpriv:OK
#302/5   verifier_bswap/BSWAP, 64:OK
#302/6   verifier_bswap/BSWAP, 64 @unpriv:OK
#302     verifier_bswap:OK
#316/1   verifier_gotol/gotol, small_imm:OK
#316/2   verifier_gotol/gotol, small_imm @unpriv:OK
#316     verifier_gotol:OK
#324/1   verifier_ldsx/LDSX, S8:OK
#324/2   verifier_ldsx/LDSX, S8 @unpriv:OK
#324/3   verifier_ldsx/LDSX, S16:OK
#324/4   verifier_ldsx/LDSX, S16 @unpriv:OK
#324/5   verifier_ldsx/LDSX, S32:OK
#324/6   verifier_ldsx/LDSX, S32 @unpriv:OK
#324/7   verifier_ldsx/LDSX, S8 range checking, privileged:OK
#324/8   verifier_ldsx/LDSX, S16 range checking:OK
#324/9   verifier_ldsx/LDSX, S16 range checking @unpriv:OK
#324/10  verifier_ldsx/LDSX, S32 range checking:OK
#324/11  verifier_ldsx/LDSX, S32 range checking @unpriv:OK
#324     verifier_ldsx:OK
#335/1   verifier_movsx/MOV32SX, S8:OK
#335/2   verifier_movsx/MOV32SX, S8 @unpriv:OK
#335/3   verifier_movsx/MOV32SX, S16:OK
#335/4   verifier_movsx/MOV32SX, S16 @unpriv:OK
#335/5   verifier_movsx/MOV64SX, S8:OK
#335/6   verifier_movsx/MOV64SX, S8 @unpriv:OK
#335/7   verifier_movsx/MOV64SX, S16:OK
#335/8   verifier_movsx/MOV64SX, S16 @unpriv:OK
#335/9   verifier_movsx/MOV64SX, S32:OK
#335/10  verifier_movsx/MOV64SX, S32 @unpriv:OK
#335/11  verifier_movsx/MOV32SX, S8, range_check:OK
#335/12  verifier_movsx/MOV32SX, S8, range_check @unpriv:OK
#335/13  verifier_movsx/MOV32SX, S16, range_check:OK
#335/14  verifier_movsx/MOV32SX, S16, range_check @unpriv:OK
#335/15  verifier_movsx/MOV32SX, S16, range_check 2:OK
#335/16  verifier_movsx/MOV32SX, S16, range_check 2 @unpriv:OK
#335/17  verifier_movsx/MOV64SX, S8, range_check:OK
#335/18  verifier_movsx/MOV64SX, S8, range_check @unpriv:OK
#335/19  verifier_movsx/MOV64SX, S16, range_check:OK
#335/20  verifier_movsx/MOV64SX, S16, range_check @unpriv:OK
#335/21  verifier_movsx/MOV64SX, S32, range_check:OK
#335/22  verifier_movsx/MOV64SX, S32, range_check @unpriv:OK
#335/23  verifier_movsx/MOV64SX, S16, R10 Sign Extension:OK
#335/24  verifier_movsx/MOV64SX, S16, R10 Sign Extension @unpriv:OK
#335     verifier_movsx:OK
#347/1   verifier_sdiv/SDIV32, non-zero imm divisor, check 1:OK
#347/2   verifier_sdiv/SDIV32, non-zero imm divisor, check 1 @unpriv:OK
#347/3   verifier_sdiv/SDIV32, non-zero imm divisor, check 2:OK
#347/4   verifier_sdiv/SDIV32, non-zero imm divisor, check 2 @unpriv:OK
#347/5   verifier_sdiv/SDIV32, non-zero imm divisor, check 3:OK
#347/6   verifier_sdiv/SDIV32, non-zero imm divisor, check 3 @unpriv:OK
#347/7   verifier_sdiv/SDIV32, non-zero imm divisor, check 4:OK
#347/8   verifier_sdiv/SDIV32, non-zero imm divisor, check 4 @unpriv:OK
#347/9   verifier_sdiv/SDIV32, non-zero imm divisor, check 5:OK
#347/10  verifier_sdiv/SDIV32, non-zero imm divisor, check 5 @unpriv:OK
#347/11  verifier_sdiv/SDIV32, non-zero imm divisor, check 6:OK
#347/12  verifier_sdiv/SDIV32, non-zero imm divisor, check 6 @unpriv:OK
#347/13  verifier_sdiv/SDIV32, non-zero imm divisor, check 7:OK
#347/14  verifier_sdiv/SDIV32, non-zero imm divisor, check 7 @unpriv:OK
#347/15  verifier_sdiv/SDIV32, non-zero imm divisor, check 8:OK
#347/16  verifier_sdiv/SDIV32, non-zero imm divisor, check 8 @unpriv:OK
#347/17  verifier_sdiv/SDIV32, non-zero reg divisor, check 1:OK
#347/18  verifier_sdiv/SDIV32, non-zero reg divisor, check 1 @unpriv:OK
#347/19  verifier_sdiv/SDIV32, non-zero reg divisor, check 2:OK
#347/20  verifier_sdiv/SDIV32, non-zero reg divisor, check 2 @unpriv:OK
#347/21  verifier_sdiv/SDIV32, non-zero reg divisor, check 3:OK
#347/22  verifier_sdiv/SDIV32, non-zero reg divisor, check 3 @unpriv:OK
#347/23  verifier_sdiv/SDIV32, non-zero reg divisor, check 4:OK
#347/24  verifier_sdiv/SDIV32, non-zero reg divisor, check 4 @unpriv:OK
#347/25  verifier_sdiv/SDIV32, non-zero reg divisor, check 5:OK
#347/26  verifier_sdiv/SDIV32, non-zero reg divisor, check 5 @unpriv:OK
#347/27  verifier_sdiv/SDIV32, non-zero reg divisor, check 6:OK
#347/28  verifier_sdiv/SDIV32, non-zero reg divisor, check 6 @unpriv:OK
#347/29  verifier_sdiv/SDIV32, non-zero reg divisor, check 7:OK
#347/30  verifier_sdiv/SDIV32, non-zero reg divisor, check 7 @unpriv:OK
#347/31  verifier_sdiv/SDIV32, non-zero reg divisor, check 8:OK
#347/32  verifier_sdiv/SDIV32, non-zero reg divisor, check 8 @unpriv:OK
#347/33  verifier_sdiv/SDIV64, non-zero imm divisor, check 1:OK
#347/34  verifier_sdiv/SDIV64, non-zero imm divisor, check 1 @unpriv:OK
#347/35  verifier_sdiv/SDIV64, non-zero imm divisor, check 2:OK
#347/36  verifier_sdiv/SDIV64, non-zero imm divisor, check 2 @unpriv:OK
#347/37  verifier_sdiv/SDIV64, non-zero imm divisor, check 3:OK
#347/38  verifier_sdiv/SDIV64, non-zero imm divisor, check 3 @unpriv:OK
#347/39  verifier_sdiv/SDIV64, non-zero imm divisor, check 4:OK
#347/40  verifier_sdiv/SDIV64, non-zero imm divisor, check 4 @unpriv:OK
#347/41  verifier_sdiv/SDIV64, non-zero imm divisor, check 5:OK
#347/42  verifier_sdiv/SDIV64, non-zero imm divisor, check 5 @unpriv:OK
#347/43  verifier_sdiv/SDIV64, non-zero imm divisor, check 6:OK
#347/44  verifier_sdiv/SDIV64, non-zero imm divisor, check 6 @unpriv:OK
#347/45  verifier_sdiv/SDIV64, non-zero reg divisor, check 1:OK
#347/46  verifier_sdiv/SDIV64, non-zero reg divisor, check 1 @unpriv:OK
#347/47  verifier_sdiv/SDIV64, non-zero reg divisor, check 2:OK
#347/48  verifier_sdiv/SDIV64, non-zero reg divisor, check 2 @unpriv:OK
#347/49  verifier_sdiv/SDIV64, non-zero reg divisor, check 3:OK
#347/50  verifier_sdiv/SDIV64, non-zero reg divisor, check 3 @unpriv:OK
#347/51  verifier_sdiv/SDIV64, non-zero reg divisor, check 4:OK
#347/52  verifier_sdiv/SDIV64, non-zero reg divisor, check 4 @unpriv:OK
#347/53  verifier_sdiv/SDIV64, non-zero reg divisor, check 5:OK
#347/54  verifier_sdiv/SDIV64, non-zero reg divisor, check 5 @unpriv:OK
#347/55  verifier_sdiv/SDIV64, non-zero reg divisor, check 6:OK
#347/56  verifier_sdiv/SDIV64, non-zero reg divisor, check 6 @unpriv:OK
#347/57  verifier_sdiv/SMOD32, non-zero imm divisor, check 1:OK
#347/58  verifier_sdiv/SMOD32, non-zero imm divisor, check 1 @unpriv:OK
#347/59  verifier_sdiv/SMOD32, non-zero imm divisor, check 2:OK
#347/60  verifier_sdiv/SMOD32, non-zero imm divisor, check 2 @unpriv:OK
#347/61  verifier_sdiv/SMOD32, non-zero imm divisor, check 3:OK
#347/62  verifier_sdiv/SMOD32, non-zero imm divisor, check 3 @unpriv:OK
#347/63  verifier_sdiv/SMOD32, non-zero imm divisor, check 4:OK
#347/64  verifier_sdiv/SMOD32, non-zero imm divisor, check 4 @unpriv:OK
#347/65  verifier_sdiv/SMOD32, non-zero imm divisor, check 5:OK
#347/66  verifier_sdiv/SMOD32, non-zero imm divisor, check 5 @unpriv:OK
#347/67  verifier_sdiv/SMOD32, non-zero imm divisor, check 6:OK
#347/68  verifier_sdiv/SMOD32, non-zero imm divisor, check 6 @unpriv:OK
#347/69  verifier_sdiv/SMOD32, non-zero reg divisor, check 1:OK
#347/70  verifier_sdiv/SMOD32, non-zero reg divisor, check 1 @unpriv:OK
#347/71  verifier_sdiv/SMOD32, non-zero reg divisor, check 2:OK
#347/72  verifier_sdiv/SMOD32, non-zero reg divisor, check 2 @unpriv:OK
#347/73  verifier_sdiv/SMOD32, non-zero reg divisor, check 3:OK
#347/74  verifier_sdiv/SMOD32, non-zero reg divisor, check 3 @unpriv:OK
#347/75  verifier_sdiv/SMOD32, non-zero reg divisor, check 4:OK
#347/76  verifier_sdiv/SMOD32, non-zero reg divisor, check 4 @unpriv:OK
#347/77  verifier_sdiv/SMOD32, non-zero reg divisor, check 5:OK
#347/78  verifier_sdiv/SMOD32, non-zero reg divisor, check 5 @unpriv:OK
#347/79  verifier_sdiv/SMOD32, non-zero reg divisor, check 6:OK
#347/80  verifier_sdiv/SMOD32, non-zero reg divisor, check 6 @unpriv:OK
#347/81  verifier_sdiv/SMOD64, non-zero imm divisor, check 1:OK
#347/82  verifier_sdiv/SMOD64, non-zero imm divisor, check 1 @unpriv:OK
#347/83  verifier_sdiv/SMOD64, non-zero imm divisor, check 2:OK
#347/84  verifier_sdiv/SMOD64, non-zero imm divisor, check 2 @unpriv:OK
#347/85  verifier_sdiv/SMOD64, non-zero imm divisor, check 3:OK
#347/86  verifier_sdiv/SMOD64, non-zero imm divisor, check 3 @unpriv:OK
#347/87  verifier_sdiv/SMOD64, non-zero imm divisor, check 4:OK
#347/88  verifier_sdiv/SMOD64, non-zero imm divisor, check 4 @unpriv:OK
#347/89  verifier_sdiv/SMOD64, non-zero imm divisor, check 5:OK
#347/90  verifier_sdiv/SMOD64, non-zero imm divisor, check 5 @unpriv:OK
#347/91  verifier_sdiv/SMOD64, non-zero imm divisor, check 6:OK
#347/92  verifier_sdiv/SMOD64, non-zero imm divisor, check 6 @unpriv:OK
#347/93  verifier_sdiv/SMOD64, non-zero imm divisor, check 7:OK
#347/94  verifier_sdiv/SMOD64, non-zero imm divisor, check 7 @unpriv:OK
#347/95  verifier_sdiv/SMOD64, non-zero imm divisor, check 8:OK
#347/96  verifier_sdiv/SMOD64, non-zero imm divisor, check 8 @unpriv:OK
#347/97  verifier_sdiv/SMOD64, non-zero reg divisor, check 1:OK
#347/98  verifier_sdiv/SMOD64, non-zero reg divisor, check 1 @unpriv:OK
#347/99  verifier_sdiv/SMOD64, non-zero reg divisor, check 2:OK
#347/100 verifier_sdiv/SMOD64, non-zero reg divisor, check 2 @unpriv:OK
#347/101 verifier_sdiv/SMOD64, non-zero reg divisor, check 3:OK
#347/102 verifier_sdiv/SMOD64, non-zero reg divisor, check 3 @unpriv:OK
#347/103 verifier_sdiv/SMOD64, non-zero reg divisor, check 4:OK
#347/104 verifier_sdiv/SMOD64, non-zero reg divisor, check 4 @unpriv:OK
#347/105 verifier_sdiv/SMOD64, non-zero reg divisor, check 5:OK
#347/106 verifier_sdiv/SMOD64, non-zero reg divisor, check 5 @unpriv:OK
#347/107 verifier_sdiv/SMOD64, non-zero reg divisor, check 6:OK
#347/108 verifier_sdiv/SMOD64, non-zero reg divisor, check 6 @unpriv:OK
#347/109 verifier_sdiv/SMOD64, non-zero reg divisor, check 7:OK
#347/110 verifier_sdiv/SMOD64, non-zero reg divisor, check 7 @unpriv:OK
#347/111 verifier_sdiv/SMOD64, non-zero reg divisor, check 8:OK
#347/112 verifier_sdiv/SMOD64, non-zero reg divisor, check 8 @unpriv:OK
#347/113 verifier_sdiv/SDIV32, zero divisor:OK
#347/114 verifier_sdiv/SDIV32, zero divisor @unpriv:OK
#347/115 verifier_sdiv/SDIV64, zero divisor:OK
#347/116 verifier_sdiv/SDIV64, zero divisor @unpriv:OK
#347/117 verifier_sdiv/SMOD32, zero divisor:OK
#347/118 verifier_sdiv/SMOD32, zero divisor @unpriv:OK
#347/119 verifier_sdiv/SMOD64, zero divisor:OK
#347/120 verifier_sdiv/SMOD64, zero divisor @unpriv:OK
#347     verifier_sdiv:OK
Summary: 6/166 PASSED, 0 SKIPPED, 0 FAILED

>>>
>>> Acked-by: Yonghong Song <yonghong.song@linux.dev>
>>>
>>>> ---
>>>>   tools/testing/selftests/bpf/progs/test_ldsx_insn.c | 2 +-
>>>>   tools/testing/selftests/bpf/progs/verifier_bswap.c | 2 +-
>>>>   tools/testing/selftests/bpf/progs/verifier_gotol.c | 2 +-
>>>>   tools/testing/selftests/bpf/progs/verifier_ldsx.c  | 2 +-
>>>>   tools/testing/selftests/bpf/progs/verifier_movsx.c | 2 +-
>>>>   tools/testing/selftests/bpf/progs/verifier_sdiv.c  | 2 +-
>>>>   6 files changed, 6 insertions(+), 6 deletions(-)
>>>>
>>>> diff --git a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>>>> index 321abf862801..916d9435f12c 100644
>>>> --- a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>>>> +++ b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
>>>> @@ -5,7 +5,7 @@
>>>>   #include <bpf/bpf_helpers.h>
>>>>   #include <bpf/bpf_tracing.h>
>>>> -#if defined(__TARGET_ARCH_x86) && __clang_major__ >= 18
>>>> +#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
>>>>   const volatile int skip = 0;
>>>>   #else
>>>>   const volatile int skip = 1;
>>> [...]
>>>
>>> .
>>
> 
> .

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for arm64

[Daniel Borkmann]

On 8/16/23 4:31 AM, Xu Kuohai wrote:
> On 8/16/2023 9:57 AM, Yonghong Song wrote:
>> On 8/15/23 6:28 PM, Xu Kuohai wrote:
>>> On 8/16/2023 12:57 AM, Yonghong Song wrote:
>>>> On 8/15/23 8:41 AM, Xu Kuohai wrote:
>>>>> From: Xu Kuohai <xukuohai@huawei.com>
>>>>>
>>>>> Enable cpu v4 instruction tests for arm64.
>>>>>
>>>>> Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
>>>>
>>>> Thanks for adding cpu v4 support for arm64. The CI looks green as well for arm64.
>>>>
>>>> https://github.com/kernel-patches/bpf/actions/runs/5868919914/job/15912774884?pr=5525
>>>
>>> Well, it looks like the CI's clang doesn't support cpu v4 yet:
>>>
>>>    #306/1   verifier_bswap/cpuv4 is not supported by compiler or jit, use a dummy test:OK
>>>    #306     verifier_bswap:OK
>>>
>>>> Ack this patch which enabled cpu v4 tests for arm64.
>>
>> Ah. Sorry. Could you paste your local cpu v4 run results for
>> these related tests in the commit message then?
> 
> Sure. The results are as follows. I'll post these in the commit message.

Thanks, I've added these to the commit message given Florent's review and
tests came in.

Yonghong, did you ping all other JIT folks as well, so they are aware and have
a chance to look into adding support for their archs?

Thanks,
Daniel

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for arm64

[Yonghong Song]

On 8/18/23 7:04 AM, Daniel Borkmann wrote:
> On 8/16/23 4:31 AM, Xu Kuohai wrote:
>> On 8/16/2023 9:57 AM, Yonghong Song wrote:
>>> On 8/15/23 6:28 PM, Xu Kuohai wrote:
>>>> On 8/16/2023 12:57 AM, Yonghong Song wrote:
>>>>> On 8/15/23 8:41 AM, Xu Kuohai wrote:
>>>>>> From: Xu Kuohai <xukuohai@huawei.com>
>>>>>>
>>>>>> Enable cpu v4 instruction tests for arm64.
>>>>>>
>>>>>> Signed-off-by: Xu Kuohai <xukuohai@huawei.com>
>>>>>
>>>>> Thanks for adding cpu v4 support for arm64. The CI looks green as 
>>>>> well for arm64.
>>>>>
>>>>> https://github.com/kernel-patches/bpf/actions/runs/5868919914/job/15912774884?pr=5525
>>>>
>>>> Well, it looks like the CI's clang doesn't support cpu v4 yet:
>>>>
>>>>    #306/1   verifier_bswap/cpuv4 is not supported by compiler or 
>>>> jit, use a dummy test:OK
>>>>    #306     verifier_bswap:OK
>>>>
>>>>> Ack this patch which enabled cpu v4 tests for arm64.
>>>
>>> Ah. Sorry. Could you paste your local cpu v4 run results for
>>> these related tests in the commit message then?
>>
>> Sure. The results are as follows. I'll post these in the commit message.
> 
> Thanks, I've added these to the commit message given Florent's review and
> tests came in.
> 
> Yonghong, did you ping all other JIT folks as well, so they are aware 
> and have
> a chance to look into adding support for their archs?

Thanks, Daniel for reminder. Will ping them soon to get
cpu v4 support for other arch's as well.

> 
> Thanks,
> Daniel
> 

Re: [PATCH bpf-next 0/7] Support cpu v4 instructions for arm64

[Florent Revest]

On Tue, Aug 15, 2023 at 5:21 PM Xu Kuohai <xukuohai@huaweicloud.com> wrote:
>
> From: Xu Kuohai <xukuohai@huawei.com>
>
> This series adds arm64 support for cpu v4 instructions [1].
>
> [1] https://lore.kernel.org/all/20230728011143.3710005-1-yonghong.song@linux.dev/
>
> Xu Kuohai (7):
>   arm64: insn: Add encoders for LDRSB/LDRSH/LDRSW
>   bpf, arm64: Support sign-extension load instructions
>   bpf, arm64: Support sign-extension mov instructions
>   bpf, arm64: Support unconditional bswap
>   bpf, arm64: Support 32-bit offset jmp instruction
>   bpf, arm64: Support signed div/mod instructions
>   selftests/bpf: Enable cpu v4 tests for arm64

Thank you Xu! The series looks good to me so:

Acked-by: Florent Revest <revest@chromium.org>

And I could reproduce your successful test runs with a recent clang so:

Tested-by: Florent Revest <revest@chromium.org>

Re: [PATCH bpf-next 0/7] Support cpu v4 instructions for arm64

[patchwork-bot+netdevbpf]

Hello:

This series was applied to bpf/bpf-next.git (master)
by Daniel Borkmann <daniel@iogearbox.net>:

On Tue, 15 Aug 2023 11:41:51 -0400 you wrote:
> From: Xu Kuohai <xukuohai@huawei.com>
> 
> This series adds arm64 support for cpu v4 instructions [1].
> 
> [1] https://lore.kernel.org/all/20230728011143.3710005-1-yonghong.song@linux.dev/
> 
> Xu Kuohai (7):
>   arm64: insn: Add encoders for LDRSB/LDRSH/LDRSW
>   bpf, arm64: Support sign-extension load instructions
>   bpf, arm64: Support sign-extension mov instructions
>   bpf, arm64: Support unconditional bswap
>   bpf, arm64: Support 32-bit offset jmp instruction
>   bpf, arm64: Support signed div/mod instructions
>   selftests/bpf: Enable cpu v4 tests for arm64
> 
> [...]

Here is the summary with links:
  - [bpf-next,1/7] arm64: insn: Add encoders for LDRSB/LDRSH/LDRSW
    https://git.kernel.org/bpf/bpf-next/c/6c9f86d3632c
  - [bpf-next,2/7] bpf, arm64: Support sign-extension load instructions
    https://git.kernel.org/bpf/bpf-next/c/cc88f540da52
  - [bpf-next,3/7] bpf, arm64: Support sign-extension mov instructions
    https://git.kernel.org/bpf/bpf-next/c/bb0a1d6b49cb
  - [bpf-next,4/7] bpf, arm64: Support unconditional bswap
    https://git.kernel.org/bpf/bpf-next/c/1104247f3f97
  - [bpf-next,5/7] bpf, arm64: Support 32-bit offset jmp instruction
    https://git.kernel.org/bpf/bpf-next/c/c32b6ee514d2
  - [bpf-next,6/7] bpf, arm64: Support signed div/mod instructions
    https://git.kernel.org/bpf/bpf-next/c/68b18191fe41
  - [bpf-next,7/7] selftests/bpf: Enable cpu v4 tests for arm64
    https://git.kernel.org/bpf/bpf-next/c/5f6395fd0680

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html