Re: [PATCH bpf-next 2/5] riscv, bpf: Relax restrictions on Zbb instructions

["Stefan O'Rear" <sorear@fastmail.com>]

On Thu, Mar 28, 2024, at 8:49 AM, Pu Lehui wrote:
> From: Pu Lehui <pulehui@huawei.com>
>
> This patch relaxes the restrictions on the Zbb instructions. The hardware
> is capable of recognizing the Zbb instructions independently, eliminating
> the need for reliance on kernel compile configurations.

This doesn't make sense to me.

RISCV_ISA_ZBB is defined as:

           Adds support to dynamically detect the presence of the ZBB
           extension (basic bit manipulation) and enable its usage.

In other words, RISCV_ISA_ZBB=n should disable everything that attempts
to detect Zbb at runtime. It is mostly relevant for code size reduction,
which is relevant for BPF since if RISCV_ISA_ZBB=n all rvzbb_enabled()
checks can be constant-folded.

If BPF needs to become an exception (why?), this should be mentioned in
Kconfig.

-s

> Signed-off-by: Pu Lehui <pulehui@huawei.com>
> ---
>  arch/riscv/net/bpf_jit.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> index 5fc374ed98ea..bcf109b88df5 100644
> --- a/arch/riscv/net/bpf_jit.h
> +++ b/arch/riscv/net/bpf_jit.h
> @@ -20,7 +20,7 @@ static inline bool rvc_enabled(void)
> 
>  static inline bool rvzbb_enabled(void)
>  {
> -	return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && 
> riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
> +	return riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
>  }
> 
>  enum {
> -- 
> 2.34.1
>
>
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