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Tue, 18 Aug 2026 21:35:32 -0700 (PDT) Message-ID: <5f1b726cd88f2261f70a5aa99f94ea1434c078c1.camel@gmail.com> Subject: Re: [RFC bpf-next 0/6] bpf: track scalar equality across the low 32 bits From: Eduard Zingerman To: Vineet Gupta , ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, memxor@gmail.com Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, john.fastabend@gmail.com, shuah@kernel.org, bpf@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Date: Tue, 18 Aug 2026 21:35:30 -0700 In-Reply-To: <20260814231945.3884596-1-vineet.gupta@linux.dev> References: <20260814231945.3884596-1-vineet.gupta@linux.dev> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-10 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2026-08-14 at 16:19 -0700, Vineet Gupta wrote: > The verifier's linked-scalar machinery tracks register equality only for = the > full 64 bits (optionally with a constant delta). There is no way to recor= d > "these two registers share just their low 32 bits", so a 32-bit mov from = a > source with unknown high bits has to drop the relationship entirely, and = a > later narrowing of the source never reaches the destination: >=20 > > =C2=A0r6 =3D ...=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* full 64-bit= unknown */ > > =C2=A0w7 =3D w6=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* 32-bi= t zero-extending mov=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = */ > > =C2=A0if w6 !=3D 0 goto .Lxx=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = /* not taken: r6's low 32 bits are 0=C2=A0 */ > > =C2=A0if w7 =3D=3D 0 goto .Lok=C2=A0=C2=A0 <-- not deduced today >=20 > The same gap exists for the 32-bit sign extension and was the > motivation for this patchset. >=20 > > =C2=A00: (61) r2 =3D *(u32 *)(r1 +24) > > =C2=A01: (bf) r0 =3D (s32)r2 > > =C2=A02: (56) if w2 !=3D 0x0 goto pc+10=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 ; R2=3D0 (branch taken) > > =C2=A0=C2=A0=C2=A0 ... > > 12: (95) exit Note that ldx instructions have similar structure: one can either zero or sign extend on 32-bit load. I think this series should be expanded to cover these cases. Also, please drop RFC tag when submitting v2.