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Marchesi" To: Dave Thaler Cc: bpf , Alexei Starovoitov , "bpf@ietf.org" , David Vernet Subject: Re: [Bpf] [PATCH V3] bpf, docs: Document BPF insn encoding in term of stored bytes In-Reply-To: (Dave Thaler's message of "Mon, 27 Feb 2023 21:49:15 +0000") References: <877cw295u8.fsf@oracle.com> Date: Tue, 28 Feb 2023 02:05:03 +0100 Message-ID: <87v8jm7g74.fsf@oracle.com> User-Agent: Gnus/5.13 (Gnus v5.13) Content-Type: text/plain X-ClientProxiedBy: LO4P123CA0020.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:151::7) To BYAPR10MB2888.namprd10.prod.outlook.com (2603:10b6:a03:88::32) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR10MB2888:EE_|SN7PR10MB6644:EE_ X-MS-Office365-Filtering-Correlation-Id: fcab3bb8-1a32-42ed-c41e-08db1927d630 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tzvbhpZrS257WMj2O9RgoZ0YIxFDixj+M3e+1EhDY5zW20+NUTM3SnVSlZ2VGJvFzZpQ2lyK8j80+jn6t6HOBUvLdbps4qOOpsz7R7sR+4sRsv8IeqCL1B86ifXsBuXBvM2irY41vahSjbvxDBXgGkl8doTQupFvU3C6Yp//OJnxFD5W5GQp6CsF6Xdd+Udv/9dFKwq3VpZvVSlczQwXEdUyDL7QE8qlniyW/v5vLetYkM/H2g4lk9rLksC8/JFB/3Kl2Hi5QjFUjaa4PAFBCoyK/r/kRrNd5V7MIAjHeOElEGOoOdjb+cBWCsZ2O5qyVwAt7v+SeSug3WoOOghQA2n1FaTScHZh0XIW+HbQ5He07OldDCPyNpBgIHkdd4YSBuHSbMORseJnrNZ0tyqU2nBz4cbYkmK+fCoibktCBAXolEAip1wgxUkHH2O4+AcrA/zbNoMsfUKJ/gtcn7PHqO07xxg2tUEopoqap7jKJiGjlxyfM7W0IITyNQ3XCFKc9P7dsmgAyHSEs88NLHJ/Gr+4W+dRQ+GSvDQ+xnhZ33dW6Wkw1tmozzJwYdmnuQ6TKgRxMSzPfV19P2Nhy5eegWEh72e/HEK71hr8RLv1wo831LtCi4e6bVXis/aKowKsZtlLhT5t/rirYq4Z19kUUg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BYAPR10MB2888.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(396003)(39860400002)(346002)(136003)(376002)(366004)(451199018)(83380400001)(54906003)(316002)(36756003)(4326008)(6916009)(8676002)(38100700002)(6506007)(53546011)(2616005)(26005)(45080400002)(6666004)(478600001)(6512007)(6486002)(966005)(5660300002)(66476007)(66946007)(66556008)(2906002)(86362001)(41300700001)(186003)(8936002);DIR:OUT;SFP:1101; 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Marchesi >> Sent: Monday, February 27, 2023 1:06 PM >> To: bpf >> Cc: Alexei Starovoitov ; bpf@ietf.org; David >> Vernet >> Subject: [Bpf] [PATCH V3] bpf, docs: Document BPF insn encoding in term of >> stored bytes >> >> >> [Changes from V2: >> - Use src and dst consistently in the document. > > Since my earlier patch, src and dst refer to the values whereas > src_reg and dst_reg refer to register numbers. Oh, I didn't realize that! Yeah sure, resending with src_reg and dst_reg. >> - Use a more graphical depiction of the 128-bit instruction. >> - Remove `Where:' fragment. >> - Clarify that unused bits are reserved and shall be zeroed.] >> >> This patch modifies instruction-set.rst so it documents the encoding of BPF >> instructions in terms of how the bytes are stored (be it in an ELF file or as >> bytes in a memory buffer to be loaded into the kernel or some other BPF >> consumer) as opposed to how the instruction looks like once loaded. >> >> This is hopefully easier to understand by implementors looking to generate >> and/or consume bytes conforming BPF instructions. >> >> The patch also clarifies that the unused bytes in a pseudo-instruction shall be >> cleared with zeros. >> >> Signed-off-by: Jose E. Marchesi >> --- >> Documentation/bpf/instruction-set.rst | 63 ++++++++++++++------------- >> 1 file changed, 33 insertions(+), 30 deletions(-) >> >> diff --git a/Documentation/bpf/instruction-set.rst >> b/Documentation/bpf/instruction-set.rst >> index 01802ed9b29b..fae2e48d6a0b 100644 >> --- a/Documentation/bpf/instruction-set.rst >> +++ b/Documentation/bpf/instruction-set.rst >> @@ -38,15 +38,11 @@ eBPF has two instruction encodings: >> * the wide instruction encoding, which appends a second 64-bit immediate >> (i.e., >> constant) value after the basic instruction for a total of 128 bits. >> >> -The basic instruction encoding looks as follows for a little-endian processor, >> -where MSB and LSB mean the most significant bits and least significant bits, >> -respectively: >> +The fields conforming an encoded basic instruction are stored in the >> +following order:: >> >> -============= ======= ======= ======= ============ >> -32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) >> -============= ======= ======= ======= ============ >> -imm offset src_reg dst_reg opcode >> -============= ======= ======= ======= ============ >> + opcode:8 src:4 dst:4 offset:16 imm:32 // In little-endian BPF. >> + opcode:8 dst:4 src:4 offset:16 imm:32 // In big-endian BPF. > > I think those should be src_reg and dst_reg (as the register numbers) > not src and dst (which are the values) or this will be a documentation > regression. > > Right now I think this is a regression since if I understand right, with this > patch, "src" and "dst" now refer to both in different places which is > confusing. > > Dave > >> **imm** >> signed integer immediate value >> @@ -54,48 +50,55 @@ imm offset src_reg dst_reg opcode >> **offset** >> signed integer offset used with pointer arithmetic >> >> -**src_reg** >> +**src** >> the source register number (0-10), except where otherwise specified >> (`64-bit immediate instructions`_ reuse this field for other purposes) >> >> -**dst_reg** >> +**dst** >> destination register number (0-10) >> >> **opcode** >> operation to perform >> >> -and as follows for a big-endian processor: >> +Note that the contents of multi-byte fields ('imm' and 'offset') are >> +stored using big-endian byte ordering in big-endian BPF and >> +little-endian byte ordering in little-endian BPF. >> >> -============= ======= ======= ======= ============ >> -32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) >> -============= ======= ======= ======= ============ >> -imm offset dst_reg src_reg opcode >> -============= ======= ======= ======= ============ >> +For example:: >> >> -Multi-byte fields ('imm' and 'offset') are similarly stored in -the byte order of >> the processor. >> + opcode offset imm assembly >> + src dst >> + 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little >> + dst src >> + 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big >> >> Note that most instructions do not use all of the fields. >> Unused fields shall be cleared to zero. >> >> -As discussed below in `64-bit immediate instructions`_, a 64-bit immediate - >> instruction uses a 64-bit immediate value that is constructed as follows. >> -The 64 bits following the basic instruction contain a pseudo instruction - >> using the same format but with opcode, dst_reg, src_reg, and offset all set to >> zero, -and imm containing the high 32 bits of the immediate value. >> +As discussed below in `64-bit immediate instructions`_, a 64-bit >> +immediate instruction uses a 64-bit immediate value that is constructed >> +as follows. The 64 bits following the basic instruction contain a >> +pseudo instruction using the same format but with opcode, dst, src, and >> +offset all set to zero, and imm containing the high 32 bits of the >> +immediate value. >> >> -================= ================== >> -64 bits (MSB) 64 bits (LSB) >> -================= ================== >> -basic instruction pseudo instruction >> -================= ================== >> +This is depicted in the following figure:: >> + >> + basic_instruction >> + .-----------------------------. >> + | | >> + code:8 regs:16 offset:16 imm:32 unused:32 imm:32 >> + | | >> + '--------------' >> + pseudo instruction >> >> Thus the 64-bit immediate value is constructed as follows: >> >> imm64 = (next_imm << 32) | imm >> >> where 'next_imm' refers to the imm value of the pseudo instruction - >> following the basic instruction. >> +following the basic instruction. The unused bytes in the pseudo >> +instruction are reserved and shall be cleared to zero. >> >> Instruction classes >> ------------------- >> @@ -137,7 +140,7 @@ code source instruction class >> source value description >> ====== ===== ============================================== >> BPF_K 0x00 use 32-bit 'imm' value as source operand >> - BPF_X 0x08 use 'src_reg' register value as source operand >> + BPF_X 0x08 use 'src' register value as source operand >> ====== ===== ============================================== >> >> **instruction class** >> -- >> 2.30.2 >> >> -- >> Bpf mailing list >> Bpf@ietf.org >> https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww >> .ietf.org%2Fmailman%2Flistinfo%2Fbpf&data=05%7C01%7Cdthaler%40micro >> soft.com%7C65d83bf2fe834f73f84908db19067400%7C72f988bf86f141af91ab >> 2d7cd011db47%7C1%7C0%7C638131287757978381%7CUnknown%7CTWFpb >> GZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6 >> Mn0%3D%7C3000%7C%7C%7C&sdata=8il1%2B8I1T8GBqn3U%2B7YJehIKjS6s >> gvxTRWS2CTpg%2FZY%3D&reserved=0