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Thu, 09 Jul 2026 17:06:53 -0700 (PDT) Message-ID: <924164ae0869fd1463694a48286bbd7e9f1ced65.camel@gmail.com> Subject: Re: [PATCH bpf-next 03/12] bpf: Wire up JIT support for 16-byte kfunc returns From: Eduard Zingerman To: Yonghong Song , bpf@vger.kernel.org Cc: Alexei Starovoitov , Andrii Nakryiko , Daniel Borkmann , kernel-team@fb.com Date: Thu, 09 Jul 2026 17:06:50 -0700 In-Reply-To: <20260708200955.2156484-1-yonghong.song@linux.dev> References: <20260708200939.2153664-1-yonghong.song@linux.dev> <20260708200955.2156484-1-yonghong.song@linux.dev> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-10 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2026-07-08 at 13:09 -0700, Yonghong Song wrote: > Continue preparing <=3D16 byte aggregate return support by wiring up the = JIT > side of the R0:R2 return convention for kfuncs. >=20 > A kfunc returning more than 8 bytes (a small aggregate or an __int128) > hands the second half of the result back in RDX, the native x86-64 ABI's > second return register. BPF instead expects a 16-byte return in the > R0:R2 register pair. BPF R0 maps to RAX so it needs no move, but BPF R2 > maps to RSI, so emit a RDX->RSI move after a BPF_PSEUDO_KFUNC_CALL whose > function model reports ret_size > 8. >=20 > Placing the second return half into R2 is possible on any JIT, but it > needs architecture-specific JIT work. Rather than requiring every JIT to > implement it at once, add a bpf_jit_supports_kfunc_ret_reg_pair() > capability, defaulting to false in the generic core; an architecture opts > in once its JIT handles the R0:R2 pair, and the remaining ones are left > for future work. The verifier enforces it in bpf_add_kfunc_call(), > rejecting a kfunc whose return is larger than 8 bytes with -EOPNOTSUPP > when the JIT lacks the capability. Only x86, arm64 and riscv are > supported so far. >=20 > On arm64 and riscv the native second return register is already BPF R2 > (x1 in bpf2a64[] and a1 in regmap[] respectively), so the value is in the > R0:R2 register pair on return with no extra move, unlike x86 (RDX->RSI). > This has been tested on x86 and arm64. The riscv path is expected to work > by the same register-mapping reasoning as arm64 but has not been tested. >=20 > Signed-off-by: Yonghong Song > --- Acked-by: Eduard Zingerman [...]