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From: Fangrui Song <maskray@google.com>
To: Eduard Zingerman <eddyz87@gmail.com>
Cc: Yonghong Song <yhs@meta.com>, Yonghong Song <yhs@fb.com>,
	bpf@vger.kernel.org,  Alexei Starovoitov <ast@kernel.org>,
	Andrii Nakryiko <andrii@kernel.org>,
	 Daniel Borkmann <daniel@iogearbox.net>,
	kernel-team@fb.com
Subject: Re: [PATCH bpf-next v2 03/15] bpf: Support new sign-extension mov insns
Date: Wed, 19 Jul 2023 08:59:54 -0700	[thread overview]
Message-ID: <CAFP8O3+2dTqatr_of4faH2a9r2dm3e3MatFfXT2-JsYMJqOQ=A@mail.gmail.com> (raw)
In-Reply-To: <40a3d3842ee4fc3323bca7112dd832486b7bed4f.camel@gmail.com>

On Wed, Jul 19, 2023 at 5:53 AM Eduard Zingerman <eddyz87@gmail.com> wrote:
>
> On Tue, 2023-07-18 at 18:17 -0700, Yonghong Song wrote:
> [...]
> > > > > +static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg,
> > > > > +                          u32 src_reg)
> > > > > +{
> > > > > +       u8 *prog = *pprog;
> > > > > +
> > > > > +       if (is64) {
> > > > > +               /* movs[b,w,l]q dst, src */
> > > > > +               if (num_bits == 8)
> > > > > +                       EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe,
> > > > > +                             add_2reg(0xC0, src_reg, dst_reg));
> > > > > +               else if (num_bits == 16)
> > > > > +                       EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf,
> > > > > +                             add_2reg(0xC0, src_reg, dst_reg));
> > > > > +               else if (num_bits == 32)
> > > > > +                       EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63,
> > > > > +                             add_2reg(0xC0, src_reg, dst_reg));
> > > > > +       } else {
> > > > > +               /* movs[b,w]l dst, src */
> > > > > +               if (num_bits == 8) {
> > > > > +                       EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe,
> > > > > +                             add_2reg(0xC0, src_reg, dst_reg));
> > >
> > > Nit: As far as I understand 4-126 Vol. 2B of [1]
> > >       the 0x40 prefix (REX prefix) is optional here
> > >       (same as implemented below for num_bits == 16).
> >
> > I think 0x40 prefix at least neededif register is from R8 - R15?
>
> Yes, please see below.
>
> > I use this website to do asm/disasm experiments and did
> > try various combinations with first 8 and later 8 registers
> > and it seems correct results are generated.
>
> It seems all roads lead to that web-site, I used it as well :)
> Today I learned that the following could be used:
>
>   echo 'movsx rax,ax' | as -o /dev/null -aln -msyntax=intel -mnaked-reg
>
> Which opens a road to scripting experiments.

This internal tool from llvm-project may also be useful:)

llvm-mc -triple=x86_64 -show-inst -x86-asm-syntax=intel
-output-asm-variant=1 <<< 'movsx rax, ax'

> > >
> > > [1] https://cdrdv2.intel.com/v1/dl/getContent/671200
> > >
> > >
> > > > > +               } else if (num_bits == 16) {
> > > > > +                       if (is_ereg(dst_reg) || is_ereg(src_reg))
> > > > > +                               EMIT1(add_2mod(0x40, src_reg, dst_reg));
> > > > > +                       EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf,
> > >
> > > Nit: Basing on the same manual I don't understand why
> > >       add_2mod(0x0f, src_reg, dst_reg) is used, '0xf' should suffice
> > >       (but I tried it both ways and it works...).
> >
> >  From the above online assembler website.
> >
> > But I will check the doc to see whether it can be simplified.
>
> I tried all combinations of r0..r9 for 64/32-bit destinations,
> 32/16/8 sources [1]:
> - 0x40 based prefix is generated if any of the following is true:
>   - dst is 64 bit
>   - dst is ereg
>   - src is ereg
>   - dst is 32-bit and src is 'sil' (part of 'rsi', used for r2)
>     (!) This one is surprising and web-site shows the same results.
>         For example `movsx eax,sil` is encoded as `40 0F BE C6`,
>         disassembling `0F BE C6` (w/o prefix) gives `movsx eax,dh`.
> - opcodes:
>   - 63      64-bit dst, 32-bit src
>   - 0F BF   64-bit dst, 16-bit src
>   - 0F BE   64-bit dst,  8-bit src
>   - 0F BF   32-bit dst, 16-bit src (same as 64-bit dst)
>   - 0F BE   32-bit dst,  8-bit src (same as 64-bit dst)
>
> Script is at [2] (it is not particularly interesting, but in case if
> you want to tweak it).
>
> [1] https://gist.github.com/eddyz87/94b35fd89f023c43dd2480e196b28ea1
> [2] https://gist.github.com/eddyz87/60991379c547df11d30fa91901862227
>
> > > > > +                             add_2reg(0xC0, src_reg, dst_reg));
> > > > > +               }
> > > > > +       }
> > > > > +
> > > > > +       *pprog = prog;
> > > > > +}
> [...]



-- 
宋方睿

  reply	other threads:[~2023-07-19 16:00 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-13  6:07 [PATCH bpf-next v2 00/15] bpf: Support new insns from cpu v4 Yonghong Song
2023-07-13  6:07 ` [PATCH bpf-next v2 01/15] bpf: Support new sign-extension load insns Yonghong Song
2023-07-14 18:13   ` Alexei Starovoitov
2023-07-14 23:22     ` Yonghong Song
2023-07-17  1:39   ` Eduard Zingerman
2023-07-19  0:15   ` Eduard Zingerman
2023-07-19  2:28     ` Yonghong Song
2023-07-13  6:07 ` [PATCH bpf-next v2 02/15] bpf: Fix sign-extension ctx member accesses Yonghong Song
2023-07-17  1:40   ` Eduard Zingerman
2023-07-19  0:40     ` Yonghong Song
2023-07-13  6:07 ` [PATCH bpf-next v2 03/15] bpf: Support new sign-extension mov insns Yonghong Song
2023-07-17  1:41   ` Eduard Zingerman
2023-07-19  1:17     ` Yonghong Song
2023-07-19 12:53       ` Eduard Zingerman
2023-07-19 15:59         ` Fangrui Song [this message]
2023-07-19 16:57           ` Eduard Zingerman
2023-07-13  6:07 ` [PATCH bpf-next v2 04/15] bpf: Support new unconditional bswap instruction Yonghong Song
2023-07-17  1:42   ` Eduard Zingerman
2023-07-19  1:22     ` Yonghong Song
2023-07-13  6:07 ` [PATCH bpf-next v2 05/15] bpf: Support new signed div/mod instructions Yonghong Song
2023-07-18 23:00   ` Eduard Zingerman
2023-07-19  2:30     ` Yonghong Song
2023-07-19  2:44       ` Alexei Starovoitov
2023-07-19  6:57         ` Yonghong Song
2023-07-13  6:07 ` [PATCH bpf-next v2 06/15] bpf: Fix jit blinding with new sdiv/smov insns Yonghong Song
2023-07-13  6:07 ` [PATCH bpf-next v2 07/15] bpf: Support new 32bit offset jmp instruction Yonghong Song
2023-07-13  6:08 ` [PATCH bpf-next v2 08/15] selftests/bpf: Add a cpuv4 test runner for cpu=v4 testing Yonghong Song
2023-07-13  6:18   ` Fangrui Song
2023-07-13  6:25     ` Yonghong Song
2023-07-13  6:08 ` [PATCH bpf-next v2 09/15] selftests/bpf: Add unit tests for new sign-extension load insns Yonghong Song
2023-07-18 23:06   ` Eduard Zingerman
2023-07-13  6:08 ` [PATCH bpf-next v2 10/15] selftests/bpf: Add unit tests for new sign-extension mov insns Yonghong Song
2023-07-13  6:08 ` [PATCH bpf-next v2 11/15] selftests/bpf: Add unit tests for new bswap insns Yonghong Song
2023-07-13  6:08 ` [PATCH bpf-next v2 12/15] selftests/bpf: Add unit tests for new sdiv/smod insns Yonghong Song
2023-07-18 23:10   ` Eduard Zingerman
2023-07-13  6:08 ` [PATCH bpf-next v2 13/15] selftests/bpf: Add unit tests for new gotol insn Yonghong Song
2023-07-13  6:08 ` [PATCH bpf-next v2 14/15] selftests/bpf: Test ldsx with more complex cases Yonghong Song
2023-07-13  6:08 ` [PATCH bpf-next v2 15/15] docs/bpf: Add documentation for new instructions Yonghong Song
2023-07-14 18:28   ` Alexei Starovoitov
2023-07-14 23:26     ` Yonghong Song
2023-07-14 23:33   ` Dave Thaler
2023-07-14 23:33     ` [Bpf] " Dave Thaler
2023-07-15  0:23     ` Alexei Starovoitov
2023-07-15  0:23       ` [Bpf] " Alexei Starovoitov
2023-07-14 23:34   ` Dave Thaler
2023-07-14 23:34     ` [Bpf] " Dave Thaler
2023-07-17  1:39 ` [PATCH bpf-next v2 00/15] bpf: Support new insns from cpu v4 Eduard Zingerman
2023-07-17 16:56   ` Alexei Starovoitov
2023-07-17 17:04     ` Eduard Zingerman
2023-07-17 21:52   ` Yonghong Song
2023-07-21 14:56     ` Jose E. Marchesi
2023-07-24  0:17       ` Jose E. Marchesi
2023-07-24  1:04         ` Jose E. Marchesi
2023-07-24  2:35           ` Yonghong Song

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