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Wed, 28 Oct 2026 11:41:06 -0700 (PDT) Received: from localhost ([153.61.198.243]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ae6e9b1506sm582040a91.15.2026.10.28.11.41.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Oct 2026 11:41:05 -0700 (PDT) Content-Type: text/plain; charset=UTF-8 Date: Wed, 28 Oct 2026 18:41:05 +0000 Message-Id: To: "Daniel Borkmann" , Cc: , Subject: Re: [PATCH bpf-next 19/21] bpf, arm64: Split 24-bit immediates of add, sub and equality compares From: "Alexei Starovoitov" In-Reply-To: <20261027182445.1156335-20-daniel@iogearbox.net> References: <20261027182445.1156335-1-daniel@iogearbox.net> <20261027182445.1156335-20-daniel@iogearbox.net> Content-Transfer-Encoding: 8bit X-Mailing-List: bpf@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 On Tue, Oct 27, 2026 at 11:24 AM Daniel Borkmann wrote: > An add, sub or compare with an immediate that neither the plain nor the > shifted 12-bit field takes moved the immediate into a register first, > two moves for most immediates up to 24 bits and then the add. Take two > adds or subs instead, of the upper 12 bits shifted and of the lower 12: > an instruction fewer, at a cycle more on the path of the operand, as the > two depend on each other where the moves did not, so an immediate that a > single move produces keeps the move. A compare for equality takes the > upper 12 bits off into a scratch register and compares against the lower > 12, as the subtraction keeps equality. [...] > arch/arm64/net/bpf_jit_comp.c | 113 ++++++++++++++++++++++------------ > 1 file changed, 74 insertions(+), 39 deletions(-) hmm Can we drop this patch? It saves 4 bytes and adds a cycle of latency? Doesn't seem worth it.