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[2001:1ae9:1c2:4c00:726e:c10f:8833:ff22]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5cf79c1de36sm4352338a12.84.2024.11.18.01.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2024 01:29:12 -0800 (PST) From: Jiri Olsa X-Google-Original-From: Jiri Olsa Date: Mon, 18 Nov 2024 10:29:09 +0100 To: Peter Zijlstra Cc: Oleg Nesterov , Andrii Nakryiko , bpf@vger.kernel.org, Song Liu , Yonghong Song , John Fastabend , Hao Luo , Steven Rostedt , Masami Hiramatsu , Alan Maguire , linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org, Will Deacon , Mark Rutland Subject: Re: [RFC 00/11] uprobes: Add support to optimize usdt probes on x86_64 Message-ID: References: <20241105133405.2703607-1-jolsa@kernel.org> <20241117114946.GD27667@noisy.programming.kicks-ass.net> Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241117114946.GD27667@noisy.programming.kicks-ass.net> On Sun, Nov 17, 2024 at 12:49:46PM +0100, Peter Zijlstra wrote: > On Tue, Nov 05, 2024 at 02:33:54PM +0100, Jiri Olsa wrote: > > hi, > > this patchset adds support to optimize usdt probes on top of 5-byte > > nop instruction. > > > > The generic approach (optimize all uprobes) is hard due to emulating > > possible multiple original instructions and its related issues. The > > usdt case, which stores 5-byte nop seems much easier, so starting > > with that. > > > > The basic idea is to replace breakpoint exception with syscall which > > is faster on x86_64. For more details please see changelog of patch 7. > > So this is really about the fact that syscalls are faster than traps on > x86_64? Is there something similar on ARM64, or are they roughly the > same speed there? yes, I recall somebody was porting uretprobe syscall to arm, but there was no speed up IIRC, so looks like it's not the case on arm I can't find the post atm, I'll keep digging jirka > > That is, I don't think this scheme will work for the various RISC > architectures, given their very limited immediate range turns a typical > call into a multi-instruction trainwreck real quick. > > Now, that isn't a problem if their exceptions and syscalls are of equal > speed.