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Tue, 02 Jul 2024 13:44:00 -0700 (PDT) Received: from [192.168.0.31] ([38.34.87.7]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac1535b94sm88718585ad.155.2024.07.02.13.44.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 13:44:00 -0700 (PDT) Message-ID: Subject: Re: [RFC bpf-next v1 3/8] bpf, x86: no_caller_saved_registers for bpf_get_smp_processor_id() From: Eduard Zingerman To: Andrii Nakryiko Cc: bpf@vger.kernel.org, ast@kernel.org, andrii@kernel.org, daniel@iogearbox.net, martin.lau@linux.dev, kernel-team@fb.com, yonghong.song@linux.dev, jose.marchesi@oracle.com Date: Tue, 02 Jul 2024 13:43:55 -0700 In-Reply-To: References: <20240629094733.3863850-1-eddyz87@gmail.com> <20240629094733.3863850-4-eddyz87@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4-0ubuntu2 Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2024-07-01 at 17:41 -0700, Andrii Nakryiko wrote: [...] > > @@ -158,6 +158,7 @@ const struct bpf_func_proto bpf_get_smp_processor_i= d_proto =3D { > > .func =3D bpf_get_smp_processor_id, > > .gpl_only =3D false, > > .ret_type =3D RET_INTEGER, > > + .nocsr =3D true, >=20 > I'm wondering if we should call this flag in such a way that it's > clear that this is more of an request, while the actual nocsr cleanup > and stuff is done only if BPF verifier/BPF JIT support that for > specific architecture/config/etc? Can change to .allow_nocsr. On the other hand, can remove this flag completely and rely on call_csr_mask(). [...] > > @@ -16030,7 +16030,14 @@ static u8 get_helper_reg_mask(const struct bpf= _func_proto *fn) > > */ > > static bool verifier_inlines_helper_call(struct bpf_verifier_env *env,= s32 imm) > > { > > - return false; > > + switch (imm) { > > +#ifdef CONFIG_X86_64 > > + case BPF_FUNC_get_smp_processor_id: > > + return env->prog->jit_requested && bpf_jit_supports_per= cpu_insn(); > > +#endif >=20 > please see bpf_jit_inlines_helper_call(), arm64 and risc-v inline it > in JIT, so we need to validate they don't assume any of R1-R5 register > to be a scratch register At the moment I return false for this archs. Or do you suggest these to be added in the current patch-set? [...]