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Wed, 17 Feb 2021 18:30:27 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 08297A4055; Wed, 17 Feb 2021 18:30:27 +0000 (GMT) Received: from [9.171.64.123] (unknown [9.171.64.123]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 17 Feb 2021 18:30:26 +0000 (GMT) Message-ID: Subject: Re: [PATCH v3 bpf-next] bpf: Explicitly zero-extend R0 after 32-bit cmpxchg From: Ilya Leoshkevich To: Brendan Jackman , bpf@vger.kernel.org Cc: Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Florent Revest Date: Wed, 17 Feb 2021 19:30:26 +0100 In-Reply-To: <20210217092831.2366396-1-jackmanb@google.com> References: <20210217092831.2366396-1-jackmanb@google.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.38.3 (3.38.3-1.fc33) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.761 definitions=2021-02-17_13:2021-02-16,2021-02-17 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2102170131 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org On Wed, 2021-02-17 at 09:28 +0000, Brendan Jackman wrote: > As pointed out by Ilya and explained in the new comment, there's a > discrepancy between x86 and BPF CMPXCHG semantics: BPF always loads > the value from memory into r0, while x86 only does so when r0 and the > value in memory are different. The same issue affects s390. > > At first this might sound like pure semantics, but it makes a real > difference when the comparison is 32-bit, since the load will > zero-extend r0/rax. > > The fix is to explicitly zero-extend rax after doing such a > CMPXCHG. Since this problem affects multiple archs, this is done in > the verifier by patching in a BPF_ZEXT_REG instruction after every > 32-bit cmpxchg. Any archs that don't need such manual zero-extension > can do a look-ahead with insn_is_zext to skip the unnecessary mov. > > Reported-by: Ilya Leoshkevich > Fixes: 5ffa25502b5a ("bpf: Add instructions for atomic_[cmp]xchg") > Signed-off-by: Brendan Jackman > --- > > Differences v2->v3[1]: >  - Moved patching into fixup_bpf_calls (patch incoming to rename this > function) >  - Added extra commentary on bpf_jit_needs_zext >  - Added check to avoid adding a pointless zext(r0) if there's > already one there. > > Difference v1->v2[1]: Now solved centrally in the verifier instead of >   specifically for the x86 JIT. Thanks to Ilya and Daniel for the > suggestions! > > [1] v2: > https://lore.kernel.org/bpf/08669818-c99d-0d30-e1db-53160c063611@iogearbox.net/T/#t >     v1: > https://lore.kernel.org/bpf/d7ebaefb-bfd6-a441-3ff2-2fdfe699b1d2@iogearbox.net/T/#t > >  kernel/bpf/core.c                             |  4 +++ >  kernel/bpf/verifier.c                         | 26 > +++++++++++++++++++ >  .../selftests/bpf/verifier/atomic_cmpxchg.c   | 25 > ++++++++++++++++++ >  .../selftests/bpf/verifier/atomic_or.c        | 26 > +++++++++++++++++++ >  4 files changed, 81 insertions(+) [...] > diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c > index 16ba43352a5f..a0d19be13558 100644 > --- a/kernel/bpf/verifier.c > +++ b/kernel/bpf/verifier.c > @@ -11662,6 +11662,32 @@ static int fixup_bpf_calls(struct > bpf_verifier_env *env) >                         continue; >                 } > > +               /* BPF_CMPXCHG always loads a value into R0, > therefore always > +                * zero-extends. However some archs' equivalent > instruction only > +                * does this load when the comparison is successful. > So here we > +                * add a BPF_ZEXT_REG after every 32-bit CMPXCHG, so > that such > +                * archs' JITs don't need to deal with the issue. > Archs that > +                * don't face this issue may use insn_is_zext to > detect and skip > +                * the added instruction. > +                */ > +               if (insn->code == (BPF_STX | BPF_W | BPF_ATOMIC) && > insn->imm == BPF_CMPXCHG) { > +                       struct bpf_insn zext_patch[2] = { [1] = > BPF_ZEXT_REG(BPF_REG_0) }; > + > +                       if (!memcmp(&insn[1], &zext_patch[1], > sizeof(struct bpf_insn))) > +                               /* Probably done by > opt_subreg_zext_lo32_rnd_hi32. */ > +                               continue; > + Isn't opt_subreg_zext_lo32_rnd_hi32() called after fixup_bpf_calls()? [...]