From: Karl Mehltretter <kmehltretter@gmail.com>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
netdev@vger.kernel.org
Cc: Karl Mehltretter <kmehltretter@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Alexei Starovoitov <ast@kernel.org>,
Daniel Borkmann <daniel@iogearbox.net>,
Jesper Dangaard Brouer <hawk@kernel.org>,
John Fastabend <john.fastabend@gmail.com>,
Stanislav Fomichev <sdf@fomichev.me>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Srinivas Kandagatla <srini@kernel.org>,
Ong Boon Leong <boon.leong.ong@intel.com>,
bpf@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH net 0/3] net: stmmac: fix DMA allocation and IRQ failure cleanup
Date: Wed, 14 Oct 2026 08:26:58 +0200 [thread overview]
Message-ID: <cover.1791958735.git.kmehltretter@gmail.com> (raw)
A DMA error-path review for the BeagleV Ahead found three bugs in the
common STMMAC code. Partial allocation can call buffer cleanup without
the metadata it indexes. A later TX allocation failure leaks the RX
resources allocated first. IRQ registration failure can release
descriptors and packet buffers while DMA remains active.
Patches 1 and 2 fix allocation cleanup. Patch 3 fixes the IRQ failure
unwind independently.
Testing:
- BeagleV Ahead, TH1520 DWMAC 3.70a: guarded baseline/fixed boots for RX
and TX allocation failures and normal-open IRQ failure. Baseline runs
reached the guarded unsafe boundaries. Fixed runs cleared the tracked
resources and stopped DMA before cleanup.
- A matched follow-up applied the same RTL8211F-VD resume repair to all
baseline and fixed kernels. At both 100 and 1000 Mbit/s, each variant
passed eight close/open cycles (32 total), delay-register checks,
pings and bidirectional 1 MiB SHA-256 transfers with no RX CRC or
DMA-API errors.
- Native-XDP IRQ failure was exercised on the same board. The baseline
reached IRQ unwind with DMA active and required a test-only rescue;
the fixed kernel stopped DMA before unwind. Both reached descriptor
cleanup with DMA inactive and no DMA-API errors.
- The physical native-XDP pair used CONFIG_BPF_JIT=n in both variants
to bypass an independent RISC-V execmem Oops after the STMMAC unwind.
The default configuration's XDP-open path remains covered by the QEMU
fault-injection matrix.
- The exact combined code passed 24 of 24 checked 64 MiB transfers on
fresh BeagleV Ahead boots with no DMA-API errors.
- QEMU orangepi-pc/dwmac-sun8i: 36 of 36 cold boots passed across the
allocation and IRQ matrices, including XDP-open IRQ failure.
- The exact combined code cross-built the STMMAC objects and BeagleV
Ahead DTB with a RISC-V defconfig and DWMAC_THEAD enabled.
The guards and fault-injection hooks are test-only and are not in this
series. The RTL8211F-VD repair is being submitted separately.
Based on 24a19b953e2a (Linux 7.3-rc7).
Karl Mehltretter (3):
net: stmmac: handle partially allocated DMA queues
net: stmmac: free RX resources when TX allocation fails
net: stmmac: stop DMA when IRQ registration fails
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 26 +++++++++++++++----
1 file changed, 21 insertions(+), 5 deletions(-)
base-commit: 24a19b953e2a3d0ea5a8c4951a0ab8f32720c907
--
2.39.5 (Apple Git-154)
next reply other threads:[~2026-10-14 6:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-14 6:26 Karl Mehltretter [this message]
2026-10-14 6:26 ` [PATCH net 1/3] net: stmmac: handle partially allocated DMA queues Karl Mehltretter
2026-10-14 11:36 ` Maxime Chevallier
2026-10-14 6:27 ` [PATCH net 2/3] net: stmmac: free RX resources when TX allocation fails Karl Mehltretter
2026-10-14 11:37 ` Maxime Chevallier
2026-10-14 6:27 ` [PATCH net 3/3] net: stmmac: stop DMA when IRQ registration fails Karl Mehltretter
2026-10-14 11:29 ` Daniel Machon
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