Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for RV64

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for RV64

[Yonghong Song]

On 8/23/23 4:10 PM, Pu Lehui wrote:
> From: Pu Lehui <pulehui@huawei.com>
> 
> Enable cpu v4 tests for RV64, and the relevant tests have passed.
> 
> Signed-off-by: Pu Lehui <pulehui@huawei.com>

Thanks for working on this!

Acked-by: Yonghong Song <yonghong.song@linux.dev>

> ---
>   tools/testing/selftests/bpf/progs/test_ldsx_insn.c | 3 ++-
>   tools/testing/selftests/bpf/progs/verifier_bswap.c | 3 ++-
>   tools/testing/selftests/bpf/progs/verifier_gotol.c | 3 ++-
>   tools/testing/selftests/bpf/progs/verifier_ldsx.c  | 3 ++-
>   tools/testing/selftests/bpf/progs/verifier_movsx.c | 3 ++-
>   tools/testing/selftests/bpf/progs/verifier_sdiv.c  | 3 ++-
>   6 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
> index 916d9435f12c..67c14ba1e87b 100644
> --- a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
> +++ b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
> @@ -5,7 +5,8 @@
>   #include <bpf/bpf_helpers.h>
>   #include <bpf/bpf_tracing.h>
>   
> -#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
> +#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
> +     (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64)) && __clang_major__ >= 18
>   const volatile int skip = 0;
>   #else
>   const volatile int skip = 1;
[...]

Re: [PATCH bpf-next 3/7] riscv, bpf: Support sign-extension mov insns

[Björn Töpel]

Pu Lehui <pulehui@huaweicloud.com> writes:

> From: Pu Lehui <pulehui@huawei.com>
>
> Add support sign-extension mov instructions for RV64.
>
> Signed-off-by: Pu Lehui <pulehui@huawei.com>
> ---
>  arch/riscv/net/bpf_jit_comp64.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index fd36cb17101a..d1497182cacf 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
>  			emit_zext_32(rd, ctx);
>  			break;
>  		}
> -		emit_mv(rd, rs, ctx);
> +		switch (insn->off) {
> +		case 0:
> +			emit_mv(rd, rs, ctx);
> +			break;
> +		case 8:
> +		case 16:
> +			emit_slli(rs, rs, 64 - insn->off, ctx);
> +			emit_srai(rd, rs, 64 - insn->off, ctx);

You're clobbering the source register (rs) here, which is correct.

(Side note: Maybe it's time to add Zbb support to the JIT soon! ;-))


Björn

Re: [PATCH bpf-next 2/7] riscv, bpf: Support sign-extension load insns

[Björn Töpel]

Pu Lehui <pulehui@huaweicloud.com> writes:

> From: Pu Lehui <pulehui@huawei.com>
>
> Add Support sign-extension load instructions for RV64.
>
> Signed-off-by: Pu Lehui <pulehui@huawei.com>

Acked-by: Björn Töpel <bjorn@kernel.org>

Re: [PATCH bpf-next 2/7] riscv, bpf: Support sign-extension load insns

[Björn Töpel]

Pu Lehui <pulehui@huaweicloud.com> writes:

> From: Pu Lehui <pulehui@huawei.com>
>
> Add Support sign-extension load instructions for RV64.
>
> Signed-off-by: Pu Lehui <pulehui@huawei.com>

Acked-by: Björn Töpel <bjorn@kernel.org>

Re: [PATCH bpf-next 4/7] riscv, bpf: Support 32-bit offset jmp insn

[Björn Töpel]

Pu Lehui <pulehui@huaweicloud.com> writes:

> From: Pu Lehui <pulehui@huawei.com>
>
> Add support 32-bit offset jmp instruction for RV64.
>
> Signed-off-by: Pu Lehui <pulehui@huawei.com>

Acked-by: Björn Töpel <bjorn@kernel.org>

Re: [PATCH bpf-next 5/7] riscv, bpf: Support signed div/mod insns

[Björn Töpel]

Pu Lehui <pulehui@huaweicloud.com> writes:

> From: Pu Lehui <pulehui@huawei.com>
>
> Add support signed div/mod instructions for RV64.
>
> Signed-off-by: Pu Lehui <pulehui@huawei.com>

Acked-by: Björn Töpel <bjorn@kernel.org>

Re: [PATCH bpf-next 6/7] riscv, bpf: Support unconditional bswap insn

[Björn Töpel]

Pu Lehui <pulehui@huaweicloud.com> writes:

> From: Pu Lehui <pulehui@huawei.com>
>
> Add support unconditional bswap instruction. Since riscv is always
> little-endian, just treat the unconditional scenario the same as
> big-endian conversion.
>
> Signed-off-by: Pu Lehui <pulehui@huawei.com>

Acked-by: Björn Töpel <bjorn@kernel.org>

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for RV64

[Björn Töpel]

Pu Lehui <pulehui@huaweicloud.com> writes:

> From: Pu Lehui <pulehui@huawei.com>
>
> Enable cpu v4 tests for RV64, and the relevant tests have passed.
>
> Signed-off-by: Pu Lehui <pulehui@huawei.com>

Acked-by: Björn Töpel <bjorn@kernel.org>

Re: [PATCH bpf-next 3/7] riscv, bpf: Support sign-extension mov insns

[Björn Töpel]

Björn Töpel <bjorn@kernel.org> writes:

> Pu Lehui <pulehui@huaweicloud.com> writes:
>
>> From: Pu Lehui <pulehui@huawei.com>
>>
>> Add support sign-extension mov instructions for RV64.
>>
>> Signed-off-by: Pu Lehui <pulehui@huawei.com>
>> ---
>>  arch/riscv/net/bpf_jit_comp64.c | 14 +++++++++++++-
>>  1 file changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
>> index fd36cb17101a..d1497182cacf 100644
>> --- a/arch/riscv/net/bpf_jit_comp64.c
>> +++ b/arch/riscv/net/bpf_jit_comp64.c
>> @@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
>>  			emit_zext_32(rd, ctx);
>>  			break;
>>  		}
>> -		emit_mv(rd, rs, ctx);
>> +		switch (insn->off) {
>> +		case 0:
>> +			emit_mv(rd, rs, ctx);
>> +			break;
>> +		case 8:
>> +		case 16:
>> +			emit_slli(rs, rs, 64 - insn->off, ctx);
>> +			emit_srai(rd, rs, 64 - insn->off, ctx);
>
> You're clobbering the source register (rs) here, which is correct.

Too quick! s/correct/incorrect/! :-)

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for RV64

[Alexei Starovoitov]

On Wed, Aug 23, 2023 at 11:25 AM Björn Töpel <bjorn@kernel.org> wrote:
>
> Pu Lehui <pulehui@huaweicloud.com> writes:
>
> > From: Pu Lehui <pulehui@huawei.com>
> >
> > Enable cpu v4 tests for RV64, and the relevant tests have passed.
> >
> > Signed-off-by: Pu Lehui <pulehui@huawei.com>
>
> Acked-by: Björn Töpel <bjorn@kernel.org>

Bjorn,

Thanks a lot for the quick review!
Could you give it a spin as well and hopefully add Tested-by ?

We still have time to get it into bpf-next for the upcoming merge window.

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for RV64

[Björn Töpel]

Alexei Starovoitov <alexei.starovoitov@gmail.com> writes:

> On Wed, Aug 23, 2023 at 11:25 AM Björn Töpel <bjorn@kernel.org> wrote:
>>
>> Pu Lehui <pulehui@huaweicloud.com> writes:
>>
>> > From: Pu Lehui <pulehui@huawei.com>
>> >
>> > Enable cpu v4 tests for RV64, and the relevant tests have passed.
>> >
>> > Signed-off-by: Pu Lehui <pulehui@huawei.com>
>>
>> Acked-by: Björn Töpel <bjorn@kernel.org>
>
> Bjorn,
>
> Thanks a lot for the quick review!
> Could you give it a spin as well and hopefully add Tested-by ?
>
> We still have time to get it into bpf-next for the upcoming merge window.

I'll kick a run! But I'd like a change to mov 8/16b patch (#3) prior
pulling.

> We still have time to get it into bpf-next for the upcoming merge window.

@Lehui Do you have time to cook a v2?


Björn

[PATCH bpf-next 0/7] Add support cpu v4 insns for RV64

[Pu Lehui]

Add support cpu v4 instructions for RV64. The relevant tests have passed as show bellow:

# ./test_progs-cpuv4 -a ldsx_insn,verifier_sdiv,verifier_movsx,verifier_ldsx,verifier_gotol,verifier_bswap
#116/1   ldsx_insn/map_val and probed_memory:OK
#116/2   ldsx_insn/ctx_member_sign_ext:OK
#116/3   ldsx_insn/ctx_member_narrow_sign_ext:OK
#116     ldsx_insn:OK
#309/1   verifier_bswap/BSWAP, 16:OK
#309/2   verifier_bswap/BSWAP, 16 @unpriv:OK
#309/3   verifier_bswap/BSWAP, 32:OK
#309/4   verifier_bswap/BSWAP, 32 @unpriv:OK
#309/5   verifier_bswap/BSWAP, 64:OK
#309/6   verifier_bswap/BSWAP, 64 @unpriv:OK
#309     verifier_bswap:OK
#323/1   verifier_gotol/gotol, small_imm:OK
#323/2   verifier_gotol/gotol, small_imm @unpriv:OK
#323     verifier_gotol:OK
#331/1   verifier_ldsx/LDSX, S8:OK
#331/2   verifier_ldsx/LDSX, S8 @unpriv:OK
#331/3   verifier_ldsx/LDSX, S16:OK
#331/4   verifier_ldsx/LDSX, S16 @unpriv:OK
#331/5   verifier_ldsx/LDSX, S32:OK
#331/6   verifier_ldsx/LDSX, S32 @unpriv:OK
#331/7   verifier_ldsx/LDSX, S8 range checking, privileged:OK
#331/8   verifier_ldsx/LDSX, S16 range checking:OK
#331/9   verifier_ldsx/LDSX, S16 range checking @unpriv:OK
#331/10  verifier_ldsx/LDSX, S32 range checking:OK
#331/11  verifier_ldsx/LDSX, S32 range checking @unpriv:OK
#331     verifier_ldsx:OK
#342/1   verifier_movsx/MOV32SX, S8:OK
#342/2   verifier_movsx/MOV32SX, S8 @unpriv:OK
#342/3   verifier_movsx/MOV32SX, S16:OK
#342/4   verifier_movsx/MOV32SX, S16 @unpriv:OK
#342/5   verifier_movsx/MOV64SX, S8:OK
#342/6   verifier_movsx/MOV64SX, S8 @unpriv:OK
#342/7   verifier_movsx/MOV64SX, S16:OK
#342/8   verifier_movsx/MOV64SX, S16 @unpriv:OK
#342/9   verifier_movsx/MOV64SX, S32:OK
#342/10  verifier_movsx/MOV64SX, S32 @unpriv:OK
#342/11  verifier_movsx/MOV32SX, S8, range_check:OK
#342/12  verifier_movsx/MOV32SX, S8, range_check @unpriv:OK
#342/13  verifier_movsx/MOV32SX, S16, range_check:OK
#342/14  verifier_movsx/MOV32SX, S16, range_check @unpriv:OK
#342/15  verifier_movsx/MOV32SX, S16, range_check 2:OK
#342/16  verifier_movsx/MOV32SX, S16, range_check 2 @unpriv:OK
#342/17  verifier_movsx/MOV64SX, S8, range_check:OK
#342/18  verifier_movsx/MOV64SX, S8, range_check @unpriv:OK
#342/19  verifier_movsx/MOV64SX, S16, range_check:OK
#342/20  verifier_movsx/MOV64SX, S16, range_check @unpriv:OK
#342/21  verifier_movsx/MOV64SX, S32, range_check:OK
#342/22  verifier_movsx/MOV64SX, S32, range_check @unpriv:OK
#342/23  verifier_movsx/MOV64SX, S16, R10 Sign Extension:OK
#342/24  verifier_movsx/MOV64SX, S16, R10 Sign Extension @unpriv:OK
#342     verifier_movsx:OK
#354/1   verifier_sdiv/SDIV32, non-zero imm divisor, check 1:OK
#354/2   verifier_sdiv/SDIV32, non-zero imm divisor, check 1 @unpriv:OK
#354/3   verifier_sdiv/SDIV32, non-zero imm divisor, check 2:OK
#354/4   verifier_sdiv/SDIV32, non-zero imm divisor, check 2 @unpriv:OK
#354/5   verifier_sdiv/SDIV32, non-zero imm divisor, check 3:OK
#354/6   verifier_sdiv/SDIV32, non-zero imm divisor, check 3 @unpriv:OK
#354/7   verifier_sdiv/SDIV32, non-zero imm divisor, check 4:OK
#354/8   verifier_sdiv/SDIV32, non-zero imm divisor, check 4 @unpriv:OK
#354/9   verifier_sdiv/SDIV32, non-zero imm divisor, check 5:OK
#354/10  verifier_sdiv/SDIV32, non-zero imm divisor, check 5 @unpriv:OK
#354/11  verifier_sdiv/SDIV32, non-zero imm divisor, check 6:OK
#354/12  verifier_sdiv/SDIV32, non-zero imm divisor, check 6 @unpriv:OK
#354/13  verifier_sdiv/SDIV32, non-zero imm divisor, check 7:OK
#354/14  verifier_sdiv/SDIV32, non-zero imm divisor, check 7 @unpriv:OK
#354/15  verifier_sdiv/SDIV32, non-zero imm divisor, check 8:OK
#354/16  verifier_sdiv/SDIV32, non-zero imm divisor, check 8 @unpriv:OK
#354/17  verifier_sdiv/SDIV32, non-zero reg divisor, check 1:OK
#354/18  verifier_sdiv/SDIV32, non-zero reg divisor, check 1 @unpriv:OK
#354/19  verifier_sdiv/SDIV32, non-zero reg divisor, check 2:OK
#354/20  verifier_sdiv/SDIV32, non-zero reg divisor, check 2 @unpriv:OK
#354/21  verifier_sdiv/SDIV32, non-zero reg divisor, check 3:OK
#354/22  verifier_sdiv/SDIV32, non-zero reg divisor, check 3 @unpriv:OK
#354/23  verifier_sdiv/SDIV32, non-zero reg divisor, check 4:OK
#354/24  verifier_sdiv/SDIV32, non-zero reg divisor, check 4 @unpriv:OK
#354/25  verifier_sdiv/SDIV32, non-zero reg divisor, check 5:OK
#354/26  verifier_sdiv/SDIV32, non-zero reg divisor, check 5 @unpriv:OK
#354/27  verifier_sdiv/SDIV32, non-zero reg divisor, check 6:OK
#354/28  verifier_sdiv/SDIV32, non-zero reg divisor, check 6 @unpriv:OK
#354/29  verifier_sdiv/SDIV32, non-zero reg divisor, check 7:OK
#354/30  verifier_sdiv/SDIV32, non-zero reg divisor, check 7 @unpriv:OK
#354/31  verifier_sdiv/SDIV32, non-zero reg divisor, check 8:OK
#354/32  verifier_sdiv/SDIV32, non-zero reg divisor, check 8 @unpriv:OK
#354/33  verifier_sdiv/SDIV64, non-zero imm divisor, check 1:OK
#354/34  verifier_sdiv/SDIV64, non-zero imm divisor, check 1 @unpriv:OK
#354/35  verifier_sdiv/SDIV64, non-zero imm divisor, check 2:OK
#354/36  verifier_sdiv/SDIV64, non-zero imm divisor, check 2 @unpriv:OK
#354/37  verifier_sdiv/SDIV64, non-zero imm divisor, check 3:OK
#354/38  verifier_sdiv/SDIV64, non-zero imm divisor, check 3 @unpriv:OK
#354/39  verifier_sdiv/SDIV64, non-zero imm divisor, check 4:OK
#354/40  verifier_sdiv/SDIV64, non-zero imm divisor, check 4 @unpriv:OK
#354/41  verifier_sdiv/SDIV64, non-zero imm divisor, check 5:OK
#354/42  verifier_sdiv/SDIV64, non-zero imm divisor, check 5 @unpriv:OK
#354/43  verifier_sdiv/SDIV64, non-zero imm divisor, check 6:OK
#354/44  verifier_sdiv/SDIV64, non-zero imm divisor, check 6 @unpriv:OK
#354/45  verifier_sdiv/SDIV64, non-zero reg divisor, check 1:OK
#354/46  verifier_sdiv/SDIV64, non-zero reg divisor, check 1 @unpriv:OK
#354/47  verifier_sdiv/SDIV64, non-zero reg divisor, check 2:OK
#354/48  verifier_sdiv/SDIV64, non-zero reg divisor, check 2 @unpriv:OK
#354/49  verifier_sdiv/SDIV64, non-zero reg divisor, check 3:OK
#354/50  verifier_sdiv/SDIV64, non-zero reg divisor, check 3 @unpriv:OK
#354/51  verifier_sdiv/SDIV64, non-zero reg divisor, check 4:OK
#354/52  verifier_sdiv/SDIV64, non-zero reg divisor, check 4 @unpriv:OK
#354/53  verifier_sdiv/SDIV64, non-zero reg divisor, check 5:OK
#354/54  verifier_sdiv/SDIV64, non-zero reg divisor, check 5 @unpriv:OK
#354/55  verifier_sdiv/SDIV64, non-zero reg divisor, check 6:OK
#354/56  verifier_sdiv/SDIV64, non-zero reg divisor, check 6 @unpriv:OK
#354/57  verifier_sdiv/SMOD32, non-zero imm divisor, check 1:OK
#354/58  verifier_sdiv/SMOD32, non-zero imm divisor, check 1 @unpriv:OK
#354/59  verifier_sdiv/SMOD32, non-zero imm divisor, check 2:OK
#354/60  verifier_sdiv/SMOD32, non-zero imm divisor, check 2 @unpriv:OK
#354/61  verifier_sdiv/SMOD32, non-zero imm divisor, check 3:OK
#354/62  verifier_sdiv/SMOD32, non-zero imm divisor, check 3 @unpriv:OK
#354/63  verifier_sdiv/SMOD32, non-zero imm divisor, check 4:OK
#354/64  verifier_sdiv/SMOD32, non-zero imm divisor, check 4 @unpriv:OK
#354/65  verifier_sdiv/SMOD32, non-zero imm divisor, check 5:OK
#354/66  verifier_sdiv/SMOD32, non-zero imm divisor, check 5 @unpriv:OK
#354/67  verifier_sdiv/SMOD32, non-zero imm divisor, check 6:OK
#354/68  verifier_sdiv/SMOD32, non-zero imm divisor, check 6 @unpriv:OK
#354/69  verifier_sdiv/SMOD32, non-zero reg divisor, check 1:OK
#354/70  verifier_sdiv/SMOD32, non-zero reg divisor, check 1 @unpriv:OK
#354/71  verifier_sdiv/SMOD32, non-zero reg divisor, check 2:OK
#354/72  verifier_sdiv/SMOD32, non-zero reg divisor, check 2 @unpriv:OK
#354/73  verifier_sdiv/SMOD32, non-zero reg divisor, check 3:OK
#354/74  verifier_sdiv/SMOD32, non-zero reg divisor, check 3 @unpriv:OK
#354/75  verifier_sdiv/SMOD32, non-zero reg divisor, check 4:OK
#354/76  verifier_sdiv/SMOD32, non-zero reg divisor, check 4 @unpriv:OK
#354/77  verifier_sdiv/SMOD32, non-zero reg divisor, check 5:OK
#354/78  verifier_sdiv/SMOD32, non-zero reg divisor, check 5 @unpriv:OK
#354/79  verifier_sdiv/SMOD32, non-zero reg divisor, check 6:OK
#354/80  verifier_sdiv/SMOD32, non-zero reg divisor, check 6 @unpriv:OK
#354/81  verifier_sdiv/SMOD64, non-zero imm divisor, check 1:OK
#354/82  verifier_sdiv/SMOD64, non-zero imm divisor, check 1 @unpriv:OK
#354/83  verifier_sdiv/SMOD64, non-zero imm divisor, check 2:OK
#354/84  verifier_sdiv/SMOD64, non-zero imm divisor, check 2 @unpriv:OK
#354/85  verifier_sdiv/SMOD64, non-zero imm divisor, check 3:OK
#354/86  verifier_sdiv/SMOD64, non-zero imm divisor, check 3 @unpriv:OK
#354/87  verifier_sdiv/SMOD64, non-zero imm divisor, check 4:OK
#354/88  verifier_sdiv/SMOD64, non-zero imm divisor, check 4 @unpriv:OK
#354/89  verifier_sdiv/SMOD64, non-zero imm divisor, check 5:OK
#354/90  verifier_sdiv/SMOD64, non-zero imm divisor, check 5 @unpriv:OK
#354/91  verifier_sdiv/SMOD64, non-zero imm divisor, check 6:OK
#354/92  verifier_sdiv/SMOD64, non-zero imm divisor, check 6 @unpriv:OK
#354/93  verifier_sdiv/SMOD64, non-zero imm divisor, check 7:OK
#354/94  verifier_sdiv/SMOD64, non-zero imm divisor, check 7 @unpriv:OK
#354/95  verifier_sdiv/SMOD64, non-zero imm divisor, check 8:OK
#354/96  verifier_sdiv/SMOD64, non-zero imm divisor, check 8 @unpriv:OK
#354/97  verifier_sdiv/SMOD64, non-zero reg divisor, check 1:OK
#354/98  verifier_sdiv/SMOD64, non-zero reg divisor, check 1 @unpriv:OK
#354/99  verifier_sdiv/SMOD64, non-zero reg divisor, check 2:OK
#354/100 verifier_sdiv/SMOD64, non-zero reg divisor, check 2 @unpriv:OK
#354/101 verifier_sdiv/SMOD64, non-zero reg divisor, check 3:OK
#354/102 verifier_sdiv/SMOD64, non-zero reg divisor, check 3 @unpriv:OK
#354/103 verifier_sdiv/SMOD64, non-zero reg divisor, check 4:OK
#354/104 verifier_sdiv/SMOD64, non-zero reg divisor, check 4 @unpriv:OK
#354/105 verifier_sdiv/SMOD64, non-zero reg divisor, check 5:OK
#354/106 verifier_sdiv/SMOD64, non-zero reg divisor, check 5 @unpriv:OK
#354/107 verifier_sdiv/SMOD64, non-zero reg divisor, check 6:OK
#354/108 verifier_sdiv/SMOD64, non-zero reg divisor, check 6 @unpriv:OK
#354/109 verifier_sdiv/SMOD64, non-zero reg divisor, check 7:OK
#354/110 verifier_sdiv/SMOD64, non-zero reg divisor, check 7 @unpriv:OK
#354/111 verifier_sdiv/SMOD64, non-zero reg divisor, check 8:OK
#354/112 verifier_sdiv/SMOD64, non-zero reg divisor, check 8 @unpriv:OK
#354/113 verifier_sdiv/SDIV32, zero divisor:OK
#354/114 verifier_sdiv/SDIV32, zero divisor @unpriv:OK
#354/115 verifier_sdiv/SDIV64, zero divisor:OK
#354/116 verifier_sdiv/SDIV64, zero divisor @unpriv:OK
#354/117 verifier_sdiv/SMOD32, zero divisor:OK
#354/118 verifier_sdiv/SMOD32, zero divisor @unpriv:OK
#354/119 verifier_sdiv/SMOD64, zero divisor:OK
#354/120 verifier_sdiv/SMOD64, zero divisor @unpriv:OK
#354     verifier_sdiv:OK
Summary: 6/166 PASSED, 0 SKIPPED, 0 FAILED

NOTE: ldsx_insn testcase uses fentry and needs to rely on ftrace direct call [0].
[0] https://lore.kernel.org/all/20230627111612.761164-1-suagrfillet@gmail.com/

Pu Lehui (7):
  riscv, bpf: Fix missing exception handling and redundant zext for
    LDX_B/H/W
  riscv, bpf: Support sign-extension load insns
  riscv, bpf: Support sign-extension mov insns
  riscv, bpf: Support 32-bit offset jmp insn
  riscv, bpf: Support signed div/mod insns
  riscv, bpf: Support unconditional bswap insn
  selftests/bpf: Enable cpu v4 tests for RV64

 arch/riscv/net/bpf_jit.h                      |  30 ++++++
 arch/riscv/net/bpf_jit_comp64.c               | 102 ++++++++++++++----
 .../selftests/bpf/progs/test_ldsx_insn.c      |   3 +-
 .../selftests/bpf/progs/verifier_bswap.c      |   3 +-
 .../selftests/bpf/progs/verifier_gotol.c      |   3 +-
 .../selftests/bpf/progs/verifier_ldsx.c       |   3 +-
 .../selftests/bpf/progs/verifier_movsx.c      |   3 +-
 .../selftests/bpf/progs/verifier_sdiv.c       |   3 +-
 8 files changed, 122 insertions(+), 28 deletions(-)

-- 
2.39.2

[PATCH bpf-next 1/7] riscv, bpf: Fix missing exception handling and redundant zext for LDX_B/H/W

[Pu Lehui]

From: Pu Lehui <pulehui@huawei.com>

For LDX_B/H/W, when zext has been inserted by verifier, it'll return 1,
and no exception handling will continue. Also, when the offset is 12-bit
value, the redundant zext inserted by the verifier is not removed. Fix
both scenarios by moving down the removal of redundant zext.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
---
 arch/riscv/net/bpf_jit_comp64.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index 0ca4f5c0097c..f2644e7ea6b5 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -1512,8 +1512,6 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 			insns_start = ctx->ninsns;
 			emit(rv_lbu(rd, 0, RV_REG_T1), ctx);
 			insn_len = ctx->ninsns - insns_start;
-			if (insn_is_zext(&insn[1]))
-				return 1;
 			break;
 		case BPF_H:
 			if (is_12b_int(off)) {
@@ -1528,8 +1526,6 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 			insns_start = ctx->ninsns;
 			emit(rv_lhu(rd, 0, RV_REG_T1), ctx);
 			insn_len = ctx->ninsns - insns_start;
-			if (insn_is_zext(&insn[1]))
-				return 1;
 			break;
 		case BPF_W:
 			if (is_12b_int(off)) {
@@ -1544,8 +1540,6 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 			insns_start = ctx->ninsns;
 			emit(rv_lwu(rd, 0, RV_REG_T1), ctx);
 			insn_len = ctx->ninsns - insns_start;
-			if (insn_is_zext(&insn[1]))
-				return 1;
 			break;
 		case BPF_DW:
 			if (is_12b_int(off)) {
@@ -1566,6 +1560,9 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 		ret = add_exception_handler(insn, ctx, rd, insn_len);
 		if (ret)
 			return ret;
+
+		if (BPF_SIZE(code) != BPF_DW && insn_is_zext(&insn[1]))
+			return 1;
 		break;
 	}
 	/* speculation barrier */
-- 
2.39.2

[PATCH bpf-next 2/7] riscv, bpf: Support sign-extension load insns

[Pu Lehui]

From: Pu Lehui <pulehui@huawei.com>

Add Support sign-extension load instructions for RV64.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
---
 arch/riscv/net/bpf_jit.h        | 10 +++++++
 arch/riscv/net/bpf_jit_comp64.c | 46 +++++++++++++++++++++++++++------
 2 files changed, 48 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index 2717f5490428..a52a3dda18c3 100644
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -501,6 +501,16 @@ static inline u32 rv_ble(u8 rs1, u8 rs2, u16 imm12_1)
 	return rv_bge(rs2, rs1, imm12_1);
 }
 
+static inline u32 rv_lb(u8 rd, u16 imm11_0, u8 rs1)
+{
+	return rv_i_insn(imm11_0, rs1, 0, rd, 0x03);
+}
+
+static inline u32 rv_lh(u8 rd, u16 imm11_0, u8 rs1)
+{
+	return rv_i_insn(imm11_0, rs1, 1, rd, 0x03);
+}
+
 static inline u32 rv_lw(u8 rd, u16 imm11_0, u8 rs1)
 {
 	return rv_i_insn(imm11_0, rs1, 2, rd, 0x03);
diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index f2644e7ea6b5..fd36cb17101a 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -580,7 +580,8 @@ static int add_exception_handler(const struct bpf_insn *insn,
 	unsigned long pc;
 	off_t offset;
 
-	if (!ctx->insns || !ctx->prog->aux->extable || BPF_MODE(insn->code) != BPF_PROBE_MEM)
+	if (!ctx->insns || !ctx->prog->aux->extable ||
+	    (BPF_MODE(insn->code) != BPF_PROBE_MEM && BPF_MODE(insn->code) != BPF_PROBE_MEMSX))
 		return 0;
 
 	if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries))
@@ -1486,7 +1487,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 		return 1;
 	}
 
-	/* LDX: dst = *(size *)(src + off) */
+	/* LDX: dst = *(unsigned size *)(src + off) */
 	case BPF_LDX | BPF_MEM | BPF_B:
 	case BPF_LDX | BPF_MEM | BPF_H:
 	case BPF_LDX | BPF_MEM | BPF_W:
@@ -1495,14 +1496,28 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 	case BPF_LDX | BPF_PROBE_MEM | BPF_H:
 	case BPF_LDX | BPF_PROBE_MEM | BPF_W:
 	case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
+	/* LDSX: dst = *(signed size *)(src + off) */
+	case BPF_LDX | BPF_MEMSX | BPF_B:
+	case BPF_LDX | BPF_MEMSX | BPF_H:
+	case BPF_LDX | BPF_MEMSX | BPF_W:
+	case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
+	case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
+	case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
 	{
 		int insn_len, insns_start;
+		bool sign_ext;
+
+		sign_ext = BPF_MODE(insn->code) == BPF_MEMSX ||
+			   BPF_MODE(insn->code) == BPF_PROBE_MEMSX;
 
 		switch (BPF_SIZE(code)) {
 		case BPF_B:
 			if (is_12b_int(off)) {
 				insns_start = ctx->ninsns;
-				emit(rv_lbu(rd, off, rs), ctx);
+				if (sign_ext)
+					emit(rv_lb(rd, off, rs), ctx);
+				else
+					emit(rv_lbu(rd, off, rs), ctx);
 				insn_len = ctx->ninsns - insns_start;
 				break;
 			}
@@ -1510,13 +1525,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 			emit_imm(RV_REG_T1, off, ctx);
 			emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
 			insns_start = ctx->ninsns;
-			emit(rv_lbu(rd, 0, RV_REG_T1), ctx);
+			if (sign_ext)
+				emit(rv_lb(rd, 0, RV_REG_T1), ctx);
+			else
+				emit(rv_lbu(rd, 0, RV_REG_T1), ctx);
 			insn_len = ctx->ninsns - insns_start;
 			break;
 		case BPF_H:
 			if (is_12b_int(off)) {
 				insns_start = ctx->ninsns;
-				emit(rv_lhu(rd, off, rs), ctx);
+				if (sign_ext)
+					emit(rv_lh(rd, off, rs), ctx);
+				else
+					emit(rv_lhu(rd, off, rs), ctx);
 				insn_len = ctx->ninsns - insns_start;
 				break;
 			}
@@ -1524,13 +1545,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 			emit_imm(RV_REG_T1, off, ctx);
 			emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
 			insns_start = ctx->ninsns;
-			emit(rv_lhu(rd, 0, RV_REG_T1), ctx);
+			if (sign_ext)
+				emit(rv_lh(rd, 0, RV_REG_T1), ctx);
+			else
+				emit(rv_lhu(rd, 0, RV_REG_T1), ctx);
 			insn_len = ctx->ninsns - insns_start;
 			break;
 		case BPF_W:
 			if (is_12b_int(off)) {
 				insns_start = ctx->ninsns;
-				emit(rv_lwu(rd, off, rs), ctx);
+				if (sign_ext)
+					emit(rv_lw(rd, off, rs), ctx);
+				else
+					emit(rv_lwu(rd, off, rs), ctx);
 				insn_len = ctx->ninsns - insns_start;
 				break;
 			}
@@ -1538,7 +1565,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 			emit_imm(RV_REG_T1, off, ctx);
 			emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
 			insns_start = ctx->ninsns;
-			emit(rv_lwu(rd, 0, RV_REG_T1), ctx);
+			if (sign_ext)
+				emit(rv_lw(rd, 0, RV_REG_T1), ctx);
+			else
+				emit(rv_lwu(rd, 0, RV_REG_T1), ctx);
 			insn_len = ctx->ninsns - insns_start;
 			break;
 		case BPF_DW:
-- 
2.39.2

[PATCH bpf-next 3/7] riscv, bpf: Support sign-extension mov insns

[Pu Lehui]

From: Pu Lehui <pulehui@huawei.com>

Add support sign-extension mov instructions for RV64.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
---
 arch/riscv/net/bpf_jit_comp64.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index fd36cb17101a..d1497182cacf 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 			emit_zext_32(rd, ctx);
 			break;
 		}
-		emit_mv(rd, rs, ctx);
+		switch (insn->off) {
+		case 0:
+			emit_mv(rd, rs, ctx);
+			break;
+		case 8:
+		case 16:
+			emit_slli(rs, rs, 64 - insn->off, ctx);
+			emit_srai(rd, rs, 64 - insn->off, ctx);
+			break;
+		case 32:
+			emit_addiw(rd, rs, 0, ctx);
+			break;
+		}
 		if (!is64 && !aux->verifier_zext)
 			emit_zext_32(rd, ctx);
 		break;
-- 
2.39.2

[PATCH bpf-next 4/7] riscv, bpf: Support 32-bit offset jmp insn

[Pu Lehui]

From: Pu Lehui <pulehui@huawei.com>

Add support 32-bit offset jmp instruction for RV64.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
---
 arch/riscv/net/bpf_jit_comp64.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index d1497182cacf..3d4e9182385d 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -1327,7 +1327,11 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 
 	/* JUMP off */
 	case BPF_JMP | BPF_JA:
-		rvoff = rv_offset(i, off, ctx);
+	case BPF_JMP32 | BPF_JA:
+		if (BPF_CLASS(code) == BPF_JMP)
+			rvoff = rv_offset(i, off, ctx);
+		else
+			rvoff = rv_offset(i, imm, ctx);
 		ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx);
 		if (ret)
 			return ret;
-- 
2.39.2

[PATCH bpf-next 5/7] riscv, bpf: Support signed div/mod insns

[Pu Lehui]

From: Pu Lehui <pulehui@huawei.com>

Add support signed div/mod instructions for RV64.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
---
 arch/riscv/net/bpf_jit.h        | 20 ++++++++++++++++++++
 arch/riscv/net/bpf_jit_comp64.c | 26 ++++++++++++++++++++------
 2 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index a52a3dda18c3..d21c6c92a683 100644
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -431,11 +431,21 @@ static inline u32 rv_mulhu(u8 rd, u8 rs1, u8 rs2)
 	return rv_r_insn(1, rs2, rs1, 3, rd, 0x33);
 }
 
+static inline u32 rv_div(u8 rd, u8 rs1, u8 rs2)
+{
+	return rv_r_insn(1, rs2, rs1, 4, rd, 0x33);
+}
+
 static inline u32 rv_divu(u8 rd, u8 rs1, u8 rs2)
 {
 	return rv_r_insn(1, rs2, rs1, 5, rd, 0x33);
 }
 
+static inline u32 rv_rem(u8 rd, u8 rs1, u8 rs2)
+{
+	return rv_r_insn(1, rs2, rs1, 6, rd, 0x33);
+}
+
 static inline u32 rv_remu(u8 rd, u8 rs1, u8 rs2)
 {
 	return rv_r_insn(1, rs2, rs1, 7, rd, 0x33);
@@ -776,11 +786,21 @@ static inline u32 rv_mulw(u8 rd, u8 rs1, u8 rs2)
 	return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b);
 }
 
+static inline u32 rv_divw(u8 rd, u8 rs1, u8 rs2)
+{
+	return rv_r_insn(1, rs2, rs1, 4, rd, 0x3b);
+}
+
 static inline u32 rv_divuw(u8 rd, u8 rs1, u8 rs2)
 {
 	return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b);
 }
 
+static inline u32 rv_remw(u8 rd, u8 rs1, u8 rs2)
+{
+	return rv_r_insn(1, rs2, rs1, 6, rd, 0x3b);
+}
+
 static inline u32 rv_remuw(u8 rd, u8 rs1, u8 rs2)
 {
 	return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b);
diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index 3d4e9182385d..027bd372c294 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -1107,13 +1107,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 		break;
 	case BPF_ALU | BPF_DIV | BPF_X:
 	case BPF_ALU64 | BPF_DIV | BPF_X:
-		emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx);
+		if (off)
+			emit(is64 ? rv_div(rd, rd, rs) : rv_divw(rd, rd, rs), ctx);
+		else
+			emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx);
 		if (!is64 && !aux->verifier_zext)
 			emit_zext_32(rd, ctx);
 		break;
 	case BPF_ALU | BPF_MOD | BPF_X:
 	case BPF_ALU64 | BPF_MOD | BPF_X:
-		emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx);
+		if (off)
+			emit(is64 ? rv_rem(rd, rd, rs) : rv_remw(rd, rd, rs), ctx);
+		else
+			emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx);
 		if (!is64 && !aux->verifier_zext)
 			emit_zext_32(rd, ctx);
 		break;
@@ -1284,16 +1290,24 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 	case BPF_ALU | BPF_DIV | BPF_K:
 	case BPF_ALU64 | BPF_DIV | BPF_K:
 		emit_imm(RV_REG_T1, imm, ctx);
-		emit(is64 ? rv_divu(rd, rd, RV_REG_T1) :
-		     rv_divuw(rd, rd, RV_REG_T1), ctx);
+		if (off)
+			emit(is64 ? rv_div(rd, rd, RV_REG_T1) :
+			     rv_divw(rd, rd, RV_REG_T1), ctx);
+		else
+			emit(is64 ? rv_divu(rd, rd, RV_REG_T1) :
+			     rv_divuw(rd, rd, RV_REG_T1), ctx);
 		if (!is64 && !aux->verifier_zext)
 			emit_zext_32(rd, ctx);
 		break;
 	case BPF_ALU | BPF_MOD | BPF_K:
 	case BPF_ALU64 | BPF_MOD | BPF_K:
 		emit_imm(RV_REG_T1, imm, ctx);
-		emit(is64 ? rv_remu(rd, rd, RV_REG_T1) :
-		     rv_remuw(rd, rd, RV_REG_T1), ctx);
+		if (off)
+			emit(is64 ? rv_rem(rd, rd, RV_REG_T1) :
+			     rv_remw(rd, rd, RV_REG_T1), ctx);
+		else
+			emit(is64 ? rv_remu(rd, rd, RV_REG_T1) :
+			     rv_remuw(rd, rd, RV_REG_T1), ctx);
 		if (!is64 && !aux->verifier_zext)
 			emit_zext_32(rd, ctx);
 		break;
-- 
2.39.2

[PATCH bpf-next 6/7] riscv, bpf: Support unconditional bswap insn

[Pu Lehui]

From: Pu Lehui <pulehui@huawei.com>

Add support unconditional bswap instruction. Since riscv is always
little-endian, just treat the unconditional scenario the same as
big-endian conversion.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
---
 arch/riscv/net/bpf_jit_comp64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index 027bd372c294..e9bd0d952901 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -1168,6 +1168,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
 		break;
 
 	case BPF_ALU | BPF_END | BPF_FROM_BE:
+	case BPF_ALU64 | BPF_END | BPF_FROM_LE:
 		emit_li(RV_REG_T2, 0, ctx);
 
 		emit_andi(RV_REG_T1, rd, 0xff, ctx);
-- 
2.39.2

[PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for RV64

[Pu Lehui]

From: Pu Lehui <pulehui@huawei.com>

Enable cpu v4 tests for RV64, and the relevant tests have passed.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
---
 tools/testing/selftests/bpf/progs/test_ldsx_insn.c | 3 ++-
 tools/testing/selftests/bpf/progs/verifier_bswap.c | 3 ++-
 tools/testing/selftests/bpf/progs/verifier_gotol.c | 3 ++-
 tools/testing/selftests/bpf/progs/verifier_ldsx.c  | 3 ++-
 tools/testing/selftests/bpf/progs/verifier_movsx.c | 3 ++-
 tools/testing/selftests/bpf/progs/verifier_sdiv.c  | 3 ++-
 6 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
index 916d9435f12c..67c14ba1e87b 100644
--- a/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
+++ b/tools/testing/selftests/bpf/progs/test_ldsx_insn.c
@@ -5,7 +5,8 @@
 #include <bpf/bpf_helpers.h>
 #include <bpf/bpf_tracing.h>
 
-#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+     (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64)) && __clang_major__ >= 18
 const volatile int skip = 0;
 #else
 const volatile int skip = 1;
diff --git a/tools/testing/selftests/bpf/progs/verifier_bswap.c b/tools/testing/selftests/bpf/progs/verifier_bswap.c
index 770f9d882542..8893094725f0 100644
--- a/tools/testing/selftests/bpf/progs/verifier_bswap.c
+++ b/tools/testing/selftests/bpf/progs/verifier_bswap.c
@@ -4,7 +4,8 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+     (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("BSWAP, 16")
diff --git a/tools/testing/selftests/bpf/progs/verifier_gotol.c b/tools/testing/selftests/bpf/progs/verifier_gotol.c
index 17319a505e87..2dae5322a18e 100644
--- a/tools/testing/selftests/bpf/progs/verifier_gotol.c
+++ b/tools/testing/selftests/bpf/progs/verifier_gotol.c
@@ -4,7 +4,8 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+     (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("gotol, small_imm")
diff --git a/tools/testing/selftests/bpf/progs/verifier_ldsx.c b/tools/testing/selftests/bpf/progs/verifier_ldsx.c
index 4a2b567c0f69..0c638f45aaf1 100644
--- a/tools/testing/selftests/bpf/progs/verifier_ldsx.c
+++ b/tools/testing/selftests/bpf/progs/verifier_ldsx.c
@@ -4,7 +4,8 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+     (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("LDSX, S8")
diff --git a/tools/testing/selftests/bpf/progs/verifier_movsx.c b/tools/testing/selftests/bpf/progs/verifier_movsx.c
index d9528d578bd9..3c8ac2c57b1b 100644
--- a/tools/testing/selftests/bpf/progs/verifier_movsx.c
+++ b/tools/testing/selftests/bpf/progs/verifier_movsx.c
@@ -4,7 +4,8 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+     (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("MOV32SX, S8")
diff --git a/tools/testing/selftests/bpf/progs/verifier_sdiv.c b/tools/testing/selftests/bpf/progs/verifier_sdiv.c
index fa3945930e93..0990f8825675 100644
--- a/tools/testing/selftests/bpf/progs/verifier_sdiv.c
+++ b/tools/testing/selftests/bpf/progs/verifier_sdiv.c
@@ -4,7 +4,8 @@
 #include <bpf/bpf_helpers.h>
 #include "bpf_misc.h"
 
-#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86)) && __clang_major__ >= 18
+#if (defined(__TARGET_ARCH_arm64) || defined(__TARGET_ARCH_x86) || \
+     (defined(__TARGET_ARCH_riscv) && __riscv_xlen == 64)) && __clang_major__ >= 18
 
 SEC("socket")
 __description("SDIV32, non-zero imm divisor, check 1")
-- 
2.39.2

Re: [PATCH bpf-next 3/7] riscv, bpf: Support sign-extension mov insns

[Pu Lehui]

On 2023/8/24 2:14, Björn Töpel wrote:
> Pu Lehui <pulehui@huaweicloud.com> writes:
> 
>> From: Pu Lehui <pulehui@huawei.com>
>>
>> Add support sign-extension mov instructions for RV64.
>>
>> Signed-off-by: Pu Lehui <pulehui@huawei.com>
>> ---
>>   arch/riscv/net/bpf_jit_comp64.c | 14 +++++++++++++-
>>   1 file changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
>> index fd36cb17101a..d1497182cacf 100644
>> --- a/arch/riscv/net/bpf_jit_comp64.c
>> +++ b/arch/riscv/net/bpf_jit_comp64.c
>> @@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
>>   			emit_zext_32(rd, ctx);
>>   			break;
>>   		}
>> -		emit_mv(rd, rs, ctx);
>> +		switch (insn->off) {
>> +		case 0:
>> +			emit_mv(rd, rs, ctx);
>> +			break;
>> +		case 8:
>> +		case 16:
>> +			emit_slli(rs, rs, 64 - insn->off, ctx);
>> +			emit_srai(rd, rs, 64 - insn->off, ctx);
> 
> You're clobbering the source register (rs) here, which is correct.

alright, will fix it

> 
> (Side note: Maybe it's time to add Zbb support to the JIT soon! ;-))
> 
> 
> Björn

Re: [PATCH bpf-next 7/7] selftests/bpf: Enable cpu v4 tests for RV64

[Pu Lehui]

On 2023/8/24 3:50, Björn Töpel wrote:
> Alexei Starovoitov <alexei.starovoitov@gmail.com> writes:
> 
>> On Wed, Aug 23, 2023 at 11:25 AM Björn Töpel <bjorn@kernel.org> wrote:
>>>
>>> Pu Lehui <pulehui@huaweicloud.com> writes:
>>>
>>>> From: Pu Lehui <pulehui@huawei.com>
>>>>
>>>> Enable cpu v4 tests for RV64, and the relevant tests have passed.
>>>>
>>>> Signed-off-by: Pu Lehui <pulehui@huawei.com>
>>>
>>> Acked-by: Björn Töpel <bjorn@kernel.org>
>>
>> Bjorn,
>>
>> Thanks a lot for the quick review!
>> Could you give it a spin as well and hopefully add Tested-by ?
>>
>> We still have time to get it into bpf-next for the upcoming merge window.
> 
> I'll kick a run! But I'd like a change to mov 8/16b patch (#3) prior
> pulling.
> 
>> We still have time to get it into bpf-next for the upcoming merge window.
> 
> @Lehui Do you have time to cook a v2?

Sorry guys for the late reply due to sleep. V2 is ready and will send soon.

> 
> 
> Björn