From: Daniel Borkmann <daniel@iogearbox.net>
To: KP Singh <kpsingh@kernel.org>, Ilya Leoshkevich <iii@linux.ibm.com>
Cc: Brendan Jackman <jackmanb@google.com>, bpf <bpf@vger.kernel.org>,
Alexei Starovoitov <ast@kernel.org>,
Andrii Nakryiko <andrii.nakryiko@gmail.com>,
Florent Revest <revest@chromium.org>
Subject: Re: [PATCH bpf-next] bpf: x86: Explicitly zero-extend rax after 32-bit cmpxchg
Date: Tue, 16 Feb 2021 01:43:30 +0100 [thread overview]
Message-ID: <d7ebaefb-bfd6-a441-3ff2-2fdfe699b1d2@iogearbox.net> (raw)
In-Reply-To: <CACYkzJ7-P4E71G-Ek_Hm5YQmvmYL_--K1dkm8pUZWbChgdjrfg@mail.gmail.com>
On 2/16/21 12:30 AM, KP Singh wrote:
> On Mon, Feb 15, 2021 at 11:42 PM Ilya Leoshkevich <iii@linux.ibm.com> wrote:
>>
>
> [...]
>
>>>>> How does the situation look on other archs when they need to
>>>>> implement this in future?
>>>>> Mainly asking whether it would be better to instead to move this
>>>>> logic into the verifier
>>>>> instead, so it'll be consistent across all archs.
>>>>
>>>> I have exactly the same check in my s390 wip patch.
>>>> So having a common solution would be great.
>>>
>>> We do rewrites for various cases like div/mod handling, perhaps would
>>> be
>>> best to emit an explicit BPF_MOV32_REG(insn->dst_reg, insn->dst_reg)
>>> there,
>>> see the fixup_bpf_calls().
>
> Agreed, this would be better.
>
>>
>> How about BPF_ZEXT_REG? Then arches that don't need this (I think
>> aarch64's instruction always zero-extends) can detect this using
>> insn_is_zext() and skip such insns.
>>
>
> +1
That would be nicer indeed.
prev parent reply other threads:[~2021-02-16 0:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-15 17:12 [PATCH bpf-next] bpf: x86: Explicitly zero-extend rax after 32-bit cmpxchg Brendan Jackman
2021-02-15 21:05 ` KP Singh
2021-02-15 22:20 ` Daniel Borkmann
2021-02-15 22:24 ` Ilya Leoshkevich
2021-02-15 22:35 ` Daniel Borkmann
2021-02-15 22:42 ` Ilya Leoshkevich
2021-02-15 23:30 ` KP Singh
2021-02-16 0:43 ` Daniel Borkmann [this message]
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