From: Pu Lehui <pulehui@huawei.com>
To: <bot+bpf-ci@kernel.org>
Cc: <visitorckw@gmail.com>, <ast@kernel.org>, <daniel@iogearbox.net>,
<andrii@kernel.org>, <eddyz87@gmail.com>, <memxor@gmail.com>,
<luke.r.nels@gmail.com>, <xi.wang@gmail.com>, <pjw@kernel.org>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<martin.lau@linux.dev>, <song@kernel.org>,
<yonghong.song@linux.dev>, <jolsa@kernel.org>,
<emil@etsalapatis.com>, <alex@ghiti.fr>, <jserv@ccns.ncku.edu.tw>,
<eleanor15x@gmail.com>, <marscheng@google.com>,
<bpf@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <martin.lau@kernel.org>,
<clm@meta.com>, <ihor.solodrai@linux.dev>
Subject: Re: [PATCH bpf-next v3 1/3] riscv, bpf: Add support for BPF_SDIV and BPF_SMOD in RV32 JIT
Date: Tue, 7 Jul 2026 10:30:08 +0800 [thread overview]
Message-ID: <fa8a040f-64c4-484f-9538-fb0ec287639f@huawei.com> (raw)
In-Reply-To: <2ed385399f170538acc571665dca8036ccaa85dd1b9dfe987d8c7d566f59e8e5@mail.kernel.org>
On 2026/7/7 2:12, bot+bpf-ci@kernel.org wrote:
>> commit c5a973b7fc82eeb9b84aaf80fc2673a94ab795b2
>> Author: Kuan-Wei Chiu <visitorckw@gmail.com>
>>
>> riscv, bpf: Add support for BPF_SDIV and BPF_SMOD in RV32 JIT
>>
>> The current rv32 bpf jit compiler incorrectly treats BPF_SDIV and
>> BPF_SMOD as unsigned operations. The BPF instruction set allows
>> signed division and modulo by reusing the BPF_DIV and BPF_MOD opcodes
>> with the instruction offset set to 1.
>>
>> Update the emit_alu_r32() function to accept an 'is_sdiv' variable and
>> emit the correct div and rem instructions when the offset is 1.
>>
>> Before this patch:
>> [ 44.161771] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times)
>> [ 44.167385] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times)
>> [ 44.171053] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times)
>> [ 44.172081] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times)
>>
>> After this patch:
>> [ 16.002192] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 95 PASS
>> [ 16.002983] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 1059 PASS
>> [ 16.017167] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 136 PASS
>> [ 16.023002] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 109 PASS
>>
>> Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
>
> This looks like a bug fix for the original RV32 BPF JIT implementation.
> Should this include:
>
> Fixes: 5f316b65e99f ("riscv, bpf: Add RV32G eBPF JIT")
not need to add fixes tag, as this not a bugfix
>
>
> ---
> AI reviewed your patch. Please fix the bug or email reply why it's not a bug.
> See: https://github.com/kernel-patches/vmtest/blob/master/ci/claude/README.md
>
> CI run summary: https://github.com/kernel-patches/bpf/actions/runs/28811594040
next prev parent reply other threads:[~2026-07-07 2:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 17:28 [PATCH bpf-next v3 0/3] riscv, bpf: Add support for signed operations and 32-bit atomics Kuan-Wei Chiu
2026-07-06 17:28 ` [PATCH bpf-next v3 1/3] riscv, bpf: Add support for BPF_SDIV and BPF_SMOD in RV32 JIT Kuan-Wei Chiu
2026-07-06 18:12 ` bot+bpf-ci
2026-07-07 2:30 ` Pu Lehui [this message]
2026-07-07 2:21 ` Pu Lehui
2026-07-06 17:28 ` [PATCH bpf-next v3 2/3] riscv, bpf: Add support for BPF_MOVSX " Kuan-Wei Chiu
2026-07-06 17:28 ` [PATCH bpf-next v3 3/3] riscv, bpf: Add 32 bit atomic operations to " Kuan-Wei Chiu
2026-07-07 2:26 ` Pu Lehui
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