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[54.240.197.231]) by smtp.gmail.com with ESMTPSA id fc16-20020a05600c525000b00418d68df226sm20107903wmb.0.2024.05.06.07.57.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 May 2024 07:57:01 -0700 (PDT) From: Puranjay Mohan To: Ilya Leoshkevich , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko Cc: bpf@vger.kernel.org, Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Ilya Leoshkevich Subject: Re: [PATCH bpf-next] s390/bpf: Fully order atomic "add", "and", "or" and "xor" In-Reply-To: <20240506141649.50845-1-iii@linux.ibm.com> References: <20240506141649.50845-1-iii@linux.ibm.com> Date: Mon, 06 May 2024 14:56:59 +0000 Message-ID: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Ilya Leoshkevich writes: > BPF_ATOMIC_OP() macro documentation states that "BPF_ADD | BPF_FETCH" > should be the same as atomic_fetch_add(), which is currently not the > case on s390x: the synchronization instruction "bcr 14,0" is missing. > > This should not be a problem in practice, because s390x is allowed to > reorder only stores with subsequent fetches from different addresses. > Still, just to be on the safe side, and also for consistency, emit the > synchronization instruction. > > Note that it's not required to do this for BPF_XCHG and BPF_CMPXCHG, > because COMPARE AND SWAP performs serialization itself. > > Fixes: ba3b86b9cef0 ("s390/bpf: Implement new atomic ops") > Reported-by: Puranjay Mohan > Closes: https://lore.kernel.org/bpf/mb61p34qvq3wf.fsf@kernel.org/ > Signed-off-by: Ilya Leoshkevich > --- > arch/s390/net/bpf_jit_comp.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c > index fa2f824e3b06..a0dfb3f665ab 100644 > --- a/arch/s390/net/bpf_jit_comp.c > +++ b/arch/s390/net/bpf_jit_comp.c > @@ -1427,6 +1427,8 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, > EMIT6_DISP_LH(0xeb000000, is32 ? (op32) : (op64), \ > (insn->imm & BPF_FETCH) ? src_reg : REG_W0, \ > src_reg, dst_reg, off); \ > + /* bcr 14,0 - see atomic_fetch_{add,and,or,xor}() */ \ > + _EMIT2(0x07e0); \ Shouldn't this be: /* bcr 14,0 - see atomic_fetch_{add,and,or,xor}() */ if (insn->imm & BPF_FETCH) _EMIT2(0x07e0); The barrier is only needed for the BPF_FETCH varient and I am assuming that the barrier has some overhead. So we should not emit it for all operations. Thanks, Puranjay