From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B84FC10E6 for ; Tue, 7 May 2024 17:59:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715104743; cv=none; b=O2rqB0gJI3gfjFG0wvXQmw5UnMHYTkKvE1H7EErsP0qCYUcI/KGzcl84xVzwbLEupui8g2EGeCfEDS3T1qoNHywxSu/5E/ICud/jSs1bvVDKtdQgEvM5UhIDZAXmy5Xi6gaRVYzTUVjLPLPzf/sclfiWU2Mg9VDGi089as+tcHg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715104743; c=relaxed/simple; bh=AFNM8weygNe//MJR86qy1aGU2LKCBu/DC5zsAWs51PU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=qM54+EMSxe5FQTv7Ms9/LIfM+lFIQp+bpohuEmE0fhYOYmEtxn4dGmK41VG0QnSyxJadW/3WRCvgY0vgiaV7tBLeHNesY9/l1/Crj/ND+ZWwoop46Qn//QarzpNrhxK6bUV+L7kZohFmuRagpXvmkoOmiXcnXZL+dH6YuObKJpc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CRJxCELM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CRJxCELM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2D60C2BBFC; Tue, 7 May 2024 17:59:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715104743; bh=AFNM8weygNe//MJR86qy1aGU2LKCBu/DC5zsAWs51PU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=CRJxCELMVzKSTxCzc/4lNfoA09gawZsrX6grUUvc6GSLe56d/Df6735sF9P/R7I0E wSygLx3jemZo0ePB3Cd2LMaVugUXUB5N/VvT/wt+xh7PBQS2M4oG82f3EFVkqfnBL3 BJotvhxHFJ2ahjEDB9RKPgdIjEc6bVxNLyMbKiqQZ5G02qQvJykPJHiL6L4KdtXc7p hHnHVVd2fSd6MdcQSF6koXEk5EzFiyun4VVWIg6tDnNk2YhMcosz3jI7AsLolIsnIm lovX5svWFq/iAUoyP/Cs6hjOkS8jVBX9xW6wpLmEa9t+OHlRKWxRWbBVrIPMz7lczS SyZvrVbgvgAtw== From: Puranjay Mohan To: Naveen N Rao Cc: Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Pu Lehui , "Paul E. McKenney" , bpf@vger.kernel.org, Ilya Leoshkevich , Tiezhu Yang , Michael Ellerman , Hari Bathini Subject: Re: [PATCH bpf] riscv, bpf: make some atomic operations fully ordered In-Reply-To: References: <20240505201633.123115-1-puranjay@kernel.org> Date: Tue, 07 May 2024 17:58:59 +0000 Message-ID: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Naveen N Rao writes: > Hi Puranjay, > > On Sun, May 05, 2024 at 10:40:00PM GMT, Puranjay Mohan wrote: >> Puranjay Mohan writes: >> >> > The BPF atomic operations with the BPF_FETCH modifier along with >> > BPF_XCHG and BPF_CMPXCHG are fully ordered but the RISC-V JIT implements >> > all atomic operations except BPF_CMPXCHG with relaxed ordering. >> >> I know that the BPF memory model is in the works and we currently don't >> have a way to make all the JITs consistent. But as far as atomic >> operations are concerned here are my observations: >> > ... >> >> >> 3. POWERPC >> ------- >> >> JIT is emitting all atomic instructions with relaxed ordering. It >> implements atomic operations using LL and SC instructions, we need to >> emit "sync" instructions before and after this sequence to make it >> follow the LKMM. This is how the kernel is doing it. > > Indeed - good find! > >> >> Naveen, can you ack this? if this is the correct thing to do, I will >> send a patch. > > Please do. > Hi Naveen, I have sent a patch fixing both ppc32 and ppc64. But I don't have a way to test this or even compile it: https://lore.kernel.org/all/20240507175439.119467-1-puranjay@kernel.org/ Can you help me test this? the change is trivial. Thanks, Puranjay