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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: buildroot@busybox.net
Subject: [Buildroot] [PATCH v1 4/9] board / intel: Add SPI peripherals for Minnowboard MAX
Date: Thu, 25 Aug 2016 17:04:42 +0300	[thread overview]
Message-ID: <1472133887-34746-5-git-send-email-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <1472133887-34746-1-git-send-email-andriy.shevchenko@linux.intel.com>

From: Mika Westerberg <mika.westerberg@linux.intel.com>

Add two SPI peripherals which can be connected to Minnowboard MAX low speed
connector. First is Atmel AT25 compatible SPI EEPROM and second is M25P80
compatible SPI serial flash.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 board/intel/minnowboard-max/acpi/at25.asl   | 58 +++++++++++++++++++++++++++++
 board/intel/minnowboard-max/acpi/m25p80.asl | 52 ++++++++++++++++++++++++++
 2 files changed, 110 insertions(+)
 create mode 100644 board/intel/minnowboard-max/acpi/at25.asl
 create mode 100644 board/intel/minnowboard-max/acpi/m25p80.asl

diff --git a/board/intel/minnowboard-max/acpi/at25.asl b/board/intel/minnowboard-max/acpi/at25.asl
new file mode 100644
index 0000000..fdc169a
--- /dev/null
+++ b/board/intel/minnowboard-max/acpi/at25.asl
@@ -0,0 +1,58 @@
+/*
+ * Minnowboard MAX
+ *
+ * http://wiki.minnowboard.org/MinnowBoard_MAX
+ *
+ * This adds Atmel AT25 compatible 1kb serial EEPROM to the SPI host
+ * controller available on Minnowboard MAX low speed connector (JP1) pins:
+ *
+ *   pin name		pin number
+ *   -----------------------------
+ *   GPIO_SPI_CS	5
+ *   GPIO_SPI_MISO	7
+ *   GPIO_SPI_MOSI	9
+ *   GPIO_SPI_CLK	11
+ *
+ * In Linux you need to set CONFIG_EEPROM_AT25=y (or m) to be able to use
+ * this device.
+ */
+DefinitionBlock ("at25.aml", "SSDT", 5, "INTEL", "AT25", 1)
+{
+    External (_SB_.SPI1, DeviceObj)
+
+    Scope (\_SB.SPI1)
+    {
+        Device (EEP0) {
+            Name (_HID, "PRP0001")
+            Name (_DDN, "Atmel AT25 compatible EEPROM")
+            Name (_CRS, ResourceTemplate () {
+                SpiSerialBus (
+                    1,                      // Chip select
+                    PolarityLow,            // Chip select is active low
+                    FourWireMode,           // Full duplex
+                    8,                      // Bits per word is 8 (byte)
+                    ControllerInitiated,    // Don't care
+                    1000000,                // 1 MHz
+                    ClockPolarityLow,       // SPI mode 0
+                    ClockPhaseFirst,        // SPI mode 0
+                    "\\_SB.SPI1",           // SPI host controller
+                    0                       // Must be 0
+                )
+            })
+
+            /*
+	     * See Documentation/devicetree/bindings/eeprom/at25.txt for
+	     * more information about these bindings.
+             */
+            Name (_DSD, Package () {
+                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                Package () {
+                    Package () {"compatible", "atmel,at25"},
+                    Package () {"size", 1024},
+                    Package () {"pagesize", 32},
+                    Package () {"address-width", 16},
+                }
+            })
+        }
+    }
+}
diff --git a/board/intel/minnowboard-max/acpi/m25p80.asl b/board/intel/minnowboard-max/acpi/m25p80.asl
new file mode 100644
index 0000000..d0676c6
--- /dev/null
+++ b/board/intel/minnowboard-max/acpi/m25p80.asl
@@ -0,0 +1,52 @@
+/*
+ * Minnowboard MAX
+ *
+ * http://wiki.minnowboard.org/MinnowBoard_MAX
+ *
+ * This adds M25P80 (AT26DF, M25P, W25X) compatible serial flash to the SPI
+ * host controller available on Minnowboard MAX low speed connector (JP1)
+ * pins:
+ *
+ *   pin name		pin number
+ *   -----------------------------
+ *   GPIO_SPI_CS	5
+ *   GPIO_SPI_MISO	7
+ *   GPIO_SPI_MOSI	9
+ *   GPIO_SPI_CLK	11
+ *
+ * In Linux you need to set CONFIG_MTD_M25P80=y (or m) to be able to use
+ * this device.
+ */
+DefinitionBlock ("m25p80.aml", "SSDT", 5, "INTEL", "M25P80", 1)
+{
+    External (_SB_.SPI1, DeviceObj)
+
+    Scope (\_SB.SPI1)
+    {
+        Device (FLS0) {
+            Name (_HID, "PRP0001")
+            Name (_DDN, "M25P80 compatible serial flash")
+            Name (_CRS, ResourceTemplate () {
+                SpiSerialBus (
+                    1,                      // Chip select
+                    PolarityLow,            // Chip select is active low
+                    FourWireMode,           // Full duplex
+                    8,                      // Bits per word is 8 (byte)
+                    ControllerInitiated,    // Don't care
+                    10000000,               // 10 MHz
+                    ClockPolarityLow,       // SPI mode 0
+                    ClockPhaseFirst,        // SPI mode 0
+                    "\\_SB.SPI1",           // SPI host controller
+                    0                       // Must be 0
+                )
+            })
+
+            Name (_DSD, Package () {
+                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                Package () {
+                    Package () {"compatible", "jedec,spi-nor"},
+                }
+            })
+        }
+    }
+}
-- 
2.8.1

  parent reply	other threads:[~2016-08-25 14:04 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-25 14:04 [Buildroot] [PATCH v1 0/9] board: introduce common infrastructure for Intel SoCs Andy Shevchenko
2016-08-25 14:04 ` [Buildroot] [PATCH v1 1/9] package/acpica: Add host configuration to the tool Andy Shevchenko
2016-08-25 21:44   ` Thomas Petazzoni
2016-08-26 10:50   ` Erico Nunes
2016-08-25 14:04 ` [Buildroot] [PATCH v1 2/9] board/intel/common: Add common files for x86 boards Andy Shevchenko
2016-08-25 21:37   ` Thomas Petazzoni
2016-08-26 16:42   ` Arnout Vandecappelle
2016-08-25 14:04 ` [Buildroot] [PATCH v1 3/9] board/intel/common: Add possibility for adding ACPI tables to the initrd Andy Shevchenko
2016-08-25 21:43   ` Thomas Petazzoni
2016-08-26  6:13   ` Arnout Vandecappelle
2016-08-26  8:39     ` Thomas Petazzoni
     [not found]     ` <20160826090454.GK1812@lahna.fi.intel.com>
2016-08-26  9:30       ` Thomas Petazzoni
     [not found]         ` <20160826093901.GO1812@lahna.fi.intel.com>
2016-08-26 13:28           ` Thomas Petazzoni
2016-08-26 16:30           ` Arnout Vandecappelle
     [not found]             ` <20160829065522.GV1812@lahna.fi.intel.com>
2016-08-29  7:45               ` Arnout Vandecappelle
     [not found]                 ` <20160829075810.GA1709@lahna.fi.intel.com>
2016-08-29  9:08                   ` Arnout Vandecappelle
2016-08-25 14:04 ` Andy Shevchenko [this message]
2016-08-25 21:47   ` [Buildroot] [PATCH v1 4/9] board / intel: Add SPI peripherals for Minnowboard MAX Thomas Petazzoni
     [not found]     ` <20160826090917.GL1812@lahna.fi.intel.com>
2016-08-26  9:26       ` Thomas Petazzoni
2016-08-25 14:04 ` [Buildroot] [PATCH v1 5/9] board / intel: Add SPI peripherals for Joule Andy Shevchenko
2016-08-25 14:04 ` [Buildroot] [PATCH v1 6/9] board / intel: Add Aosong AM2315 sensor for Intel Joule Andy Shevchenko
2016-08-25 14:04 ` [Buildroot] [PATCH v1 7/9] board / intel: Add GPIO LEDs " Andy Shevchenko
2016-08-25 14:04 ` [Buildroot] [PATCH v1 8/9] board / intel: Add GPIO LEDs for Intel Minnowboard Andy Shevchenko
2016-08-25 14:04 ` [Buildroot] [PATCH v1 9/9] board / intel: Add GPIO buttons " Andy Shevchenko

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