Re: [Buildroot] [PATCH 00/28] Use the best FPU strategies on 32-bits Arm Cortex

From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
To: Giulio Benetti <giulio.benetti@benettiengineering.com>
Cc: Theo Debrouwere <t.debrouwere@televic.com>,
	Simon Doppler <dopsi@dopsi.ch>,
	Sergey Matyukevich <geomatsi@gmail.com>,
	Mike Harmony <mike.harmony@snapav.com>,
	Bartosz Bilas <b.bilas@grinn-global.com>,
	Davide Viti <zinosat@gmail.com>,
	Jan Kraval <jan.kraval@gmail.com>,
	Ludovic Desroches <ludovic.desroches@microchip.com>,
	Marcin Niestroj <m.niestroj@grinn-global.com>,
	Michel Stempin <michel.stempin@wanadoo.fr>,
	Lothar Felten <lothar.felten@gmail.com>,
	buildroot@buildroot.org, Edgar Bonet <bonet@grenoble.cnrs.fr>,
	Fabio Estevam <festevam@gmail.com>,
	"Yann E . MORIN" <yann.morin.1998@free.fr>,
	Biagio Montaruli <biagio.hkr@gmail.com>
Subject: Re: [Buildroot] [PATCH 00/28] Use the best FPU strategies on 32-bits Arm Cortex
Date: Sat, 22 Jan 2022 15:32:43 +0100	[thread overview]
Message-ID: <20220122153243.009b24ba@windsurf> (raw)
In-Reply-To: <20220118104338.2081259-1-giulio.benetti@benettiengineering.com>

Hello,

On Tue, 18 Jan 2022 11:43:10 +0100
Giulio Benetti <giulio.benetti@benettiengineering.com> wrote:

> this patchset aims to enable the best FPU strategy for every board with
> 32-bits Arm Cortex actually present in Buildroot. I don't own these boards
> so I can't test these changes. What is about Allwinner doesn't worry me
> because I've tested a lot of cases with Olimex boards, but the other
> changes are still to be tested.
> 
> So I ask to the board maintainers to test the patches that involve their
> boards if possible. Anyway I've checked well all the SoCs Datasheet and I
> think I've made it correctly, even if in some of them it's not specified
> if VFPv4 means -D32. I assume it like that because otherwise -D16 is
> usually specified.

Do we have a good understand of what -mfpu=neon-vfpv4 does? Your patch
series basically converts many defconfigs to use this -mfpu value, but
it's not clear to me how it works. What does it mean to combine NEON
and VFPv4 instructions?

Regarding VFPv4 D16 vs. D32,
https://developer.arm.com/documentation/den0018/a/Compiling-NEON-Instructions/GCC-command-line-options/Option-to-specify-the-FPU
tells us:

  VFPv3 and VFPv4 implementations provide 32 double-precision
  registers. However, when NEON unit is not present, the top sixteen
  registers (D16-D31) become optional. This is shown by the -d16 in the
  option name, which means that the top sixteen D registers are not
  available.

So, my understanding is that when NEON is available, the VFPv4 is
guaranteed to have the 32 double-precision registers (D32).

Thomas
-- 
Thomas Petazzoni, co-owner and CEO, Bootlin
Embedded Linux and Kernel engineering and training
https://bootlin.com
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