Re: [Buildroot] [PATCH for-next 01/11] arch/Config.in.riscv: add Zicsr and Zifencei standalone extensions

[Thomas Petazzoni via buildroot <buildroot@buildroot.org>]

Hello,

On Sat, 23 Jul 2022 15:00:40 +0200
Romain Naour <romain.naour@smile.fr> wrote:

> I'm not familiar with the riscv instruction set, so I was not sure if we should
> support the possibility to disable Zicsr and Zifencei standalone extensions with
> gcc 12. AFIU, they are unconditionally enabled in previous gcc releases.

Correct, which is why I think they will always be present in
Linux-capable RISC-V cores. The reason I believe they were split from
the I part of the ISA is because I is the base part of the ISA, and
some people wanted to make RISC-V designs without those instructions,
but not RISC-V designs targeting Linux.

So for now, I think we should simply make the assumption that all
RISC-V cores will have those instructions.

If that turns out to be wrong in the future, we can always revisit that.

> Additionally we have received two patches to add "vector operations extension"
> 
> http://patchwork.ozlabs.org/project/buildroot/patch/20220704085552.3499243-2-abel@x-silicon.com/
> 
> http://patchwork.ozlabs.org/project/buildroot/patch/20220627135359.2232222-1-fhunleth@troodon-software.com/
> 
> But this requires gcc-12
> 
> http://patchwork.ozlabs.org/project/buildroot/patch/20220627135359.2232222-1-fhunleth@troodon-software.com/#2933736
> 
> Do you think "Vector Instructions (V)" deserve an option ? (I would say yes).

Yes, V definitely needs an option, as there will clearly be
Linux-capable RISC-V cores that do not implement the V extension.

The option for the V extension will have to select
BR2_ARCH_NEEDS_GCC_AT_LEAST_12.

Best regards,

Thomas
-- 
Thomas Petazzoni, co-owner and CEO, Bootlin
Embedded Linux and Kernel engineering and training
https://bootlin.com
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