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[2a01:cb05:945b:7e00:9bdc:6887:23a2:4f31]) by smtp.gmail.com with ESMTPSA id hn8-20020a05600ca38800b003fee6e170f9sm2888409wmb.45.2023.08.31.13.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 13:17:39 -0700 (PDT) From: Romain Naour To: buildroot@buildroot.org Date: Thu, 31 Aug 2023 22:17:37 +0200 Message-ID: <20230831201737.509574-1-romain.naour@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693513060; x=1694117860; darn=buildroot.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=zlQTLtmy0EeqrPTDuU1dgVV5yOaWCIAcLt7ZTBCD1DQ=; b=AfGZw5m5mXFvIy3x/hvPh2/qo5tTndxhSQxy3Aq+fgaSX3Tv8Ethm5LsoX9roKNXB0 WEgfFHeE01vEirIeWxDqZ8NcnWF3BLcnvJz8h8BigkX5c7LIXMwoUMZDIltYXAwhm3k5 qQXlV/vfMIrh/fzPlqLZxlfqwIvEXwfKWQ2rVL9Lc6xwjJbqGjopodeeKuCwHCDIyPCu sQ9hBC43qOMWSWfqROJmYf9wTafp3c+TwGm/GhZko5exTiTGoIb4+5I29EAFPvmRPNvc bvpBPyjRKnf65Ca9YqK2RUCgoEHeFHx/PyorOgbaRrbIMO4cqrseIEdNFyCj5pJhfKO8 MYtw== X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=AfGZw5m5 Subject: [Buildroot] [PATCH] configs/beaglev_defconfig: fix build with binutils >= 2.38 X-BeenThere: buildroot@buildroot.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Romain Naour Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: buildroot-bounces@buildroot.org Sender: "buildroot" Backport an upstream patch fixing the build with binutils >= 2.38 for riscv's for Zicsr and Zifencei. Fixes: https://gitlab.com/buildroot.org/buildroot/-/jobs/4987456149 Signed-off-by: Romain Naour --- ...iscv-Fix-build-against-binutils-2.38.patch | 58 +++++++++++++++++++ configs/beaglev_defconfig | 1 + 2 files changed, 59 insertions(+) create mode 100644 board/beaglev/patches/uboot/0001-riscv-Fix-build-against-binutils-2.38.patch diff --git a/board/beaglev/patches/uboot/0001-riscv-Fix-build-against-binutils-2.38.patch b/board/beaglev/patches/uboot/0001-riscv-Fix-build-against-binutils-2.38.patch new file mode 100644 index 0000000000..52b496f054 --- /dev/null +++ b/board/beaglev/patches/uboot/0001-riscv-Fix-build-against-binutils-2.38.patch @@ -0,0 +1,58 @@ +From 0cf11f3c0478f4286adcfb09bf9137f8b00212e3 Mon Sep 17 00:00:00 2001 +From: Alexandre Ghiti +Date: Mon, 3 Oct 2022 18:07:54 +0200 +Subject: [PATCH] riscv: Fix build against binutils 2.38 + +The following description is copied from the equivalent patch for the +Linux Kernel proposed by Aurelien Jarno: + +>From version 2.38, binutils default to ISA spec version 20191213. This +means that the csr read/write (csrr*/csrw*) instructions and fence.i +instruction has separated from the `I` extension, become two standalone +extensions: Zicsr and Zifencei. As the kernel uses those instruction, +this causes the following build failure: + +arch/riscv/cpu/mtrap.S: Assembler messages: +arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' +arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' +arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' +arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' + +Signed-off-by: Alexandre Ghiti +Reviewed-by: Bin Meng +Tested-by: Heinrich Schuchardt +Tested-by: Heiko Stuebner +Tested-by: Christian Stewart +Reviewed-by: Rick Chen +(cherry picked from commit 1dde977518f13824b847e23275001191139bc384) +Upstream: https://gitlab.com/u-boot/u-boot/-/commit/1dde977518f13824b847e23275001191139bc384 +Signed-off-by: Romain Naour +--- + arch/riscv/Makefile | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 0b80eb8d864..53d1194ffb6 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany + endif + +-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ ++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) ++ ++# Newer binutils versions default to ISA spec version 20191213 which moves some ++# instructions from the I extension to the Zicsr and Zifencei extensions. ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) ++ifeq ($(toolchain-need-zicsr-zifencei),y) ++ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei ++endif ++ ++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ + -mcmodel=$(CMODEL) + + PLATFORM_CPPFLAGS += $(ARCH_FLAGS) +-- +2.41.0 + diff --git a/configs/beaglev_defconfig b/configs/beaglev_defconfig index 42c732b973..a76c1ffb5f 100644 --- a/configs/beaglev_defconfig +++ b/configs/beaglev_defconfig @@ -40,3 +40,4 @@ BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,starfive-tech,u-boot,64e BR2_TARGET_UBOOT_BOARD_DEFCONFIG="starfive_vic7100_beagle_v_smode" BR2_PACKAGE_HOST_GENIMAGE=y BR2_PACKAGE_HOST_JH71XX_TOOLS=y +BR2_GLOBAL_PATCH_DIR="board/beaglev/patches" -- 2.41.0 _______________________________________________ buildroot mailing list buildroot@buildroot.org https://lists.buildroot.org/mailman/listinfo/buildroot