From: Peter Korsgaard <peter@korsgaard.com>
To: Bram Vlerick <bram.vlerick@openpixelsystems.org>
Cc: buildroot@buildroot.org
Subject: Re: [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes
Date: Sat, 17 Sep 2022 14:32:46 +0200 [thread overview]
Message-ID: <87h7162nbl.fsf@dell.be.48ers.dk> (raw)
In-Reply-To: <20220816120718.3021545-1-bram.vlerick@openpixelsystems.org> (Bram Vlerick's message of "Tue, 16 Aug 2022 14:07:17 +0200")
>>>>> "Bram" == Bram Vlerick <bram.vlerick@openpixelsystems.org> writes:
> When enable DM for SPL binary, the DTB part of SPL may not 4 bytes aligned.
> If u-boot-spl is not aligned, the offset of the DDR firmware is not 4
> byte aligned when u-boot-spl-ddr.bin is created. This causes the ddr
> firmware to not be loaded correctly at boot.
> See imx-mkimage commit bba038d893046b44683182dba540f104dab80fe7 for
> implementation in imx-mkimage.
> Signed-off-by: Bram Vlerick <bram.vlerick@openpixelsystems.org>
Committed to 2022.05.x and 2022.02.x, thanks.
--
Bye, Peter Korsgaard
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prev parent reply other threads:[~2022-09-17 12:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-16 12:07 [Buildroot] [PATCH 1/2] board/freescale/common/imx: align u-boot-spl to 4 bytes Bram Vlerick
2022-08-23 21:30 ` Thomas Petazzoni via buildroot
2022-08-24 7:38 ` Bram Vlerick
2022-09-17 12:32 ` Peter Korsgaard [this message]
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