[Buildroot] [PATCH next 1/4] arch/arm: add the Neoverse-V1 core

[Buildroot] [PATCH next 1/4] arch/arm: add the Neoverse-V1 core

[Julien Olivain via buildroot]

This commit adds the Neoverse-V1 core, which is an armv8.4a ISA.
See: [1] [2].

This CPU support was added in GCC 11. See [3] [4] [5].

This CPU supports Aarch64 at all exception levels (EL0 to EL3).
It also supports Aarch32 only in EL0 (user-space). This means it's
technically possible to compile Aarch32 code. GCC has the support
to do so. Since Buildroot recompiles a full system (ATF, Kernel,
user-space) this support has limited value. This is why this
CPU is limited to 64bit builds only.

Qemu added neoverse-v1 support in upstream commit [6], first included
in v8.1.0.

[1] https://developer.arm.com/Processors/Neoverse%20V1
[2] https://developer.arm.com/documentation/101427/0102/Functional-description/Introduction/About-the-core
[3] https://gcc.gnu.org/gcc-11/changes.html#arm-targets
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-11.1.0#l141
[5] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c9d56eb777552ac5ee0c281e1f6e34b6fe929b77
[6] https://gitlab.com/qemu-project/qemu/-/commit/c74138c6c040b62e941326a4fbb25a93fdd35b72

Signed-off-by: Julien Olivain <ju.o@free.fr>
---
 arch/Config.in.arm | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index a0bf6c3386..16911f5b95 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -498,6 +498,12 @@ config BR2_tsv110
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
 
 comment "armv8.4a cores"
+config BR2_neoverse_v1
+	bool "neoverse-V1 (aka zeus)"
+	depends on BR2_ARCH_IS_64
+	select BR2_ARM_CPU_HAS_FP_ARMV8
+	select BR2_ARM_CPU_ARMV8A
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
 config BR2_saphira
 	bool "saphira"
 	depends on BR2_ARCH_IS_64
@@ -918,6 +924,7 @@ config BR2_GCC_TARGET_CPU
 	default "neoverse-n1"	if BR2_neoverse_n1
 	default "tsv110"	if BR2_tsv110
 	# armv8.4a
+	default "neoverse-v1"   if BR2_neoverse_v1
 	default "saphira"	if BR2_saphira
 	# armv9.0a
 	default "cortex-a710"	if BR2_cortex_a710
-- 
2.53.0

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[Buildroot] [PATCH next 2/4] arch/arm: add the Neoverse-V2 core

[Julien Olivain via buildroot]

This commit adds the Neoverse-V2 core, which is an armv9.0a ISA.
See: [1] [2].

This CPU support was added in GCC 13. See [3] [4] [5].

This CPU supports Aarch64 at all exception levels (EL0 to EL3).
It also supports Aarch32 only in EL0 (user-space). This means it's
technically possible to compile Aarch32 code. GCC has the support
to do so. Since Buildroot recompiles a full system (ATF, Kernel,
user-space) this support has limited value. This is why this
CPU is limited to 64bit builds only.

[1] https://developer.arm.com/Processors/Neoverse%20V2
[2] https://developer.arm.com/documentation/102375/latest/
[3] https://gcc.gnu.org/gcc-13/changes.html#aarch64
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-13.1.0#l184
[5] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=14d4b4fb12041dde1511262b926662929196c3fe

Signed-off-by: Julien Olivain <ju.o@free.fr>
---
 arch/Config.in.arm | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index 16911f5b95..e9f3c53e0d 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -524,6 +524,12 @@ config BR2_neoverse_n2
 	select BR2_ARM_CPU_HAS_FP_ARMV8
 	select BR2_ARM_CPU_ARMV9A
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
+config BR2_neoverse_v2
+	bool "neoverse-V2 (aka demeter)"
+	depends on BR2_ARCH_IS_64
+	select BR2_ARM_CPU_HAS_FP_ARMV8
+	select BR2_ARM_CPU_ARMV9A
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_13
 
 comment "armv9.2a cores"
 config BR2_cortex_a720
@@ -929,6 +935,7 @@ config BR2_GCC_TARGET_CPU
 	# armv9.0a
 	default "cortex-a710"	if BR2_cortex_a710
 	default "neoverse-n2"	if BR2_neoverse_n2
+	default "neoverse-v2"	if BR2_neoverse_v2
 	# armv9.2a
 	default "cortex-a720"	if BR2_cortex_a720
 
-- 
2.53.0

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[Buildroot] [PATCH next 3/4] arch/arm: add the Neoverse-V3 core

[Julien Olivain via buildroot]

This commit adds the Neoverse-V3 core, which is an armv9.2a ISA.
See: [1] [2].

This CPU support was added in GCC 15. See [3] [4] [5].

This CPU supports Aarch64 only at all exception levels (EL0 to EL3).

[1] https://developer.arm.com/Processors/Neoverse%20V3
[2] https://developer.arm.com/documentation/107734/0002/The-Neoverse--V3--core/Neoverse--V3--core-features
[3] https://gcc.gnu.org/gcc-15/changes.html#aarch64
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-15.1.0#l221
[5] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=729000b90300a31ef9ed405635a0be761c5e168b

Signed-off-by: Julien Olivain <ju.o@free.fr>
---
 arch/Config.in.arm | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index e9f3c53e0d..ff301785e5 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -538,6 +538,12 @@ config BR2_cortex_a720
 	select BR2_ARM_CPU_HAS_FP_ARMV8
 	select BR2_ARM_CPU_ARMV9A
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_14
+config BR2_neoverse_v3
+	bool "neoverse-V3 (aka poseidon)"
+	depends on BR2_ARCH_IS_64
+	select BR2_ARM_CPU_HAS_FP_ARMV8
+	select BR2_ARM_CPU_ARMV9A
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_15
 endchoice
 
 config BR2_ARM_ENABLE_NEON
@@ -938,6 +944,7 @@ config BR2_GCC_TARGET_CPU
 	default "neoverse-v2"	if BR2_neoverse_v2
 	# armv9.2a
 	default "cortex-a720"	if BR2_cortex_a720
+	default "neoverse-v3"	if BR2_neoverse_v3
 
 config BR2_GCC_TARGET_ABI
 	default "aapcs-linux"	if BR2_arm || BR2_armeb
-- 
2.53.0

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[Buildroot] [PATCH next 4/4] arch/arm: add the Neoverse-V3AE core

[Julien Olivain via buildroot]

This commit adds the Neoverse-V3AE (Automotive Enhanced) core, which
is an armv9.2a ISA. See: [1] [2].

This CPU support was added in GCC 15. See [3] [4] [5].

This CPU supports Aarch64 only at all exception levels (EL0 to EL3).

This CPU is present in NVIDIA Jetson Thor / Tegra T264 [6].

[1] https://developer.arm.com/Processors/Neoverse%20V3AE
[2] https://developer.arm.com/documentation/101595/0002/The-Neoverse-V3AE--core/Neoverse-V3AE--core-features
[3] https://gcc.gnu.org/gcc-15/changes.html#aarch64
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-15.1.0#l222
[5] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=7ca2a803c4a0d8e894f0b36625a2c838c54fb4cd
[6] https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-thor/

Signed-off-by: Julien Olivain <ju.o@free.fr>
---
 arch/Config.in.arm | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index ff301785e5..eb5babe29b 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -544,6 +544,12 @@ config BR2_neoverse_v3
 	select BR2_ARM_CPU_HAS_FP_ARMV8
 	select BR2_ARM_CPU_ARMV9A
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_15
+config BR2_neoverse_v3ae
+	bool "neoverse-V3AE (aka poseidon)"
+	depends on BR2_ARCH_IS_64
+	select BR2_ARM_CPU_HAS_FP_ARMV8
+	select BR2_ARM_CPU_ARMV9A
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_15
 endchoice
 
 config BR2_ARM_ENABLE_NEON
@@ -945,6 +951,7 @@ config BR2_GCC_TARGET_CPU
 	# armv9.2a
 	default "cortex-a720"	if BR2_cortex_a720
 	default "neoverse-v3"	if BR2_neoverse_v3
+	default "neoverse-v3ae"	if BR2_neoverse_v3ae
 
 config BR2_GCC_TARGET_ABI
 	default "aapcs-linux"	if BR2_arm || BR2_armeb
-- 
2.53.0

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Re: [Buildroot] [PATCH next 1/4] arch/arm: add the Neoverse-V1 core

[Julien Olivain via buildroot]

On 03/03/2026 21:27, Julien Olivain via buildroot wrote:
> This commit adds the Neoverse-V1 core, which is an armv8.4a ISA.
> See: [1] [2].
> 
> This CPU support was added in GCC 11. See [3] [4] [5].
> 
> This CPU supports Aarch64 at all exception levels (EL0 to EL3).
> It also supports Aarch32 only in EL0 (user-space). This means it's
> technically possible to compile Aarch32 code. GCC has the support
> to do so. Since Buildroot recompiles a full system (ATF, Kernel,
> user-space) this support has limited value. This is why this
> CPU is limited to 64bit builds only.
> 
> Qemu added neoverse-v1 support in upstream commit [6], first included
> in v8.1.0.
> 
> [1] https://developer.arm.com/Processors/Neoverse%20V1
> [2] 
> https://developer.arm.com/documentation/101427/0102/Functional-description/Introduction/About-the-core
> [3] https://gcc.gnu.org/gcc-11/changes.html#arm-targets
> [4] 
> https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-11.1.0#l141
> [5] 
> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c9d56eb777552ac5ee0c281e1f6e34b6fe929b77
> [6] 
> https://gitlab.com/qemu-project/qemu/-/commit/c74138c6c040b62e941326a4fbb25a93fdd35b72
> 
> Signed-off-by: Julien Olivain <ju.o@free.fr>

Series applied to master.
For the record, I added a note in the commit log about the binutils
support for Neoverse V2/V3.
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