From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jason Gunthorpe Subject: Re: [PATCH V4 05/18] iommu/ioasid: Redefine IOASID set and allocation APIs Date: Fri, 19 Mar 2021 09:46:45 -0300 Message-ID: <20210319124645.GP2356281@nvidia.com> References: <1614463286-97618-1-git-send-email-jacob.jun.pan@linux.intel.com> <1614463286-97618-6-git-send-email-jacob.jun.pan@linux.intel.com> <20210318172234.3e8c34f7@jacob-builder> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=u/nsU6ATM1M8lSjy/TMu9GVYVVA4i5cKPjws1WsiPcE=; b=uEritXANFQG9Bn/p5GsiLsdhMB3nJCOyTybyQHux5rmSPPBo2G6ryAUzXwr++B8XxBaveDtPL64dDaB5Q3iVDRzLcT5fPyntxu1W2y0RXngGQ8hPvLx/w9j0+MzTnnaLJCYawYG/x3kjvC9gLCw5yEKGZBs2CpquGEt3I1ooO+2UEwi1Emf+O9TJpdsubfCqnK/bwcl1yRHFdi12VZv7UxAE42iQihPC/gVX7iduaCJeB6RV5UZR/RpiYwz90nmYkHCR6zTDUNHtW/xtyT1qVIApYU/Rr5geV4OZk71gQp5nkk1YE4C01mjmHvm+lMqutkbIrv9AkoHagzMm9/iB7g== Content-Disposition: inline In-Reply-To: List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Sender: "iommu" To: Jean-Philippe Brucker Cc: "Tian, Kevin" , Alex Williamson , Raj Ashok , Jonathan Corbet , Jean-Philippe Brucker , LKML , Dave Jiang , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, Li Zefan , Johannes Weiner , Tejun Heo , cgroups-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Wu Hao , David Woodhouse On Fri, Mar 19, 2021 at 10:58:41AM +0100, Jean-Philippe Brucker wrote: > Although there is no use for it at the moment (only two upstream users and > it looks like amdkfd always uses current too), I quite like the > client-server model where the privileged process does bind() and programs > the hardware queue on behalf of the client process. This creates a lot complexity, how do does process A get a secure reference to B? How does it access the memory in B to setup the HW? Why do we need separation anyhow? SVM devices are supposed to be secure or they shouldn't do SVM. Jason