From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jason Gunthorpe Subject: Re: [PATCH V4 05/18] iommu/ioasid: Redefine IOASID set and allocation APIs Date: Thu, 1 Apr 2021 10:46:41 -0300 Message-ID: <20210401134641.GG1463678@nvidia.com> References: <20210329163147.GG2356281@nvidia.com> <20210330132830.GO2356281@nvidia.com> <20210331124038.GE1463678@nvidia.com> <20210401114648.GX1463678@nvidia.com> <20210401131533.GD1463678@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UsmoWToKgEuO9q8+ezLJ1l1ZNZ7WRArJNMv+HLs4XY8=; b=d6F6d3zM6tSVvQhCQhG2PZxTAGJ49JvXYr4+36eB8HNI8ut52fXZybYS4+Axm16RrrQpNzeSJW9EcyvnvsjS+7WndNDKK7cRlyYU8uvZMrqovBqBC++wdWuiHgVtZkrCEsaJVzWhSLH8SXZf77ZbYzfsTaT4sNphBf3/wmurKOxcMZlwvTMxmy08sgATMwESg7M3ND0dRk2kKYRIZqDvB0sMc6P9RsmyVw08P/L2HTjdZSrI8q1RFVrJYCjEfmoaG/A/+Eu39HFHt5bJjB4OmcW1cp0791wi77/uOVElejZMzQWrpHezQaGI/Lq4UJ102HRHxfuDKM6XqAYWQcNVQw== Content-Disposition: inline In-Reply-To: List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Sender: "iommu" To: "Liu, Yi L" Cc: Jean-Philippe Brucker , "Tian, Kevin" , Alex Williamson , "Raj, Ashok" , Jonathan Corbet , Jean-Philippe Brucker , LKML , "Jiang, Dave" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , Li Zefan , Johannes Weiner , Tejun Heo , "cgroups-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "Wu, Hao" , David Woodhouse On Thu, Apr 01, 2021 at 01:43:36PM +0000, Liu, Yi L wrote: > > From: Jason Gunthorpe > > Sent: Thursday, April 1, 2021 9:16 PM > > > > On Thu, Apr 01, 2021 at 01:10:48PM +0000, Liu, Yi L wrote: > > > > From: Jason Gunthorpe > > > > Sent: Thursday, April 1, 2021 7:47 PM > > > [...] > > > > I'm worried Intel views the only use of PASID in a guest is with > > > > ENQCMD, but that is not consistent with the industry. We need to see > > > > normal nested PASID support with assigned PCI VFs. > > > > > > I'm not quire flow here. Intel also allows PASID usage in guest without > > > ENQCMD. e.g. Passthru a PF to guest, and use PASID on it without > > ENQCMD. > > > > Then you need all the parts, the hypervisor calls from the vIOMMU, and > > you can't really use a vPASID. > > This is a diagram shows the vSVA setup. I'm not talking only about vSVA. Generic PASID support with arbitary mappings. And how do you deal with the vPASID vs pPASID issue if the system has a mix of physical devices and mdevs? Jason