From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jean-Philippe Brucker Subject: Re: [PATCH V4 05/18] iommu/ioasid: Redefine IOASID set and allocation APIs Date: Thu, 6 May 2021 09:23:48 +0200 Message-ID: References: <20210426123817.GQ1370958@nvidia.com> <20210504084148.4f61d0b5@jacob-builder> <20210504180050.GB1370958@nvidia.com> <20210504151154.02908c63@jacob-builder> <20210504231530.GE1370958@nvidia.com> <20210505102259.044cafdf@jacob-builder> <20210505180023.GJ1370958@nvidia.com> <20210505130446.3ee2fccd@jacob-builder> Mime-Version: 1.0 Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=eRP4wTn1wFZOpPD7g2y7lVg+V5xezb4JX6rjQ3r6xH4=; b=hUJi1Ju1LlScfHhDyP72PNYvaUr6tj3fzBj+bZ8lHKvWeTBj3NT+hIdlrf/7xRWASa 6Pzl54QcOoN1FrgBAKNgI7p/u+Z67s85MNyGYoOGpLpm+B7uGbsGiRpdBDjBmYzy+mn1 T4+0QHVMlUST9R6hoUf/e2yagDGq567NRATcCfxLdrrWXMQAlV9egyi1+gUty6dpbudK sG8R5sRiXurKziDANc3OM7wQg/58LnoDibOv9BsTRUF+iR4Ijjh1a2YVVOz/Sx6vpa/J 3lZ2bKsEQKGQxdMwD9vshCsR0OAelyfZBQ01L7pmUJ1RGEcUaLvkbSVy2Yjc9Coaiplc 6HWg== Content-Disposition: inline In-Reply-To: <20210505130446.3ee2fccd@jacob-builder> List-ID: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Jacob Pan Cc: Jason Gunthorpe , "Tian, Kevin" , Alex Williamson , "Liu, Yi L" , Auger Eric , LKML , Joerg Roedel , Lu Baolu , David Woodhouse , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , "cgroups-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Tejun Heo , Li Zefan , Johannes Weiner , Jean-Philippe Brucker , Jonathan Corbet , "Raj, Ashok" , "Wu, Hao" , "Jiang, Dave" On Wed, May 05, 2021 at 01:04:46PM -0700, Jacob Pan wrote: > > > For ARM, since the guest owns the per device PASID table. There is no > > > need to allocate PASIDs from the host nor the hypervisor. Without SWQ, > > > there is no need for global PASID/SSID either. So PASID being global > > > for ARM is for simplicity in case of host PASID/SSID. > > > > It isn't clear how ARM can support PASID and mdev but that is an > > unrelated issue.. > > > AFAIK, the current SMMU device assignment is per RID, since only one stage2 > page tables per RID, not per PASID. This is equivalent to the older VT-d > spec. prior to scalable mode. Yes that's right. Since SMMUv3 has a single level-2 page table per RID, it doesn't support assigning level-1 page tables to guests for mdevs (sub-VF devices). So no PASIDs for mdevs, which also means each guest has its own PASID space and the host doesn't track guest PASIDs. Thanks, Jean