From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D7FA1C32 for ; Tue, 16 Aug 2022 05:11:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41AE2C433C1; Tue, 16 Aug 2022 05:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660626675; bh=edf7dLjFEuJe/V8+O2M1QBQXMxOs1h0RiCDvty8gh9c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Anka/EkUBhdowoQe9Au7gwWRehfBdWxQJwrjYHOd5OvSfIkluoQsVCaDAiNvj72xu CtswVGtZ/HHBNSUnmb4Mgji1MBRsAr4A/3pq6dEjt3LNRfoMR3O7iPVLQGKRhEstV0 qkW30ceYj2TloUX05W2I+BaIadIyL5YDYemSLKP9lcRaxLiWG0Xu+Ar1FO+ebFYACq TTBxIZLih/Wt7jQ7RUHBbT/YKN0NB1tDnRqAPhgAuJVflNywrQGYztELLwcv/woCOK Y/PxLj233V3HAvPHn8jA9uel8ZpAjCnC9VBpP4Z1eDCka1P8crr5TohDdKaFfwUqK8 SWSamsVI/J7Uw== Date: Tue, 16 Aug 2022 05:11:10 +0000 From: Tzung-Bi Shih To: Prashant Malani Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, bleung@chromium.org, Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Lee Jones , Sebastian Reichel , Tinghan Shen , Xiang wangx Subject: Re: [PATCH v5 2/7] platform/chrome: cros_typec_switch: Add switch driver Message-ID: References: <20220815063555.1384505-1-pmalani@chromium.org> <20220815063555.1384505-3-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220815063555.1384505-3-pmalani@chromium.org> On Mon, Aug 15, 2022 at 06:34:19AM +0000, Prashant Malani wrote: > Introduce a driver to configure USB Type-C mode switches and retimers > which are controlled by the Chrome OS EC (Embedded Controller). > This allows Type-C port drivers, as well as alternate mode drivers to > configure their relevant mode switches and retimers according to the > Type-C state they want to achieve. s/Chrome OS/ChromeOS/. > diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig [...] > +config CROS_TYPEC_SWITCH > + tristate "ChromeOS EC Type-C Switch Control" > + depends on MFD_CROS_EC_DEV && TYPEC && ACPI > + default MFD_CROS_EC_DEV > + help > + If you say Y here, you get support for configuring the Chrome OS EC Type C > + muxes and retimers. s/Chrome OS/ChromeOS/. Up to you, s/Type C/Type-C/g. > diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c > new file mode 100644 > index 000000000000..0d319e315d57 > --- /dev/null > +++ b/drivers/platform/chrome/cros_typec_switch.c > @@ -0,0 +1,170 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright 2022 Google LLC > + * > + * This driver provides the ability to configure Type C muxes and retimers which are controlled by > + * the Chrome OS EC. > + */ s/Chrome OS/ChromeOS/. > +static int cros_typec_register_switches(struct cros_typec_switch_data *sdata) > +{ > + struct cros_typec_port *port = NULL; > + struct device *dev = sdata->dev; > + struct fwnode_handle *fwnode; > + struct acpi_device *adev; > + unsigned long long index; > + int ret = 0; `port` and `ret` don't need to be initialized. > +MODULE_DESCRIPTION("Chrome OS EC Type C Switch control"); s/Chrome OS/ChromeOS/.