Re: [PATCH 5.10.y-cip 09/28] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value

Claudiu Beznea
2026-03-25T08:36:23Z

Hi, Pavel,

On 3/24/26 11:33, Pavel Machek wrote:
> Hi!
>
>> commit d5ceb9496c565eb5763c127c6eb2d2b3068ab1df upstream.
>>
>> Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum
>> waiting time between exit from a conventional reset and sending the
>> first configuration request to the device.
>>
>> As described in PCIe r6.0, sec 6.6.1 <Conventional Reset>, there are two
>> different use cases of the value:
>>
>> - "With a Downstream Port that does not support Link speeds greater
>> than 5.0 GT/s, software must wait a minimum of 100 ms following exit
>> from a Conventional Reset before sending a Configuration Request to
>> the device immediately below that Port."
>>
>> - "With a Downstream Port that supports Link speeds greater than
>> 5.0 GT/s, software must wait a minimum of 100 ms after Link training
>> completes before sending a Configuration Request to the device
>> immediately below that Port."
>>
>> [kwilczynski: commit log]
>> Link: https://lore.kernel.org/linux-pci/20240328091835.14797-21-minda.chen@starfivetech.com
>> Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
>> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
>> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>> Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
>> [claudiu.beznea: fixed conflict by keeping only the definition for
>> PCIE_RESET_CONFIG_DEVICE_WAIT_MS]
>
> I don't understand the message here. Upstream patch seems to be
> identical to this one, but context differs.

Yes, the commit d5ceb9496c565eb5763c127c6eb2d2b3068ab1df ("PCI: Add
PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value") and this patch are
identical, but, cherry-picking commit d5ceb9496c565eb5763c127c6eb2d2b3068ab1df
on top of v5.10.249-cip69 give the following conflict:

#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */

<<<<<<< HEAD

=======

#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000

/* Power stable to PERST# inactive from PCIe card Electromechanical Spec */

#define PCIE_T_PVPERL_MS 100

/*

* PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>

* Recommends 1ms to 10ms timeout to check L2 ready.

*/

#define PCIE_PME_TO_L2_TIMEOUT_US 10000

/*

* PCIe r6.0, sec 6.6.1 <Conventional Reset>

*

* - "With a Downstream Port that does not support Link speeds greater

* than 5.0 GT/s, software must wait a minimum of 100 ms following exit

* from a Conventional Reset before sending a Configuration Request to

* the device immediately below that Port."

*

* - "With a Downstream Port that supports Link speeds greater than

* 5.0 GT/s, software must wait a minimum of 100 ms after Link training

* completes before sending a Configuration Request to the device

* immediately below that Port."

*/

#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100

>>>>>>> d5ceb9496c56 (PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time
value)
extern const unsigned char pcie_link_speed[];

extern bool pci_early_dump;

So, I had to manually adjust it and keep only the
PCIE_RESET_CONFIG_DEVICE_WAIT_MS define along with its documentation.

Thank you,
Claudiu