[PATCH 5.10.y-cip 26/28] arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock

Claudiu
2026-03-11T11:04:40Z

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

commit 1a66160fb28abcd228f69e00bb183a4749f23805 upstream.

Versa3 clock generator available on RZ/G3S SMARC Module provides the
reference clock for SoC PCIe interface. Update the device tree to reflect
this connection.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20251119143523.977085-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 7c40532fc869..b11f2e49748b 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -170,6 +170,11 @@ a0 80 30 30 9c
};
};

+&pcie_port0 {
+ clocks = <&versa3 5>;
+ clock-names = "ref";
+};
+
#if SW_CONFIG2 == SW_ON
/* SD0 slot */
&sdhi0 {
--
2.43.0