Re: [PATCH 5.10.y-cip 09/28] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value

Pavel Machek
2026-03-24T09:33:45Z

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Hi!

> commit d5ceb9496c565eb5763c127c6eb2d2b3068ab1df upstream.
>
> Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum
> waiting time between exit from a conventional reset and sending the
> first configuration request to the device.
>
> As described in PCIe r6.0, sec 6.6.1 <Conventional Reset>, there are two
> different use cases of the value:
>
> - "With a Downstream Port that does not support Link speeds greater
> than 5.0 GT/s, software must wait a minimum of 100 ms following exit
> from a Conventional Reset before sending a Configuration Request to
> the device immediately below that Port."
>
> - "With a Downstream Port that supports Link speeds greater than
> 5.0 GT/s, software must wait a minimum of 100 ms after Link training
> completes before sending a Configuration Request to the device
> immediately below that Port."
>
> [kwilczynski: commit log]
> Link: https://lore.kernel.org/linux-pci/20240328091835.14797-21-minda.chen@starfivetech.com
> Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
> [claudiu.beznea: fixed conflict by keeping only the definition for
> PCIE_RESET_CONFIG_DEVICE_WAIT_MS]

I don't understand the message here. Upstream patch seems to be
identical to this one, but context differs.

Thanks and best regards,
Pavel

> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index c2fd92a9ee1a..a391e4db9401 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -11,6 +11,21 @@
>
> #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
>
> +/*
> + * PCIe r6.0, sec 6.6.1 <Conventional Reset>
> + *
> + * - "With a Downstream Port that does not support Link speeds greater
> + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit
> + * from a Conventional Reset before sending a Configuration Request to
> + * the device immediately below that Port."
> + *
> + * - "With a Downstream Port that supports Link speeds greater than
> + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training
> + * completes before sending a Configuration Request to the device
> + * immediately below that Port."
> + */
> +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100
> +
> extern const unsigned char pcie_link_speed[];
> extern bool pci_early_dump;
>

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