From mboxrd@z Thu Jan  1 00:00:00 1970
From: ben.hutchings@codethink.co.uk (Ben Hutchings)
Date: Tue, 22 Aug 2017 19:07:33 +0100
Subject: [cip-dev] [PATCH 01/14] ARM: dts: r8a7743: initial SoC device
	tree
In-Reply-To: <1502185828-45443-2-git-send-email-biju.das@bp.renesas.com>
References: <1502185828-45443-1-git-send-email-biju.das@bp.renesas.com>
	<1502185828-45443-2-git-send-email-biju.das@bp.renesas.com>
Message-ID: <1503425253.2047.148.camel@codethink.co.uk>
To: cip-dev@lists.cip-project.org
List-Id: cip-dev.lists.cip-project.org

On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
> The  initial r8A7743 SoC device tree including CPU0, GIC and timer.
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>

I compared this to the upstream version (commit
34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand why
the clocks are described differently, but can you explain why there's no
soc node?

Ben.

> ---
>  arch/arm/boot/dts/r8a7743.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r8a7743.dtsi
> 
> diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
> new file mode 100644
> index 0000000..8575a2f
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7743.dtsi
> @@ -0,0 +1,56 @@
> +/*
> + * Device Tree Source for the r8a7743 SoC
> + *
> + * Copyright (C) 2017 Renesas Electronics Corp.
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2.  This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	compatible = "renesas,r8a7743";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a15";
> +			reg = <0>;
> +			clock-frequency = <1500000000>;
> +		};
> +	};
> +
> +	gic: interrupt-controller at f1001000 {
> +		compatible = "arm,gic-400";
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0 0xf1001000 0 0x1000>,
> +		      <0 0xf1002000 0 0x1000>,
> +		      <0 0xf1004000 0 0x2000>,
> +		      <0 0xf1006000 0 0x2000>;
> +		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
> +				   IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) |
> +				    IRQ_TYPE_LEVEL_LOW)>,
> +			     <1 14 (GIC_CPU_MASK_SIMPLE(2) |
> +				    IRQ_TYPE_LEVEL_LOW)>,
> +			     <1 11 (GIC_CPU_MASK_SIMPLE(2) |
> +				    IRQ_TYPE_LEVEL_LOW)>,
> +			     <1 10 (GIC_CPU_MASK_SIMPLE(2) |
> +				    IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +};

-- 
Ben Hutchings
Software Developer, Codethink Ltd.