* [cip-dev] [PATCH 4.19.y-cip 1/4] arm64: dts: renesas: r8a774c0: Fix cpu nodes style
2019-07-15 13:47 [cip-dev] [PATCH 4.19.y-cip 0/4] Add CAN support Biju Das
@ 2019-07-15 13:48 ` Biju Das
2019-07-15 13:48 ` [cip-dev] [PATCH 4.19.y-cip 2/4] arm64: dts: renesas: r8a774c0: Add CAN nodes Biju Das
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Biju Das @ 2019-07-15 13:48 UTC (permalink / raw)
To: cip-dev
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
commit 12ce412b2cc6aea88c9c93e6303372f72014efc6 upstream.
We usually leave a space between "=" and the value of device
tree properties, but unfortunately that was overlooked for the
"clocks" property of cpu at 0 and cpu at 1.
This patch fixes the spacing with the "clocks" property of
cpu at 0 and cpu at 1.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 8a2e4d8..8678da4 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -76,7 +76,7 @@
power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
+ clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@@ -87,7 +87,7 @@
power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
+ clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 2/4] arm64: dts: renesas: r8a774c0: Add CAN nodes
2019-07-15 13:47 [cip-dev] [PATCH 4.19.y-cip 0/4] Add CAN support Biju Das
2019-07-15 13:48 ` [cip-dev] [PATCH 4.19.y-cip 1/4] arm64: dts: renesas: r8a774c0: Fix cpu nodes style Biju Das
@ 2019-07-15 13:48 ` Biju Das
2019-07-15 13:48 ` [cip-dev] [PATCH 4.19.y-cip 3/4] arm64: dts: renesas: r8a774c0: Add clkp2 clock to " Biju Das
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Biju Das @ 2019-07-15 13:48 UTC (permalink / raw)
To: cip-dev
commit 59c3a00d6d41f72d9993e3a33b6cf8a396efffc5 upstream.
Add the device nodes for both RZ/G2E CAN channels.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 8678da4..064fbda 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -964,6 +964,30 @@
status = "disabled";
};
+ can0: can at e6c30000 {
+ compatible = "renesas,can-r8a774c0",
+ "renesas,rcar-gen3-can";
+ reg = <0 0xe6c30000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>, <&can_clk>;
+ clock-names = "clkp1", "can_clk";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can at e6c38000 {
+ compatible = "renesas,can-r8a774c0",
+ "renesas,rcar-gen3-can";
+ reg = <0 0xe6c38000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>, <&can_clk>;
+ clock-names = "clkp1", "can_clk";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
pwm0: pwm at e6e30000 {
compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 3/4] arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes
2019-07-15 13:47 [cip-dev] [PATCH 4.19.y-cip 0/4] Add CAN support Biju Das
2019-07-15 13:48 ` [cip-dev] [PATCH 4.19.y-cip 1/4] arm64: dts: renesas: r8a774c0: Fix cpu nodes style Biju Das
2019-07-15 13:48 ` [cip-dev] [PATCH 4.19.y-cip 2/4] arm64: dts: renesas: r8a774c0: Add CAN nodes Biju Das
@ 2019-07-15 13:48 ` Biju Das
2019-07-15 13:48 ` [cip-dev] [PATCH 4.19.y-cip 4/4] arm64: dts: renesas: cat875: Add CAN support Biju Das
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Biju Das @ 2019-07-15 13:48 UTC (permalink / raw)
To: cip-dev
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
commit 036bc85c1d06ef0a0924aed3fbbef8dccb86b9a1 upstream.
According to the latest information, clkp2 is available on RZ/G2.
Modify CAN0 and CAN1 nodes accordingly.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 064fbda..b6f6929 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -969,8 +969,10 @@
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 916>, <&can_clk>;
- clock-names = "clkp1", "can_clk";
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
@@ -981,8 +983,10 @@
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 915>, <&can_clk>;
- clock-names = "clkp1", "can_clk";
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 4/4] arm64: dts: renesas: cat875: Add CAN support
2019-07-15 13:47 [cip-dev] [PATCH 4.19.y-cip 0/4] Add CAN support Biju Das
` (2 preceding siblings ...)
2019-07-15 13:48 ` [cip-dev] [PATCH 4.19.y-cip 3/4] arm64: dts: renesas: r8a774c0: Add clkp2 clock to " Biju Das
@ 2019-07-15 13:48 ` Biju Das
2019-07-15 21:58 ` [cip-dev] [PATCH 4.19.y-cip 0/4] " Pavel Machek
2019-07-16 11:31 ` Pavel Machek
5 siblings, 0 replies; 7+ messages in thread
From: Biju Das @ 2019-07-15 13:48 UTC (permalink / raw)
To: cip-dev
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
commit e64f2c4b3aba6832758afe030ea4a703148546d7 upstream.
Add CAN support to the CAT875 sub board.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/cat875.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
index 14db667..aaefc3a 100644
--- a/arch/arm64/boot/dts/renesas/cat875.dtsi
+++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
@@ -30,6 +30,18 @@
};
};
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-0 = <&can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&pciec0 {
status = "okay";
};
@@ -41,4 +53,14 @@
function = "avb";
};
};
+
+ can0_pins: can0 {
+ groups = "can0_data";
+ function = "can0";
+ };
+
+ can1_pins: can1 {
+ groups = "can1_data";
+ function = "can1";
+ };
};
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 0/4] Add CAN support
2019-07-15 13:47 [cip-dev] [PATCH 4.19.y-cip 0/4] Add CAN support Biju Das
` (3 preceding siblings ...)
2019-07-15 13:48 ` [cip-dev] [PATCH 4.19.y-cip 4/4] arm64: dts: renesas: cat875: Add CAN support Biju Das
@ 2019-07-15 21:58 ` Pavel Machek
2019-07-16 11:31 ` Pavel Machek
5 siblings, 0 replies; 7+ messages in thread
From: Pavel Machek @ 2019-07-15 21:58 UTC (permalink / raw)
To: cip-dev
On Mon 2019-07-15 14:47:59, Biju Das wrote:
> This patch series add CAN support to CAT875 sub board.
> Also it fixes cpu node style.
>
> This patch series is based on linux-4.19.y-cip and all the patches
> in this series are cherry-picked from linux rc tree.
>
> This patch series is depend on the below patch series
> https://patchwork.kernel.org/project/cip-dev/list/?series=145919
This looks good to me.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 7+ messages in thread* [cip-dev] [PATCH 4.19.y-cip 0/4] Add CAN support
2019-07-15 13:47 [cip-dev] [PATCH 4.19.y-cip 0/4] Add CAN support Biju Das
` (4 preceding siblings ...)
2019-07-15 21:58 ` [cip-dev] [PATCH 4.19.y-cip 0/4] " Pavel Machek
@ 2019-07-16 11:31 ` Pavel Machek
5 siblings, 0 replies; 7+ messages in thread
From: Pavel Machek @ 2019-07-16 11:31 UTC (permalink / raw)
To: cip-dev
On Mon 2019-07-15 14:47:59, Biju Das wrote:
> This patch series add CAN support to CAT875 sub board.
> Also it fixes cpu node style.
>
> This patch series is based on linux-4.19.y-cip and all the patches
> in this series are cherry-picked from linux rc tree.
Thanks; applied and pushed out.
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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