From: pavel@denx.de (Pavel Machek)
To: cip-dev@lists.cip-project.org
Subject: [cip-dev] [PATCH 4.19.y-cip 08/23] clk: renesas: rcar-gen3: Add spinlock
Date: Tue, 16 Jul 2019 13:17:53 +0200 [thread overview]
Message-ID: <20190716111753.GA24157@amd> (raw)
In-Reply-To: <1563197408-59548-9-git-send-email-biju.das@bp.renesas.com>
Hi!
> commit 875e8f6b0156c0ad56fd0c29c78e3f2f67ec0b16 upstream.
>
> Protect the CPG register read-modify-write sequence with a spinlock.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
> index 37be0e8..3bef9f2 100644
> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -33,14 +33,19 @@
>
> #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
>
> +static spinlock_t cpg_lock;
> +
This is a bit unusual. I'd expect the the lock to be in data structure
describing the hardware... but maybe the hardware abstraction here is
so simple that we can get away with this.
> static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
> {
> + unsigned long flags;
> u32 val;
>
> + spin_lock_irqsave(&cpg_lock, flags);
> val = readl(reg);
> val &= ~clear;
> val |= set;
> writel(val, reg);
> + spin_unlock_irqrestore(&cpg_lock, flags);
> };
>
> struct cpg_simple_notifier {
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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next prev parent reply other threads:[~2019-07-16 11:17 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-15 13:29 [cip-dev] [PATCH 4.19.y-cip 00/23] Clock enhancements Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 01/23] clk: renesas: r8a774a1: Add CPEX clock Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 02/23] clk: renesas: rcar-gen3: Set state when registering SD clocks Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 03/23] clk: renesas: rcar-gen3: Add documentation for " Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 04/23] clk: renesas: rcar-gen3: Add HS400 quirk for SD clock Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 05/23] clk: renesas: Remove usage of CLK_IS_BASIC Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 06/23] clk: renesas: r8a774a1: Add missing CANFD clock Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 07/23] clk: renesas: rcar-gen3: Factor out cpg_reg_modify() Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 08/23] clk: renesas: rcar-gen3: Add spinlock Biju Das
2019-07-16 11:17 ` Pavel Machek [this message]
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 09/23] clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 10/23] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 11/23] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 12/23] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 13/23] clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 14/23] math64: New DIV64_U64_ROUND_CLOSEST helper Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 15/23] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents Biju Das
2019-07-16 11:22 ` Pavel Machek
2019-07-16 12:01 ` Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 16/23] clk: renesas: r8a774c0: Add Z2 clock Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 17/23] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 18/23] clk: renesas: rcar-gen3: Correct parent clock of HS-USB Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 19/23] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 20/23] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 21/23] clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value Biju Das
2019-07-16 11:24 ` Pavel Machek
2019-07-16 11:56 ` Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 22/23] clk: renesas: rcar-gen3: Remove unused variable Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 23/23] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices Biju Das
2019-07-15 19:50 ` [cip-dev] [PATCH 4.19.y-cip 00/23] Clock enhancements Pavel Machek
2019-07-15 21:57 ` Pavel Machek
2019-07-16 6:45 ` Biju Das
2019-07-16 11:28 ` Pavel Machek
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