From: "Pavel Machek" <pavel@ucw.cz>
To: cip-dev@lists.cip-project.org
Cc: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>,
Chris Paterson <chris.paterson2@renesas.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [cip-dev] [PATCH 4.4.y-cip] serial: sh-sci: Make sure status register SCxSR is read in correct sequence
Date: Fri, 17 Jul 2020 10:24:58 +0200 [thread overview]
Message-ID: <20200717082458.GA10436@amd> (raw)
In-Reply-To: <1594905847-54471-1-git-send-email-biju.das.jz@bp.renesas.com>
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Hi!
> From: Kazuhiro Fujita <kazuhiro.fujita.jg@renesas.com>
>
> commit 3dc4db3662366306e54ddcbda4804acb1258e4ba upstream.
>
> For SCIF and HSCIF interfaces the SCxSR register holds the status of
> data that is to be read next from SCxRDR register, But where as for
> SCIFA and SCIFB interfaces SCxSR register holds status of data that is
> previously read from SCxRDR register.
>
> This patch makes sure the status register is read depending on the port
> types so that errors are caught accordingly.
Looks good to me.
> Cc: <stable@vger.kernel.org>
I notice this applies cleanly to v4.4-stable. Was this submitted to
4.4 / do you need some help there?
Does this have user-visible impact?
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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next prev parent reply other threads:[~2020-07-17 8:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-16 13:24 [cip-dev] [PATCH 4.4.y-cip] serial: sh-sci: Make sure status register SCxSR is read in correct sequence Biju Das
2020-07-17 6:34 ` Nobuhiro Iwamatsu
2020-07-17 21:02 ` Pavel Machek
2020-07-17 8:24 ` Pavel Machek [this message]
2020-07-17 9:00 ` Biju Das
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