From: Pavel Machek <pavel@denx.de>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK
Date: Wed, 15 Dec 2021 11:05:37 +0100 [thread overview]
Message-ID: <20211215100537.GA18047@amd> (raw)
In-Reply-To: <20211215004612.13289-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
[-- Attachment #1: Type: text/plain, Size: 855 bytes --]
Hi!
> This patch series adds initial support for Renesas RZ/G2L SoC [0] and
> Renesas RZ/G2L SMARC EVK [1].
>
> The RZ/G2L microprocessor includes a Cortex-A55 (1.2 GHz) CPU, 16-bit
> DDR3L/DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec
> (H.264). It also has many interfaces such as camera input, display output,
> USB 2.0, and Gbit-Ether, making it ideal for applications such as
> entry-class industrial human-machine interfaces (HMIs) and embedded devices
> with video capabilities.
I have reviewed patches and they look okay to me. I'll proceed with
testing.
Do we have suitable board in the test lab / is there plan to add one?
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
next prev parent reply other threads:[~2021-12-15 10:06 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-15 0:46 [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK Lad Prabhakar
2021-12-15 0:46 ` [PATCH 5.10.y-cip 1/7] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC Lad Prabhakar
2021-12-15 0:46 ` [PATCH 5.10.y-cip 2/7] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants Lad Prabhakar
2021-12-15 0:46 ` [PATCH 5.10.y-cip 3/7] dt-bindings: arm: renesas: Document SMARC EVK Lad Prabhakar
2021-12-15 0:46 ` [PATCH 5.10.y-cip 4/7] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller Lad Prabhakar
2021-12-15 0:46 ` [PATCH 5.10.y-cip 5/7] soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's Lad Prabhakar
2021-12-15 0:46 ` [PATCH 5.10.y-cip 6/7] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's Lad Prabhakar
2021-12-15 0:46 ` [PATCH 5.10.y-cip 7/7] arm64: defconfig: Enable ARCH_R9A07G044 Lad Prabhakar
2021-12-15 10:05 ` Pavel Machek [this message]
2021-12-15 10:31 ` [PATCH 5.10.y-cip 0/7] Add binding and SoC identification for Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK Prabhakar Mahadev Lad
2021-12-15 10:34 ` [cip-dev] " Chris Paterson
2021-12-16 0:40 ` nobuhiro1.iwamatsu
2021-12-16 9:52 ` Chris Paterson
2021-12-16 20:46 ` nobuhiro1.iwamatsu
2021-12-16 5:10 ` nobuhiro1.iwamatsu
2021-12-16 9:08 ` Pavel Machek
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211215100537.GA18047@amd \
--to=pavel@denx.de \
--cc=biju.das.jz@bp.renesas.com \
--cc=cip-dev@lists.cip-project.org \
--cc=nobuhiro1.iwamatsu@toshiba.co.jp \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox