From: Pavel Machek <pavel@denx.de>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 05/24] clk: renesas: Add CPG core wrapper for RZ/G2L SoC
Date: Fri, 17 Dec 2021 11:10:54 +0100 [thread overview]
Message-ID: <20211217101053.GA17079@amd> (raw)
In-Reply-To: <20211216125446.15451-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi!
> commit ef3c613ccd68a78727b817c3dacf4a68d1ffc67f upstream.
>
> Add CPG core wrapper for RZ/G2L family.
>
> Based on a patch in the BSP by Binh Nguyen
> <binh.nguyen.jz@renesas.com>.
Some comments below.
> +static struct clk * __init
> +rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
...
> + pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
> + if (!pll_clk) {
> + clk = ERR_PTR(-ENOMEM);
> + return NULL;
> + }
I believe this wanted to return clk? But I'd recommend just directly
returning the ERR_PTR().
> +static struct clk
> +*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
> + void *data)
...
> + if (IS_ERR(clk))
> + dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
> + PTR_ERR(clk));
Is "\n" missing?
> +static void __init
> +rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
> + const struct rzg2l_cpg_info *info,
> + struct rzg2l_cpg_priv *priv)
> +{
> + struct mstp_clock *clock = NULL;
...
> + parent = priv->clks[mod->parent];
> + if (IS_ERR(parent)) {
> + clk = parent;
> + goto fail;
> + }
> +
> + clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
> + if (!clock) {
> + clk = ERR_PTR(-ENOMEM);
> + goto fail;
> + }
...
> +fail:
> + dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
> + mod->name, PTR_ERR(clk));
> + kfree(clock);
Should this be devm_kfree? (And is devm_kfree(NULL) ok?)
> +static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
> +{
> + if (clkspec->args_count != 2)
> + return false;
> +
> + switch (clkspec->args[0]) {
> + case CPG_MOD:
> + return true;
> +
> + default:
> + return false;
> + }
> +}
"return clkspec->args[0] == CPG_MOD" would be simpler way to say this.
> +static int __init rzg2l_cpg_probe(struct platform_device *pdev)
> +{
...
> + error = rzg2l_cpg_reset_controller_register(priv);
> + if (error)
> + return error;
> +
> + return 0;
> +}
You can just return error unconditionally.
> +static const struct of_device_id rzg2l_cpg_match[] = {
> + { /* sentinel */ }
> +};
It matches nothing? Aha, id is added in next patch.
> +/**
> + * Definitions of CPG Core Clocks
> + *
> + * These include:
> + * - Clock outputs exported to DT
> + * - External input clocks
> + * - Internal CPG clocks
> + */
This is not kerneldoc -> should not be marked with /**.
Best regards,
Pavel
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next prev parent reply other threads:[~2021-12-17 10:11 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 12:54 [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 01/24] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 02/24] serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 03/24] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 04/24] dt-bindings: clock: Add r9a07g044 CPG Clock Definitions Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 05/24] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar
2021-12-17 10:10 ` Pavel Machek [this message]
2021-12-17 11:03 ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 06/24] clk: renesas: Add support for R9A07G044 SoC Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Rename divider table Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 08/24] clk: renesas: r9a07g044: Fix P1 Clock Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 09/24] clk: renesas: r9a07g044: Add P2 Clock support Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l: Add multi clock PM support Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 11/24] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Lad Prabhakar
2021-12-17 10:19 ` Pavel Machek
2021-12-17 11:11 ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 12/24] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 13/24] arm64: dts: renesas: r9a07g044: Add SYSC node Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 14/24] dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 15/24] clk: renesas: rzg2l: Remove unneeded semicolon Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 16/24] clk: renesas: rzg2l: Fix return value and unused assignment Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 17/24] clk: renesas: rzg2l: Fix a double free on error Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 18/24] clk: renesas: rzg2l: Avoid mixing error pointers and NULL Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 19/24] clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 20/24] clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 21/24] clk: mux: provide devm_clk_hw_register_mux() Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 22/24] clk: renesas: rzg2l: Add support to handle MUX clocks Lad Prabhakar
2021-12-16 12:54 ` [PATCH 5.10.y-cip 23/24] clk: renesas: rzg2l: Add support to handle coupled clocks Lad Prabhakar
2021-12-17 10:38 ` Pavel Machek
2021-12-17 11:29 ` Prabhakar Mahadev Lad
2021-12-16 12:54 ` [PATCH 5.10.y-cip 24/24] clk: renesas: rzg2l: Fix clk status function Lad Prabhakar
2021-12-17 7:42 ` [cip-dev] [PATCH 5.10.y-cip 00/24] Add CPG and initial DTS/I for Renesas RZ/G2L SoC + SMARC EVK nobuhiro1.iwamatsu
2021-12-17 10:39 ` Pavel Machek
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