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Date: Fri, 17 Dec 2021 11:19:17 +0100
From: Pavel Machek <pavel@denx.de>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>, Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 11/24] arm64: dts: renesas: Add initial DTSI
 for RZ/G2{L,LC} SoC's
Message-ID: <20211217101917.GB17079@amd>
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Hi!

> commit 68a45525297b2e9afbd9bba807ddd2c9f69beee6 upstream.
>=20
> Add initial DTSI for RZ/G2{L,LC} SoC's.
>=20
> File structure:
> r9a07g044.dtsi  =3D> RZ/G2L family SoC common parts
> r9a07g044l1.dtsi =3D> RZ/G2L R9A07G044L1 SoC specific parts
> r9a07g044l2.dtsi =3D> RZ/G2L R9A07G044L2 SoC specific parts

I just want to double check:

> +		scif0: serial@1004b800 {
> +			compatible =3D "renesas,scif-r9a07g044";
> +			reg =3D <0 0x1004b800 0 0x400>;
> +			interrupts =3D <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names =3D "eri", "rxi", "txi",
> +					  "bri", "dri", "tei";

Are the last two interrupts supposed to be same?

Best regards,
							Pavel
--=20
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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