Hi!

> This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
> 
> All the patches have been cherry picked from v5.16-rc5.
> 
> I have created a MR [0] for cip-kernel-config (for testing purpose), which
> can later be merged once this patches have been merged.

And these are various minor nits I noticed while reviewing the code.

Best regards,
								Pavel

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index ef68dabcf4dc3..dacf43ed6d040 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -4,14 +4,14 @@
 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/G2L combined Pin and GPIO controller
+title: Renesas RZ/G2L combined pin and GPIO controller
 
 maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
 description:
-  The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
+  The Renesas SoCs of the RZ/G2L series feature a combined pin and GPIO
   controller.
   Pin multiplexing and GPIO configuration is performed on a per-pin basis.
   Each port features up to 8 pins, each of them configurable for GPIO function
diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index ee2872e7d64c6..6946dd0d0485d 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -25,7 +25,7 @@
 #include "../dmaengine.h"
 #include "../virt-dma.h"
 
-enum  rz_dmac_prep_type {
+enum rz_dmac_prep_type {
 	RZ_DMAC_DESC_MEMCPY,
 	RZ_DMAC_DESC_SLAVE_SG,
 };
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 20b2af889ca96..08d0bf139ba3a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -328,7 +328,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 		psel_val[i] = MUX_FUNC(value);
 	}
 
-	/* Register a single pin group listing all the pins we read from DT */
+	/* Register a single pin group, listing all the pins we read from DT */
 	gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
 	if (gsel < 0) {
 		ret = gsel;
@@ -612,7 +612,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
 		if (ret)
 			return ret;
 
-		/* Check config matching between to pin  */
+		/* Check config matching between the pins */
 		if (i && prev_config != *config)
 			return -EOPNOTSUPP;
 
@@ -886,7 +886,7 @@ static const u32 rzg2l_gpio_configs[] = {
 	RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
 };
 
-static  struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
+static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
 	{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
 	 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
 	{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
@@ -1109,7 +1109,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
 	pctrl->clk = devm_clk_get(pctrl->dev, NULL);
 	if (IS_ERR(pctrl->clk)) {
 		ret = PTR_ERR(pctrl->clk);
-		dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
+		dev_err(pctrl->dev, "failed to get GPIO clk: %i\n", ret);
 		return ret;
 	}
 
@@ -1127,7 +1127,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
 				       pctrl->clk);
 	if (ret) {
 		dev_err(pctrl->dev,
-			"failed to register GPIO clk disable action, %i\n",
+			"failed to register GPIO clk disable action: %i\n",
 			ret);
 		return ret;
 	}
@@ -1171,5 +1171,5 @@ static int __init rzg2l_pinctrl_init(void)
 core_initcall(rzg2l_pinctrl_init);
 
 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
-MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
+MODULE_DESCRIPTION("Pin and GPIO controller driver for RZ/G2L family");
 MODULE_LICENSE("GPL v2");


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