* [PATCH 5.10.y-cip 01/21] dt-bindings: usb: generic-ehci: Document dr_mode property
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 02/21] dt-bindings: usb: generic-ohci: " Lad Prabhakar
` (19 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 31f21e2a09a150972f9188c3a785998131e843ba upstream.
Document the optional property dr_mode present on both RZ/G2 and
R-Car Gen3 SoCs.
It fixes dtbs_check warning,
'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210630073013.22415-3-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/usb/generic-ehci.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 247ef00381ea..78b235fb76df 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -91,6 +91,11 @@ properties:
iommus:
maxItems: 1
+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 02/21] dt-bindings: usb: generic-ohci: Document dr_mode property
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 01/21] dt-bindings: usb: generic-ehci: Document dr_mode property Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 03/21] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Lad Prabhakar
` (18 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 0c29ec921059abf110434addd8b8ed9032e710c7 upstream.
Document the optional property dr_mode present on both RZ/G2 and
R-Car Gen3 SoCs.
It fixes the dtbs_check warning,
'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210630073013.22415-2-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/usb/generic-ohci.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index 2178bcc401bc..05e1db57c312 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -79,6 +79,11 @@ properties:
iommus:
maxItems: 1
+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 03/21] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 01/21] dt-bindings: usb: generic-ehci: Document dr_mode property Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 02/21] dt-bindings: usb: generic-ohci: " Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 04/21] reset: renesas: Add RZ/G2L usbphy control driver Lad Prabhakar
` (17 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 18931afe5b4fb7f91da43043c867e504e742a781 upstream.
Add device tree binding document for RZ/G2L USBPHY Control Device.
It mainly controls reset and power down of the USB/PHY.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210719121938.6532-4-biju.das.jz@bp.renesas.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../reset/renesas,rzg2l-usbphy-ctrl.yaml | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
new file mode 100644
index 000000000000..b13514e6783d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L USBPHY Control
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+ The RZ/G2L USBPHY Control mainly controls reset and power down of the
+ USB/PHY.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usbphy-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+ description: |
+ The phandle's argument in the reset specifier is the PHY reset associated
+ with the USB port.
+ 0 = Port 1 Phy reset
+ 1 = Port 2 Phy reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - power-domains
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0x11c40000 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 04/21] reset: renesas: Add RZ/G2L usbphy control driver
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (2 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 03/21] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 05/21] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Lad Prabhakar
` (16 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit bee08559701fb98b43d7061717e7c3131230aa69 upstream.
Add support for RZ/G2L USBPHY Control driver. It mainly controls
reset and power down of the USB/PHY.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719121938.6532-5-biju.das.jz@bp.renesas.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/reset/Kconfig | 7 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-rzg2l-usbphy-ctrl.c | 175 ++++++++++++++++++++++++
3 files changed, 183 insertions(+)
create mode 100644 drivers/reset/reset-rzg2l-usbphy-ctrl.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 147543ad303f..9a759b0e5a79 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -154,6 +154,13 @@ config RESET_RASPBERRYPI
interfacing with RPi4's co-processor and model these firmware
initialization routines as reset lines.
+config RESET_RZG2L_USBPHY_CTRL
+ tristate "Renesas RZ/G2L USBPHY control driver"
+ depends on ARCH_R9A07G044 || COMPILE_TEST
+ help
+ Support for USBPHY Control found on RZ/G2L family. It mainly
+ controls reset and power down of the USB/PHY.
+
config RESET_SCMI
tristate "Reset driver controlled via ARM SCMI interface"
depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 16947610cc3b..243f765cdfa2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
+obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
new file mode 100644
index 000000000000..e0704fd2b533
--- /dev/null
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L USBPHY control driver
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/reset-controller.h>
+
+#define RESET 0x000
+
+#define RESET_SEL_PLLRESET BIT(12)
+#define RESET_PLLRESET BIT(8)
+
+#define RESET_SEL_P2RESET BIT(5)
+#define RESET_SEL_P1RESET BIT(4)
+#define RESET_PHYRST_2 BIT(1)
+#define RESET_PHYRST_1 BIT(0)
+
+#define PHY_RESET_PORT2 (RESET_SEL_P2RESET | RESET_PHYRST_2)
+#define PHY_RESET_PORT1 (RESET_SEL_P1RESET | RESET_PHYRST_1)
+
+#define NUM_PORTS 2
+
+struct rzg2l_usbphy_ctrl_priv {
+ struct reset_controller_dev rcdev;
+ struct reset_control *rstc;
+ void __iomem *base;
+
+ spinlock_t lock;
+};
+
+#define rcdev_to_priv(x) container_of(x, struct rzg2l_usbphy_ctrl_priv, rcdev)
+
+static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
+ u32 port_mask = PHY_RESET_PORT1 | PHY_RESET_PORT2;
+ void __iomem *base = priv->base;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(base + RESET);
+ val |= id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
+ if (port_mask == (val & port_mask))
+ val |= RESET_PLLRESET;
+ writel(val, base + RESET);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+}
+
+static int rzg2l_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
+ void __iomem *base = priv->base;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(base + RESET);
+
+ val |= RESET_SEL_PLLRESET;
+ val &= ~(RESET_PLLRESET | (id ? PHY_RESET_PORT2 : PHY_RESET_PORT1));
+ writel(val, base + RESET);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+}
+
+static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
+ u32 port_mask;
+
+ port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
+
+ return !!(readl(priv->base + RESET) & port_mask);
+}
+
+static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
+ { .compatible = "renesas,rzg2l-usbphy-ctrl" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);
+
+static const struct reset_control_ops rzg2l_usbphy_ctrl_reset_ops = {
+ .assert = rzg2l_usbphy_ctrl_assert,
+ .deassert = rzg2l_usbphy_ctrl_deassert,
+ .status = rzg2l_usbphy_ctrl_status,
+};
+
+static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rzg2l_usbphy_ctrl_priv *priv;
+ unsigned long flags;
+ int error;
+ u32 val;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(priv->rstc))
+ return dev_err_probe(dev, PTR_ERR(priv->rstc),
+ "failed to get reset\n");
+
+ reset_control_deassert(priv->rstc);
+
+ priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops;
+ priv->rcdev.of_reset_n_cells = 1;
+ priv->rcdev.nr_resets = NUM_PORTS;
+ priv->rcdev.of_node = dev->of_node;
+ priv->rcdev.dev = dev;
+
+ error = devm_reset_controller_register(dev, &priv->rcdev);
+ if (error)
+ return error;
+
+ spin_lock_init(&priv->lock);
+ dev_set_drvdata(dev, priv);
+
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_resume_and_get(&pdev->dev);
+
+ /* put pll and phy into reset state */
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(priv->base + RESET);
+ val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1;
+ writel(val, priv->base + RESET);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+}
+
+static int rzg2l_usbphy_ctrl_remove(struct platform_device *pdev)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ pm_runtime_put(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ reset_control_assert(priv->rstc);
+
+ return 0;
+}
+
+static struct platform_driver rzg2l_usbphy_ctrl_driver = {
+ .driver = {
+ .name = "rzg2l_usbphy_ctrl",
+ .of_match_table = rzg2l_usbphy_ctrl_match_table,
+ },
+ .probe = rzg2l_usbphy_ctrl_probe,
+ .remove = rzg2l_usbphy_ctrl_remove,
+};
+module_platform_driver(rzg2l_usbphy_ctrl_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control");
+MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 05/21] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (3 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 04/21] reset: renesas: Add RZ/G2L usbphy control driver Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 06/21] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Lad Prabhakar
` (15 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 177cd475e1f12d256c9bf7de274fef7bea30cddb upstream.
Document RZ/G2L (R9A07G044L) SoC bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210727185527.19907-6-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/usb/renesas,usbhs.yaml | 26 +++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
index 737c1f47b7de..7ab36f81939c 100644
--- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
+++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
@@ -17,7 +17,9 @@ properties:
- const: renesas,rza1-usbhs
- items:
- - const: renesas,usbhs-r7s9210 # RZ/A2
+ - enum:
+ - renesas,usbhs-r7s9210 # RZ/A2
+ - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rza2-usbhs
- items:
@@ -60,7 +62,8 @@ properties:
- description: USB 2.0 clock selector
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
renesas,buswait:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -113,6 +116,25 @@ required:
- clocks
- interrupts
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,usbhs-r9a07g044
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: U2P_IXL_INT
+ - description: U2P_INT_DMA[0]
+ - description: U2P_INT_DMA[1]
+ - description: U2P_INT_DMAERR
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 06/21] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (4 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 05/21] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 07/21] phy: renesas: convert to devm_platform_ioremap_resource Lad Prabhakar
` (14 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 5711af410c28d2b9c99a91e8e6fe9ba6520771f0 upstream.
Document USB phy bindings for RZ/G2L SoC.
RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It uses
a different OTG-BC interrupt bit for device recognition. Apart from this,
the PHY reset is controlled by USBPHY control IP and Document reset is a
required property.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210727185527.19907-3-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/phy/renesas,usb2-phy.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index 829e8c7e467a..5bd85364f5de 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -30,6 +30,11 @@ properties:
- renesas,usb2-phy-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-usb2-phy
+ - items:
+ - enum:
+ - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usb2-phy # RZ/G2L family
+
reg:
maxItems: 1
@@ -94,6 +99,16 @@ required:
- clocks
- '#phy-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzg2l-usb2-phy
+ then:
+ required:
+ - resets
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 07/21] phy: renesas: convert to devm_platform_ioremap_resource
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (5 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 06/21] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 08/21] phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/G2L Lad Prabhakar
` (13 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
commit 0b5604affbec0241d72996924b2f5a33d96b860a upstream.
Use devm_platform_ioremap_resource to simplify code
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/1604642930-29019-12-git-send-email-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/phy/renesas/phy-rcar-gen2.c | 4 +---
drivers/phy/renesas/phy-rcar-gen3-pcie.c | 4 +---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 4 +---
drivers/phy/renesas/phy-rcar-gen3-usb3.c | 4 +---
4 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen2.c b/drivers/phy/renesas/phy-rcar-gen2.c
index 2e279ac0fa4d..c375a4676a3d 100644
--- a/drivers/phy/renesas/phy-rcar-gen2.c
+++ b/drivers/phy/renesas/phy-rcar-gen2.c
@@ -339,7 +339,6 @@ static int rcar_gen2_phy_probe(struct platform_device *pdev)
struct rcar_gen2_phy_driver *drv;
struct phy_provider *provider;
struct device_node *np;
- struct resource *res;
void __iomem *base;
struct clk *clk;
const struct rcar_gen2_phy_data *data;
@@ -357,8 +356,7 @@ static int rcar_gen2_phy_probe(struct platform_device *pdev)
return PTR_ERR(clk);
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
diff --git a/drivers/phy/renesas/phy-rcar-gen3-pcie.c b/drivers/phy/renesas/phy-rcar-gen3-pcie.c
index c4e4aa216936..4dc721eb9577 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-pcie.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-pcie.c
@@ -76,7 +76,6 @@ static int rcar_gen3_phy_pcie_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct phy_provider *provider;
struct rcar_gen3_phy *phy;
- struct resource *res;
void __iomem *base;
int error;
@@ -86,8 +85,7 @@ static int rcar_gen3_phy_pcie_probe(struct platform_device *pdev)
return -EINVAL;
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 2cb949f931b6..fbc55232120e 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -611,7 +611,6 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct rcar_gen3_chan *channel;
struct phy_provider *provider;
- struct resource *res;
const struct phy_ops *phy_usb2_ops;
int ret = 0, i;
@@ -624,8 +623,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
if (!channel)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- channel->base = devm_ioremap_resource(dev, res);
+ channel->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(channel->base))
return PTR_ERR(channel->base);
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb3.c b/drivers/phy/renesas/phy-rcar-gen3-usb3.c
index 566b4cf4ff38..f27d6f471629 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb3.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb3.c
@@ -133,7 +133,6 @@ static int rcar_gen3_phy_usb3_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct rcar_gen3_usb3 *r;
struct phy_provider *provider;
- struct resource *res;
int ret = 0;
struct clk *clk;
@@ -146,8 +145,7 @@ static int rcar_gen3_phy_usb3_probe(struct platform_device *pdev)
if (!r)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- r->base = devm_ioremap_resource(dev, res);
+ r->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(r->base))
return PTR_ERR(r->base);
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 08/21] phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/G2L
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (6 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 07/21] phy: renesas: convert to devm_platform_ioremap_resource Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 09/21] clk: renesas: r9a07g044: Add USB clocks/resets Lad Prabhakar
` (12 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit b0512a6ec0cd6dcea659d834592bbcb0cae127a4 upstream.
This patch adds USB2.0 PHY support for RZ/G2L SoC.
We need to use a different compatible string due to some differences
with R-Car Gen3 USB2.0 PHY. It uses line ctrl register for OTG_ID
pin changes and different OTG-BC interrupt bit for device recognition.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> # on R-Car
Link: https://lore.kernel.org/r/20210727185527.19907-4-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 97 ++++++++++++++++++------
1 file changed, 73 insertions(+), 24 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index fbc55232120e..9de617ca9daa 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -64,6 +64,7 @@
/* VBCTRL */
#define USB2_VBCTRL_OCCLREN BIT(16)
#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
+#define USB2_VBCTRL_VBOUT BIT(0)
/* LINECTRL1 */
#define USB2_LINECTRL1_DPRPD_EN BIT(19)
@@ -78,6 +79,10 @@
#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS BIT(4)
+/* RZ/G2L specific */
+#define USB2_OBINT_IDCHG_EN BIT(0)
+#define USB2_LINECTRL1_USB2_IDMON BIT(0)
+
#define NUM_OF_PHYS 4
enum rcar_gen3_phy_index {
PHY_INDEX_BOTH_HC,
@@ -112,9 +117,16 @@ struct rcar_gen3_chan {
struct mutex lock; /* protects rphys[...].powered */
enum usb_dr_mode dr_mode;
int irq;
+ u32 obint_enable_bits;
bool extcon_host;
bool is_otg_channel;
bool uses_otg_pins;
+ bool soc_no_adp_ctrl;
+};
+
+struct rcar_gen3_phy_drv_data {
+ const struct phy_ops *phy_usb2_ops;
+ bool no_adp_ctrl;
};
/*
@@ -172,14 +184,22 @@ static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
{
void __iomem *usb2_base = ch->base;
- u32 val = readl(usb2_base + USB2_ADPCTRL);
+ u32 vbus_ctrl_reg = USB2_ADPCTRL;
+ u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
+ u32 val;
dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
+ if (ch->soc_no_adp_ctrl) {
+ vbus_ctrl_reg = USB2_VBCTRL;
+ vbus_ctrl_val = USB2_VBCTRL_VBOUT;
+ }
+
+ val = readl(usb2_base + vbus_ctrl_reg);
if (vbus)
- val |= USB2_ADPCTRL_DRVVBUS;
+ val |= vbus_ctrl_val;
else
- val &= ~USB2_ADPCTRL_DRVVBUS;
- writel(val, usb2_base + USB2_ADPCTRL);
+ val &= ~vbus_ctrl_val;
+ writel(val, usb2_base + vbus_ctrl_reg);
}
static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
@@ -188,9 +208,9 @@ static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
u32 val = readl(usb2_base + USB2_OBINTEN);
if (ch->uses_otg_pins && enable)
- val |= USB2_OBINT_BITS;
+ val |= ch->obint_enable_bits;
else
- val &= ~USB2_OBINT_BITS;
+ val &= ~ch->obint_enable_bits;
writel(val, usb2_base + USB2_OBINTEN);
}
@@ -252,6 +272,9 @@ static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
if (!ch->uses_otg_pins)
return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
+ if (ch->soc_no_adp_ctrl)
+ return !!(readl(ch->base + USB2_LINECTRL1) & USB2_LINECTRL1_USB2_IDMON);
+
return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
}
@@ -376,16 +399,17 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD;
writel(val, usb2_base + USB2_LINECTRL1);
- val = readl(usb2_base + USB2_VBCTRL);
- val &= ~USB2_VBCTRL_OCCLREN;
- writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
- val = readl(usb2_base + USB2_ADPCTRL);
- writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
-
+ if (!ch->soc_no_adp_ctrl) {
+ val = readl(usb2_base + USB2_VBCTRL);
+ val &= ~USB2_VBCTRL_OCCLREN;
+ writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
+ val = readl(usb2_base + USB2_ADPCTRL);
+ writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
+ }
msleep(20);
writel(0xffffffff, usb2_base + USB2_OBINTSTA);
- writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
+ writel(ch->obint_enable_bits, usb2_base + USB2_OBINTEN);
rcar_gen3_device_recognition(ch);
}
@@ -397,9 +421,9 @@ static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
u32 status = readl(usb2_base + USB2_OBINTSTA);
irqreturn_t ret = IRQ_NONE;
- if (status & USB2_OBINT_BITS) {
+ if (status & ch->obint_enable_bits) {
dev_vdbg(ch->dev, "%s: %08x\n", __func__, status);
- writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
+ writel(ch->obint_enable_bits, usb2_base + USB2_OBINTSTA);
rcar_gen3_device_recognition(ch);
ret = IRQ_HANDLED;
}
@@ -535,26 +559,45 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
.owner = THIS_MODULE,
};
+static const struct rcar_gen3_phy_drv_data rcar_gen3_phy_usb2_data = {
+ .phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
+ .no_adp_ctrl = false,
+};
+
+static const struct rcar_gen3_phy_drv_data rz_g1c_phy_usb2_data = {
+ .phy_usb2_ops = &rz_g1c_phy_usb2_ops,
+ .no_adp_ctrl = false,
+};
+
+static const struct rcar_gen3_phy_drv_data rz_g2l_phy_usb2_data = {
+ .phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
+ .no_adp_ctrl = true,
+};
+
static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
{
.compatible = "renesas,usb2-phy-r8a77470",
- .data = &rz_g1c_phy_usb2_ops,
+ .data = &rz_g1c_phy_usb2_data,
},
{
.compatible = "renesas,usb2-phy-r8a7795",
- .data = &rcar_gen3_phy_usb2_ops,
+ .data = &rcar_gen3_phy_usb2_data,
},
{
.compatible = "renesas,usb2-phy-r8a7796",
- .data = &rcar_gen3_phy_usb2_ops,
+ .data = &rcar_gen3_phy_usb2_data,
},
{
.compatible = "renesas,usb2-phy-r8a77965",
- .data = &rcar_gen3_phy_usb2_ops,
+ .data = &rcar_gen3_phy_usb2_data,
+ },
+ {
+ .compatible = "renesas,rzg2l-usb2-phy",
+ .data = &rz_g2l_phy_usb2_data,
},
{
.compatible = "renesas,rcar-gen3-usb2-phy",
- .data = &rcar_gen3_phy_usb2_ops,
+ .data = &rcar_gen3_phy_usb2_data,
},
{ /* sentinel */ },
};
@@ -608,10 +651,10 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np)
static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
{
+ const struct rcar_gen3_phy_drv_data *phy_data;
struct device *dev = &pdev->dev;
struct rcar_gen3_chan *channel;
struct phy_provider *provider;
- const struct phy_ops *phy_usb2_ops;
int ret = 0, i;
if (!dev->of_node) {
@@ -627,6 +670,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
if (IS_ERR(channel->base))
return PTR_ERR(channel->base);
+ channel->obint_enable_bits = USB2_OBINT_BITS;
/* get irq number here and request_irq for OTG in phy_init */
channel->irq = platform_get_irq_optional(pdev, 0);
channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
@@ -653,16 +697,21 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
* And then, phy-core will manage runtime pm for this device.
*/
pm_runtime_enable(dev);
- phy_usb2_ops = of_device_get_match_data(dev);
- if (!phy_usb2_ops) {
+
+ phy_data = of_device_get_match_data(dev);
+ if (!phy_data) {
ret = -EINVAL;
goto error;
}
+ channel->soc_no_adp_ctrl = phy_data->no_adp_ctrl;
+ if (phy_data->no_adp_ctrl)
+ channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
+
mutex_init(&channel->lock);
for (i = 0; i < NUM_OF_PHYS; i++) {
channel->rphys[i].phy = devm_phy_create(dev, NULL,
- phy_usb2_ops);
+ phy_data->phy_usb2_ops);
if (IS_ERR(channel->rphys[i].phy)) {
dev_err(dev, "Failed to create USB2 PHY\n");
ret = PTR_ERR(channel->rphys[i].phy);
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 09/21] clk: renesas: r9a07g044: Add USB clocks/resets
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (7 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 08/21] phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/G2L Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 10/21] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Lad Prabhakar
` (11 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 03fa6e4b2622035389a4beb9699551d63d130493 upstream.
Add clock/reset entries for USB PHY control, USB2.0 host and device.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210630073013.22415-5-biju.das.jz@bp.renesas.com
[geert: s/usb0_device/usb0_func]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 740355fe7d5c..016a69f80a05 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -96,6 +96,14 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
0x52c, 0),
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
0x52c, 1),
+ DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
+ 0x578, 0),
+ DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
+ 0x578, 1),
+ DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
+ 0x578, 2),
+ DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
+ 0x578, 3),
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
0x580, 0),
DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
@@ -126,6 +134,10 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
+ DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
+ DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
+ DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
+ DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 10/21] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (8 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 09/21] clk: renesas: r9a07g044: Add USB clocks/resets Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 11/21] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Lad Prabhakar
` (10 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 73484ab0120c66e32262365fde38eafde57bebac upstream.
Add USB2.0 phy and host support to SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210812151808.7916-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 95 ++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 7c83a8d39351..655627c9da02 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -257,6 +257,101 @@
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0 0x11c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ status = "disabled";
+ };
+
+ ohci0: usb@11c50000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c50000 0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11c70000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c70000 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11c50100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c50100 0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11c70100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c70100 0 0x100>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c50200 0 0x700>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c70200 0 0x700>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 11/21] arm64: dts: renesas: r9a07g044: Add USB2.0 device support
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (9 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 10/21] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 12/21] arm64: dts: renesas: rzg2l-smarc: Enable USB2.0 support Lad Prabhakar
` (9 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit f86e17d6e8be33083d20ab802840ce68a9fff40f upstream.
Add USB2.0 device support to RZ/G2L SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210812151808.7916-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 655627c9da02..5818adc1ede9 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -352,6 +352,25 @@
power-domains = <&cpg>;
status = "disabled";
};
+
+ hsusb: usb@11c60000 {
+ compatible = "renesas,usbhs-r9a07g044",
+ "renesas,rza2-usbhs";
+ reg = <0 0x11c60000 0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 12/21] arm64: dts: renesas: rzg2l-smarc: Enable USB2.0 support
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (10 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 11/21] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 13/21] dt-bindings: can: rcar_canfd: Group tuples in pin control properties Lad Prabhakar
` (8 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit cbcd120394268c5b2781bca345e1631d551a3227 upstream.
Enable USB2.0 Host/Device support on RZ/G2L SMARC EVK.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210920182955.13445-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 61 ++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 0987163f25ee..7ecd4a3f4175 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -17,17 +17,63 @@
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
+
+ usb0_vbus_otg: regulator-usb0-vbus-otg {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB0_VBUS_OTG";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
};
&extal_clk {
clock-frequency = <24000000>;
};
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
&pinctrl {
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
+
+ usb0_pins: usb0 {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
+ <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
+ };
+
+ usb1_pins: usb1 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
+ };
};
&scif0 {
@@ -35,3 +81,18 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 13/21] dt-bindings: can: rcar_canfd: Group tuples in pin control properties
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (11 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 12/21] arm64: dts: renesas: rzg2l-smarc: Enable USB2.0 support Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 14/21] dt-bindings: can: rcar_canfd: Convert to json-schema Lad Prabhakar
` (7 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 6faf708793cb4edf2472d8e4d7014f407b65cdb7 upstream.
To improve human readability and enable automatic validation, the tuples
in "pinctrl-*" properties should be grouped using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20210204125937.1646305-1-geert+renesas@glider.be
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
index 22cf2a889b2c..248c4ed97a0a 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -97,7 +97,7 @@ E.g. below enables Channel 0 alone in the board using External clock
as fCAN clock.
&canfd {
- pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+ pinctrl-0 = <&canfd0_pins>, <&can_clk_pins>;
pinctrl-names = "default";
status = "okay";
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 14/21] dt-bindings: can: rcar_canfd: Convert to json-schema
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (12 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 13/21] dt-bindings: can: rcar_canfd: Group tuples in pin control properties Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family Lad Prabhakar
` (6 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 8a5e7d19c8c747e3e7bfa0283a54742b103afcb5 upstream.
Convert the Renesas R-Car CAN FD Controller Device Tree binding
documentation to json-schema.
Document missing properties.
The CANFD clock needs to be configured for the maximum frequency on
R-Car V3M and V3H, too.
Update the example to match reality.
Link: https://lore.kernel.org/r/905134c87f72e2d8e37c309e0ce28ecd7d4f3992.1620323639.git.geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/net/can/rcar_canfd.txt | 107 ---------------
.../bindings/net/can/renesas,rcar-canfd.yaml | 122 ++++++++++++++++++
2 files changed, 122 insertions(+), 107 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
create mode 100644 Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml
diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
deleted file mode 100644
index 248c4ed97a0a..000000000000
--- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-Renesas R-Car CAN FD controller Device Tree Bindings
-----------------------------------------------------
-
-Required properties:
-- compatible: Must contain one or more of the following:
- - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
- - "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller.
- - "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller.
- - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
- - "renesas,r8a774e1-canfd" for R8A774E1 (RZ/G2H) compatible controller.
- - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
- - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
- - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller.
- - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller.
- - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller.
- - "renesas,r8a77990-canfd" for R8A77990 (R-Car E3) compatible controller.
- - "renesas,r8a77995-canfd" for R8A77995 (R-Car D3) compatible controller.
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first, followed by the
- family-specific and/or generic versions.
-
-- reg: physical base address and size of the R-Car CAN FD register map.
-- interrupts: interrupt specifiers for the Channel & Global interrupts
-- clocks: phandles and clock specifiers for 3 clock inputs.
-- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
-- pinctrl-0: pin control group to be used for this controller.
-- pinctrl-names: must be "default".
-
-Required child nodes:
-The controller supports two channels and each is represented as a child node.
-The name of the child nodes are "channel0" and "channel1" respectively. Each
-child node supports the "status" property only, which is used to
-enable/disable the respective channel.
-
-Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795,
-R8A7796, R8A77965, R8A77990, and R8A77995:
-In the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN
-and CAN FD controller at the same time. It needs to be scaled to maximum
-frequency if any of these controllers use it. This is done using the below
-properties:
-
-- assigned-clocks: phandle of canfd clock.
-- assigned-clock-rates: maximum frequency of this clock.
-
-Optional property:
-The controller can operate in either CAN FD only mode (default) or
-Classical CAN only mode. The mode is global to both the channels. In order to
-enable the later, define the following optional property.
- - renesas,no-can-fd: puts the controller in Classical CAN only mode.
-
-Example
--------
-
-SoC common .dtsi file:
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a7795-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A7795_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&cpg>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
-Board specific .dts file:
-
-E.g. below enables Channel 1 alone in the board in Classical CAN only mode.
-
-&canfd {
- pinctrl-0 = <&canfd1_pins>;
- pinctrl-names = "default";
- renesas,no-can-fd;
- status = "okay";
-
- channel1 {
- status = "okay";
- };
-};
-
-E.g. below enables Channel 0 alone in the board using External clock
-as fCAN clock.
-
-&canfd {
- pinctrl-0 = <&canfd0_pins>, <&can_clk_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- channel0 {
- status = "okay";
- };
-};
diff --git a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml
new file mode 100644
index 000000000000..0b33ba9ccb47
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car CAN FD Controller
+
+maintainers:
+ - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
+
+allOf:
+ - $ref: can-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r8a774a1-canfd # RZ/G2M
+ - renesas,r8a774b1-canfd # RZ/G2N
+ - renesas,r8a774c0-canfd # RZ/G2E
+ - renesas,r8a774e1-canfd # RZ/G2H
+ - renesas,r8a7795-canfd # R-Car H3
+ - renesas,r8a7796-canfd # R-Car M3-W
+ - renesas,r8a77965-canfd # R-Car M3-N
+ - renesas,r8a77970-canfd # R-Car V3M
+ - renesas,r8a77980-canfd # R-Car V3H
+ - renesas,r8a77990-canfd # R-Car E3
+ - renesas,r8a77995-canfd # R-Car D3
+ - const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Channel interrupt
+ - description: Global interrupt
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: fck
+ - const: canfd
+ - const: can_clk
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ renesas,no-can-fd:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The controller can operate in either CAN FD only mode (default) or
+ Classical CAN only mode. The mode is global to both the channels.
+ Specify this property to put the controller in Classical CAN only mode.
+
+ assigned-clocks:
+ description:
+ Reference to the CANFD clock. The CANFD clock is a div6 clock and can be
+ used by both CAN (if present) and CAN FD controllers at the same time.
+ It needs to be scaled to maximum frequency if any of these controllers
+ use it.
+
+ assigned-clock-rates:
+ description: Maximum frequency of the CANFD clock.
+
+patternProperties:
+ "^channel[01]$":
+ type: object
+ description:
+ The controller supports two channels and each is represented as a child
+ node. Each child node supports the "status" property only, which
+ is used to enable/disable the respective channel.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - assigned-clocks
+ - assigned-clock-rates
+ - channel0
+ - channel1
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ canfd: can@e66c0000 {
+ compatible = "renesas,r8a7795-canfd",
+ "renesas,rcar-gen3-canfd";
+ reg = <0xe66c0000 0x8000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 914>,
+ <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 914>;
+
+ channel0 {
+ };
+
+ channel1 {
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (13 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 14/21] dt-bindings: can: rcar_canfd: Convert to json-schema Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 23:13 ` Pavel Machek
2021-12-22 13:49 ` [PATCH 5.10.y-cip 16/21] can: rcar_canfd: rcar_canfd_handle_channel_tx(): fix redundant assignment Lad Prabhakar
` (5 subsequent siblings)
20 siblings, 1 reply; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 76e9353a80e9e9ff65b362a6dd8545d84427ec30 upstream.
CANFD block on RZ/G2L SoC is almost identical to one found on
R-Car Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel
are split into different sources and the IP doesn't divide (1/2)
CANFD clock within the IP.
This patch adds compatible string for RZ/G2L family and splits
the irq handlers to accommodate both RZ/G2L and R-Car Gen3 SoC's.
Link: https://lore.kernel.org/r/20210727133022.634-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
[mkl: fixed typo: recieve -> receive, thanks Geert]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/net/can/rcar/rcar_canfd.c | 338 +++++++++++++++++++++++-------
1 file changed, 265 insertions(+), 73 deletions(-)
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index de59dd6aad29..0b0ceae0d844 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -37,9 +37,15 @@
#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
+#include <linux/reset.h>
#define RCANFD_DRV_NAME "rcar_canfd"
+enum rcanfd_chip_id {
+ RENESAS_RCAR_GEN3 = 0,
+ RENESAS_RZG2L,
+};
+
/* Global register bits */
/* RSCFDnCFDGRMCFG */
@@ -513,6 +519,9 @@ struct rcar_canfd_global {
enum rcar_canfd_fcanclk fcan; /* CANFD or Ext clock */
unsigned long channels_mask; /* Enabled channels mask */
bool fdmode; /* CAN FD or Classical CAN only mode */
+ struct reset_control *rstc1;
+ struct reset_control *rstc2;
+ enum rcanfd_chip_id chip_id;
};
/* CAN FD mode nominal rate constants */
@@ -1070,38 +1079,70 @@ static void rcar_canfd_tx_done(struct net_device *ndev)
can_led_event(ndev, CAN_LED_EVENT_TX);
}
+static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
+{
+ struct rcar_canfd_channel *priv = gpriv->ch[ch];
+ struct net_device *ndev = priv->ndev;
+ u32 gerfl;
+
+ /* Handle global error interrupts */
+ gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
+ if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
+ rcar_canfd_global_error(ndev);
+}
+
+static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
+{
+ struct rcar_canfd_global *gpriv = dev_id;
+ u32 ch;
+
+ for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+ rcar_canfd_handle_global_err(gpriv, ch);
+
+ return IRQ_HANDLED;
+}
+
+static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
+{
+ struct rcar_canfd_channel *priv = gpriv->ch[ch];
+ u32 ridx = ch + RCANFD_RFFIFO_IDX;
+ u32 sts;
+
+ /* Handle Rx interrupts */
+ sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+ if (likely(sts & RCANFD_RFSTS_RFIF)) {
+ if (napi_schedule_prep(&priv->napi)) {
+ /* Disable Rx FIFO interrupts */
+ rcar_canfd_clear_bit(priv->base,
+ RCANFD_RFCC(ridx),
+ RCANFD_RFCC_RFIE);
+ __napi_schedule(&priv->napi);
+ }
+ }
+}
+
+static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
+{
+ struct rcar_canfd_global *gpriv = dev_id;
+ u32 ch;
+
+ for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+ rcar_canfd_handle_global_receive(gpriv, ch);
+
+ return IRQ_HANDLED;
+}
+
static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
{
struct rcar_canfd_global *gpriv = dev_id;
- struct net_device *ndev;
- struct rcar_canfd_channel *priv;
- u32 sts, gerfl;
- u32 ch, ridx;
+ u32 ch;
/* Global error interrupts still indicate a condition specific
* to a channel. RxFIFO interrupt is a global interrupt.
*/
for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
- priv = gpriv->ch[ch];
- ndev = priv->ndev;
- ridx = ch + RCANFD_RFFIFO_IDX;
-
- /* Global error interrupts */
- gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
- if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
- rcar_canfd_global_error(ndev);
-
- /* Handle Rx interrupts */
- sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
- if (likely(sts & RCANFD_RFSTS_RFIF)) {
- if (napi_schedule_prep(&priv->napi)) {
- /* Disable Rx FIFO interrupts */
- rcar_canfd_clear_bit(priv->base,
- RCANFD_RFCC(ridx),
- RCANFD_RFCC_RFIE);
- __napi_schedule(&priv->napi);
- }
- }
+ rcar_canfd_handle_global_err(gpriv, ch);
+ rcar_canfd_handle_global_receive(gpriv, ch);
}
return IRQ_HANDLED;
}
@@ -1139,38 +1180,73 @@ static void rcar_canfd_state_change(struct net_device *ndev,
}
}
-static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+ struct rcar_canfd_channel *priv = priv = gpriv->ch[ch];
+ struct net_device *ndev = priv->ndev;
+ u32 sts;
+
+ /* Handle Tx interrupts */
+ sts = rcar_canfd_read(priv->base,
+ RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+ if (likely(sts & RCANFD_CFSTS_CFTXIF))
+ rcar_canfd_tx_done(ndev);
+}
+
+static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
{
struct rcar_canfd_global *gpriv = dev_id;
- struct net_device *ndev;
- struct rcar_canfd_channel *priv;
- u32 sts, ch, cerfl;
+ u32 ch;
+
+ for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+ rcar_canfd_handle_channel_tx(gpriv, ch);
+
+ return IRQ_HANDLED;
+}
+
+static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
+{
+ struct rcar_canfd_channel *priv = gpriv->ch[ch];
+ struct net_device *ndev = priv->ndev;
u16 txerr, rxerr;
+ u32 sts, cerfl;
+
+ /* Handle channel error interrupts */
+ cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
+ sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
+ txerr = RCANFD_CSTS_TECCNT(sts);
+ rxerr = RCANFD_CSTS_RECCNT(sts);
+ if (unlikely(RCANFD_CERFL_ERR(cerfl)))
+ rcar_canfd_error(ndev, cerfl, txerr, rxerr);
+
+ /* Handle state change to lower states */
+ if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
+ priv->can.state != CAN_STATE_BUS_OFF))
+ rcar_canfd_state_change(ndev, txerr, rxerr);
+}
+
+static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
+{
+ struct rcar_canfd_global *gpriv = dev_id;
+ u32 ch;
+
+ for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+ rcar_canfd_handle_channel_err(gpriv, ch);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+ struct rcar_canfd_global *gpriv = dev_id;
+ u32 ch;
/* Common FIFO is a per channel resource */
for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
- priv = gpriv->ch[ch];
- ndev = priv->ndev;
-
- /* Channel error interrupts */
- cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
- sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
- txerr = RCANFD_CSTS_TECCNT(sts);
- rxerr = RCANFD_CSTS_RECCNT(sts);
- if (unlikely(RCANFD_CERFL_ERR(cerfl)))
- rcar_canfd_error(ndev, cerfl, txerr, rxerr);
-
- /* Handle state change to lower states */
- if (unlikely((priv->can.state != CAN_STATE_ERROR_ACTIVE) &&
- (priv->can.state != CAN_STATE_BUS_OFF)))
- rcar_canfd_state_change(ndev, txerr, rxerr);
-
- /* Handle Tx interrupts */
- sts = rcar_canfd_read(priv->base,
- RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
- if (likely(sts & RCANFD_CFSTS_CFTXIF))
- rcar_canfd_tx_done(ndev);
+ rcar_canfd_handle_channel_err(gpriv, ch);
+ rcar_canfd_handle_channel_tx(gpriv, ch);
}
+
return IRQ_HANDLED;
}
@@ -1577,6 +1653,53 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
priv->can.clock.freq = fcan_freq;
dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+ if (gpriv->chip_id == RENESAS_RZG2L) {
+ char *irq_name;
+ int err_irq;
+ int tx_irq;
+
+ err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
+ if (err_irq < 0) {
+ err = err_irq;
+ goto fail;
+ }
+
+ tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
+ if (tx_irq < 0) {
+ err = tx_irq;
+ goto fail;
+ }
+
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+ "canfd.ch%d_err", ch);
+ if (!irq_name) {
+ err = -ENOMEM;
+ goto fail;
+ }
+ err = devm_request_irq(&pdev->dev, err_irq,
+ rcar_canfd_channel_err_interrupt, 0,
+ irq_name, gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq CH Err(%d) failed, error %d\n",
+ err_irq, err);
+ goto fail;
+ }
+ irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+ "canfd.ch%d_trx", ch);
+ if (!irq_name) {
+ err = -ENOMEM;
+ goto fail;
+ }
+ err = devm_request_irq(&pdev->dev, tx_irq,
+ rcar_canfd_channel_tx_interrupt, 0,
+ irq_name, gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq Tx (%d) failed, error %d\n",
+ tx_irq, err);
+ goto fail;
+ }
+ }
+
if (gpriv->fdmode) {
priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
priv->can.data_bittiming_const =
@@ -1636,7 +1759,11 @@ static int rcar_canfd_probe(struct platform_device *pdev)
struct device_node *of_child;
unsigned long channels_mask = 0;
int err, ch_irq, g_irq;
+ int g_err_irq, g_recc_irq;
bool fdmode = true; /* CAN FD only mode - default */
+ enum rcanfd_chip_id chip_id;
+
+ chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
fdmode = false; /* Classical CAN only mode */
@@ -1649,16 +1776,30 @@ static int rcar_canfd_probe(struct platform_device *pdev)
if (of_child && of_device_is_available(of_child))
channels_mask |= BIT(1); /* Channel 1 */
- ch_irq = platform_get_irq(pdev, 0);
- if (ch_irq < 0) {
- err = ch_irq;
- goto fail_dev;
- }
+ if (chip_id == RENESAS_RCAR_GEN3) {
+ ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
+ if (ch_irq < 0) {
+ /* For backward compatibility get irq by index */
+ ch_irq = platform_get_irq(pdev, 0);
+ if (ch_irq < 0)
+ return ch_irq;
+ }
- g_irq = platform_get_irq(pdev, 1);
- if (g_irq < 0) {
- err = g_irq;
- goto fail_dev;
+ g_irq = platform_get_irq_byname_optional(pdev, "g_int");
+ if (g_irq < 0) {
+ /* For backward compatibility get irq by index */
+ g_irq = platform_get_irq(pdev, 1);
+ if (g_irq < 0)
+ return g_irq;
+ }
+ } else {
+ g_err_irq = platform_get_irq_byname(pdev, "g_err");
+ if (g_err_irq < 0)
+ return g_err_irq;
+
+ g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
+ if (g_recc_irq < 0)
+ return g_recc_irq;
}
/* Global controller context */
@@ -1670,6 +1811,19 @@ static int rcar_canfd_probe(struct platform_device *pdev)
gpriv->pdev = pdev;
gpriv->channels_mask = channels_mask;
gpriv->fdmode = fdmode;
+ gpriv->chip_id = chip_id;
+
+ if (gpriv->chip_id == RENESAS_RZG2L) {
+ gpriv->rstc1 = devm_reset_control_get_exclusive(&pdev->dev, "rstp_n");
+ if (IS_ERR(gpriv->rstc1))
+ return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc1),
+ "failed to get rstp_n\n");
+
+ gpriv->rstc2 = devm_reset_control_get_exclusive(&pdev->dev, "rstc_n");
+ if (IS_ERR(gpriv->rstc2))
+ return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc2),
+ "failed to get rstc_n\n");
+ }
/* Peripheral clock */
gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
@@ -1699,7 +1853,7 @@ static int rcar_canfd_probe(struct platform_device *pdev)
}
fcan_freq = clk_get_rate(gpriv->can_clk);
- if (gpriv->fcan == RCANFD_CANFDCLK)
+ if (gpriv->fcan == RCANFD_CANFDCLK && gpriv->chip_id == RENESAS_RCAR_GEN3)
/* CANFD clock is further divided by (1/2) within the IP */
fcan_freq /= 2;
@@ -1711,20 +1865,51 @@ static int rcar_canfd_probe(struct platform_device *pdev)
gpriv->base = addr;
/* Request IRQ that's common for both channels */
- err = devm_request_irq(&pdev->dev, ch_irq,
- rcar_canfd_channel_interrupt, 0,
- "canfd.chn", gpriv);
- if (err) {
- dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
- ch_irq, err);
- goto fail_dev;
+ if (gpriv->chip_id == RENESAS_RCAR_GEN3) {
+ err = devm_request_irq(&pdev->dev, ch_irq,
+ rcar_canfd_channel_interrupt, 0,
+ "canfd.ch_int", gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+ ch_irq, err);
+ goto fail_dev;
+ }
+
+ err = devm_request_irq(&pdev->dev, g_irq,
+ rcar_canfd_global_interrupt, 0,
+ "canfd.g_int", gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+ g_irq, err);
+ goto fail_dev;
+ }
+ } else {
+ err = devm_request_irq(&pdev->dev, g_recc_irq,
+ rcar_canfd_global_receive_fifo_interrupt, 0,
+ "canfd.g_recc", gpriv);
+
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+ g_recc_irq, err);
+ goto fail_dev;
+ }
+
+ err = devm_request_irq(&pdev->dev, g_err_irq,
+ rcar_canfd_global_err_interrupt, 0,
+ "canfd.g_err", gpriv);
+ if (err) {
+ dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+ g_err_irq, err);
+ goto fail_dev;
+ }
}
- err = devm_request_irq(&pdev->dev, g_irq,
- rcar_canfd_global_interrupt, 0,
- "canfd.gbl", gpriv);
+
+ err = reset_control_reset(gpriv->rstc1);
+ if (err)
+ goto fail_dev;
+ err = reset_control_reset(gpriv->rstc2);
if (err) {
- dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
- g_irq, err);
+ reset_control_assert(gpriv->rstc1);
goto fail_dev;
}
@@ -1733,7 +1918,7 @@ static int rcar_canfd_probe(struct platform_device *pdev)
if (err) {
dev_err(&pdev->dev,
"failed to enable peripheral clock, error %d\n", err);
- goto fail_dev;
+ goto fail_reset;
}
err = rcar_canfd_reset_controller(gpriv);
@@ -1790,6 +1975,9 @@ static int rcar_canfd_probe(struct platform_device *pdev)
rcar_canfd_disable_global_interrupts(gpriv);
fail_clk:
clk_disable_unprepare(gpriv->clkp);
+fail_reset:
+ reset_control_assert(gpriv->rstc1);
+ reset_control_assert(gpriv->rstc2);
fail_dev:
return err;
}
@@ -1810,6 +1998,9 @@ static int rcar_canfd_remove(struct platform_device *pdev)
/* Enter global sleep mode */
rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
clk_disable_unprepare(gpriv->clkp);
+ reset_control_assert(gpriv->rstc1);
+ reset_control_assert(gpriv->rstc2);
+
return 0;
}
@@ -1827,7 +2018,8 @@ static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
rcar_canfd_resume);
static const struct of_device_id rcar_canfd_of_table[] = {
- { .compatible = "renesas,rcar-gen3-canfd" },
+ { .compatible = "renesas,rcar-gen3-canfd", .data = (void *)RENESAS_RCAR_GEN3 },
+ { .compatible = "renesas,rzg2l-canfd", .data = (void *)RENESAS_RZG2L },
{ }
};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family
2021-12-22 13:49 ` [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family Lad Prabhakar
@ 2021-12-22 23:13 ` Pavel Machek
2021-12-22 23:37 ` Prabhakar Mahadev Lad
0 siblings, 1 reply; 27+ messages in thread
From: Pavel Machek @ 2021-12-22 23:13 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 4233 bytes --]
Hi!
> commit 76e9353a80e9e9ff65b362a6dd8545d84427ec30 upstream.
>
> CANFD block on RZ/G2L SoC is almost identical to one found on
> R-Car Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel
> are split into different sources and the IP doesn't divide (1/2)
> CANFD clock within the IP.
>
> This patch adds compatible string for RZ/G2L family and splits
> the irq handlers to accommodate both RZ/G2L and R-Car Gen3 SoC's.
> +++ b/drivers/net/can/rcar/rcar_canfd.c
> +
> +static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
> +{
> + struct rcar_canfd_global *gpriv = dev_id;
> + u32 ch;
> +
> + for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
> + rcar_canfd_handle_global_err(gpriv, ch);
> +
> + return IRQ_HANDLED;
> +}
> +
You are returning IRQ_HANDLED even when you do no handling. That
probably will not do harm as long as interrupts are not shared. Is
that guaranteed to be true?
> @@ -1577,6 +1653,53 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
> priv->can.clock.freq = fcan_freq;
> dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
>
> + if (gpriv->chip_id == RENESAS_RZG2L) {
> + char *irq_name;
> + int err_irq;
> + int tx_irq;
> +
> + err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
> + if (err_irq < 0) {
> + err = err_irq;
> + goto fail;
> + }
This leaks ndev; it should free_candev(ndev); before returning, AFAICT.
> @@ -1670,6 +1811,19 @@ static int rcar_canfd_probe(struct platform_device *pdev)
> gpriv->pdev = pdev;
> gpriv->channels_mask = channels_mask;
> gpriv->fdmode = fdmode;
> + gpriv->chip_id = chip_id;
> +
> + if (gpriv->chip_id == RENESAS_RZG2L) {
> + gpriv->rstc1 = devm_reset_control_get_exclusive(&pdev->dev, "rstp_n");
> + if (IS_ERR(gpriv->rstc1))
> + return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc1),
> + "failed to get rstp_n\n");
> +
> + gpriv->rstc2 = devm_reset_control_get_exclusive(&pdev->dev, "rstc_n");
> + if (IS_ERR(gpriv->rstc2))
> + return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc2),
> + "failed to get rstc_n\n");
> + }
>
> /* Peripheral clock */
> gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
The code is correct but it mixes direct returns with "goto
fail_dev", which is just alias for return. I'd prefer just doing
returns directly, but it really should not mix direct returns with
goto return.
> - err = devm_request_irq(&pdev->dev, g_irq,
> - rcar_canfd_global_interrupt, 0,
> - "canfd.gbl", gpriv);
Strange. New code variant no longer allocates canfd.gbl?
> + err = reset_control_reset(gpriv->rstc1);
> + if (err)
> + goto fail_dev;
> + err = reset_control_reset(gpriv->rstc2);
> if (err) {
> - dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
> - g_irq, err);
> + reset_control_assert(gpriv->rstc1);
> goto fail_dev;
> }
I'd introduce new label here, so that you don't need to do
reset_control_assert(gpriv->rstc1); at two different places... like
below...
Best regards,
Pavel
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index 52629c6c19702..ce9b3a0032bf8 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -1908,10 +1908,8 @@ static int rcar_canfd_probe(struct platform_device *pdev)
if (err)
goto fail_dev;
err = reset_control_reset(gpriv->rstc2);
- if (err) {
- reset_control_assert(gpriv->rstc1);
- goto fail_dev;
- }
+ if (err)
+ goto fail_reset1;
/* Enable peripheral clock for register access */
err = clk_prepare_enable(gpriv->clkp);
@@ -1976,8 +1974,9 @@ static int rcar_canfd_probe(struct platform_device *pdev)
fail_clk:
clk_disable_unprepare(gpriv->clkp);
fail_reset:
- reset_control_assert(gpriv->rstc1);
reset_control_assert(gpriv->rstc2);
+fail_reset1:
+ reset_control_assert(gpriv->rstc1);
fail_dev:
return err;
}
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply related [flat|nested] 27+ messages in thread* RE: [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family
2021-12-22 23:13 ` Pavel Machek
@ 2021-12-22 23:37 ` Prabhakar Mahadev Lad
2021-12-23 18:43 ` Pavel Machek
[not found] ` <16C376847BE1186B.4760@lists.cip-project.org>
0 siblings, 2 replies; 27+ messages in thread
From: Prabhakar Mahadev Lad @ 2021-12-22 23:37 UTC (permalink / raw)
To: Pavel Machek; +Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu, Biju Das
Hi Pavel,
Thank you for the review.
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 22 December 2021 23:14
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family
>
> Hi!
>
> > commit 76e9353a80e9e9ff65b362a6dd8545d84427ec30 upstream.
> >
> > CANFD block on RZ/G2L SoC is almost identical to one found on R-Car
> > Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel are split
> > into different sources and the IP doesn't divide (1/2) CANFD clock
> > within the IP.
> >
> > This patch adds compatible string for RZ/G2L family and splits the irq
> > handlers to accommodate both RZ/G2L and R-Car Gen3 SoC's.
>
>
> > +++ b/drivers/net/can/rcar/rcar_canfd.c
> > +
> > +static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void
> > +*dev_id) {
> > + struct rcar_canfd_global *gpriv = dev_id;
> > + u32 ch;
> > +
> > + for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
> > + rcar_canfd_handle_global_err(gpriv, ch);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
>
> You are returning IRQ_HANDLED even when you do no handling. That probably will not do harm as long as
> interrupts are not shared. Is that guaranteed to be true?
>
As of the current users of this driver interrupts are not shared.
> > @@ -1577,6 +1653,53 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
> > priv->can.clock.freq = fcan_freq;
> > dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
> >
> > + if (gpriv->chip_id == RENESAS_RZG2L) {
> > + char *irq_name;
> > + int err_irq;
> > + int tx_irq;
> > +
> > + err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
> > + if (err_irq < 0) {
> > + err = err_irq;
> > + goto fail;
> > + }
>
> This leaks ndev; it should free_candev(ndev); before returning, AFAICT.
>
Agreed, this needs a fix.
> > @@ -1670,6 +1811,19 @@ static int rcar_canfd_probe(struct platform_device *pdev)
> > gpriv->pdev = pdev;
> > gpriv->channels_mask = channels_mask;
> > gpriv->fdmode = fdmode;
> > + gpriv->chip_id = chip_id;
> > +
> > + if (gpriv->chip_id == RENESAS_RZG2L) {
> > + gpriv->rstc1 = devm_reset_control_get_exclusive(&pdev->dev, "rstp_n");
> > + if (IS_ERR(gpriv->rstc1))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc1),
> > + "failed to get rstp_n\n");
> > +
> > + gpriv->rstc2 = devm_reset_control_get_exclusive(&pdev->dev, "rstc_n");
> > + if (IS_ERR(gpriv->rstc2))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc2),
> > + "failed to get rstc_n\n");
> > + }
> >
> > /* Peripheral clock */
> > gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
>
> The code is correct but it mixes direct returns with "goto fail_dev", which is just alias for return.
> I'd prefer just doing returns directly, but it really should not mix direct returns with goto return.
>
Agreed.
> > - err = devm_request_irq(&pdev->dev, g_irq,
> > - rcar_canfd_global_interrupt, 0,
> > - "canfd.gbl", gpriv);
>
> Strange. New code variant no longer allocates canfd.gbl?
>
It does, its just that its renamed to "canfd.g_int".
> > + err = reset_control_reset(gpriv->rstc1);
> > + if (err)
> > + goto fail_dev;
> > + err = reset_control_reset(gpriv->rstc2);
> > if (err) {
> > - dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
> > - g_irq, err);
> > + reset_control_assert(gpriv->rstc1);
> > goto fail_dev;
> > }
>
> I'd introduce new label here, so that you don't need to do reset_control_assert(gpriv->rstc1); at two
> different places... like below...
>
Thanks for the suggestion. Let me include this while I fix the leak.
Cheers,
Prabhakar
> Best regards,
>
> Pavel
>
> diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
> index 52629c6c19702..ce9b3a0032bf8 100644
> --- a/drivers/net/can/rcar/rcar_canfd.c
> +++ b/drivers/net/can/rcar/rcar_canfd.c
> @@ -1908,10 +1908,8 @@ static int rcar_canfd_probe(struct platform_device *pdev)
> if (err)
> goto fail_dev;
> err = reset_control_reset(gpriv->rstc2);
> - if (err) {
> - reset_control_assert(gpriv->rstc1);
> - goto fail_dev;
> - }
> + if (err)
> + goto fail_reset1;
>
> /* Enable peripheral clock for register access */
> err = clk_prepare_enable(gpriv->clkp); @@ -1976,8 +1974,9 @@ static int rcar_canfd_probe(struct
> platform_device *pdev)
> fail_clk:
> clk_disable_unprepare(gpriv->clkp);
> fail_reset:
> - reset_control_assert(gpriv->rstc1);
> reset_control_assert(gpriv->rstc2);
> +fail_reset1:
> + reset_control_assert(gpriv->rstc1);
> fail_dev:
> return err;
> }
>
>
>
>
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family
2021-12-22 23:37 ` Prabhakar Mahadev Lad
@ 2021-12-23 18:43 ` Pavel Machek
[not found] ` <16C376847BE1186B.4760@lists.cip-project.org>
1 sibling, 0 replies; 27+ messages in thread
From: Pavel Machek @ 2021-12-23 18:43 UTC (permalink / raw)
To: Prabhakar Mahadev Lad
Cc: Pavel Machek, cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu,
Biju Das
[-- Attachment #1: Type: text/plain, Size: 793 bytes --]
Hi!
> > > + if (gpriv->chip_id == RENESAS_RZG2L) {
> > > + char *irq_name;
> > > + int err_irq;
> > > + int tx_irq;
> > > +
> > > + err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
> > > + if (err_irq < 0) {
> > > + err = err_irq;
> > > + goto fail;
> > > + }
> >
> > This leaks ndev; it should free_candev(ndev); before returning, AFAICT.
> >
> Agreed, this needs a fix.
Yes. OTOH this is just a problem in error paths. Other patches look
good, so this should probably be fixed in the mainline.
I can apply the series if there are no other comments.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread[parent not found: <16C376847BE1186B.4760@lists.cip-project.org>]
* Re: [cip-dev] [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family
[not found] ` <16C376847BE1186B.4760@lists.cip-project.org>
@ 2021-12-26 16:08 ` Pavel Machek
2021-12-27 13:45 ` Prabhakar Mahadev Lad
0 siblings, 1 reply; 27+ messages in thread
From: Pavel Machek @ 2021-12-26 16:08 UTC (permalink / raw)
To: cip-dev; +Cc: Prabhakar Mahadev Lad, Pavel Machek, Nobuhiro Iwamatsu, Biju Das
[-- Attachment #1: Type: text/plain, Size: 447 bytes --]
Hi!
> > Agreed, this needs a fix.
>
> Yes. OTOH this is just a problem in error paths. Other patches look
> good, so this should probably be fixed in the mainline.
>
> I can apply the series if there are no other comments.
I applied/pushed the series.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [cip-dev] [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family
2021-12-26 16:08 ` [cip-dev] " Pavel Machek
@ 2021-12-27 13:45 ` Prabhakar Mahadev Lad
0 siblings, 0 replies; 27+ messages in thread
From: Prabhakar Mahadev Lad @ 2021-12-27 13:45 UTC (permalink / raw)
To: Pavel Machek, cip-dev@lists.cip-project.org; +Cc: Nobuhiro Iwamatsu, Biju Das
Hi Pavel,
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 26 December 2021 16:08
> To: cip-dev@lists.cip-project.org
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; Pavel Machek <pavel@denx.de>;
> Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [cip-dev] [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family
>
> Hi!
>
> > > Agreed, this needs a fix.
> >
> > Yes. OTOH this is just a problem in error paths. Other patches look
> > good, so this should probably be fixed in the mainline.
> >
> > I can apply the series if there are no other comments.
>
> I applied/pushed the series.
>
Thank you, I will backport the fix as soon as its available in -rc.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 5.10.y-cip 16/21] can: rcar_canfd: rcar_canfd_handle_channel_tx(): fix redundant assignment
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (14 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 15/21] can: rcar_canfd: Add support for RZ/G2L family Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 17/21] dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock Lad Prabhakar
` (4 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 1d38ec4974143827631d44a6a2a4c069fc4c05bd upstream.
Fix redundant assignment of 'priv' to itself in
rcar_canfd_handle_channel_tx().
Fixes: 76e9353a80e9 ("can: rcar_canfd: Add support for RZ/G2L family")
Link: https://lore.kernel.org/r/20210820161449.18169-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/net/can/rcar/rcar_canfd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index 0b0ceae0d844..52629c6c1970 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -1182,7 +1182,7 @@ static void rcar_canfd_state_change(struct net_device *ndev,
static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
{
- struct rcar_canfd_channel *priv = priv = gpriv->ch[ch];
+ struct rcar_canfd_channel *priv = gpriv->ch[ch];
struct net_device *ndev = priv->ndev;
u32 sts;
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 17/21] dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (15 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 16/21] can: rcar_canfd: rcar_canfd_handle_channel_tx(): fix redundant assignment Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 18/21] clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2 Lad Prabhakar
` (3 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 0b256c403d4082bafc681143913442288010277c upstream.
Add P0_DIV2 core clock required for CANFD module. CANFD core clock is
sourced from P0_DIV2 referenced from HW manual Rev.0.50.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719143811.2135-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
include/dt-bindings/clock/r9a07g044-cpg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
index 0728ad07ff7a..0bb17ff1a01a 100644
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -30,6 +30,7 @@
#define R9A07G044_CLK_P2 19
#define R9A07G044_CLK_AT 20
#define R9A07G044_OSCCLK 21
+#define R9A07G044_CLK_P0_DIV2 22
/* R9A07G044 Module Clocks */
#define R9A07G044_CA55_SCLK 0
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 18/21] clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (16 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 17/21] dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 19/21] clk: renesas: r9a07g044: Add clock and reset entries for CANFD Lad Prabhakar
` (2 subsequent siblings)
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit d28b1e03dc8d1070538ca3ea3f4e6732109ddf42 upstream.
Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
to R9A07G044_CLK_P0_DIV2.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719143811.2135-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 016a69f80a05..fba754858f13 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -16,7 +16,7 @@
enum clk_ids {
/* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
+ LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
/* External Input Clocks */
CLK_EXTAL,
@@ -77,6 +77,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 19/21] clk: renesas: r9a07g044: Add clock and reset entries for CANFD
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (17 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 18/21] clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2 Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 20/21] arm64: dts: renesas: r9a07g044: Add CANFD node Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 21/21] arm64: defconfig: Enable RZ/G2L USBPHY control driver Lad Prabhakar
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 3b5c734592ade51fed3982bc840a830e066e668e upstream.
Add clock and reset entries for CANFD in CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210715182123.23372-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index fba754858f13..0c45cad4ee65 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -125,6 +125,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
0x584, 4),
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
0x588, 0),
+ DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
+ 0x594, 0),
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
0x598, 0),
};
@@ -149,6 +151,8 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
+ DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
+ DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 20/21] arm64: dts: renesas: r9a07g044: Add CANFD node
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (18 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 19/21] clk: renesas: r9a07g044: Add clock and reset entries for CANFD Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
2021-12-22 13:49 ` [PATCH 5.10.y-cip 21/21] arm64: defconfig: Enable RZ/G2L USBPHY control driver Lad Prabhakar
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 9ea0c7b3c200a54e42a4b5171970791e70dd4f53 upstream.
Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210727133022.634-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 5818adc1ede9..6eefba96f5c7 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -13,6 +13,13 @@
#address-cells = <2>;
#size-cells = <2>;
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
compatible = "fixed-clock";
@@ -89,6 +96,40 @@
status = "disabled";
};
+ canfd: can@10050000 {
+ compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
+ reg = <0 0x10050000 0 0x8000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g_err", "g_recc",
+ "ch0_err", "ch0_rec", "ch0_trx",
+ "ch1_err", "ch1_rec", "ch1_trx";
+ clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
+ <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
+ assigned-clock-rates = <50000000>;
+ resets = <&cpg R9A07G044_CANFD_RSTP_N>,
+ <&cpg R9A07G044_CANFD_RSTC_N>;
+ reset-names = "rstp_n", "rstc_n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+ channel1 {
+ status = "disabled";
+ };
+ };
+
i2c0: i2c@10058000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5.10.y-cip 21/21] arm64: defconfig: Enable RZ/G2L USBPHY control driver
2021-12-22 13:49 [PATCH 5.10.y-cip 00/21] RZ/G2L: Add support for USB/CANFD Lad Prabhakar
` (19 preceding siblings ...)
2021-12-22 13:49 ` [PATCH 5.10.y-cip 20/21] arm64: dts: renesas: r9a07g044: Add CANFD node Lad Prabhakar
@ 2021-12-22 13:49 ` Lad Prabhakar
20 siblings, 0 replies; 27+ messages in thread
From: Lad Prabhakar @ 2021-12-22 13:49 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit ba73a2ab051812597f4f55fe4046587f48b7a916 upstream.
RZ/G2L SoC supports USBPHY control,so enable it in ARM64 defconfig.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210812151808.7916-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2604bcd75baa..afc696d94c89 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -994,6 +994,7 @@ CONFIG_QCOM_PDC=y
CONFIG_RESET_IMX7=y
CONFIG_RESET_QCOM_AOSS=y
CONFIG_RESET_QCOM_PDC=m
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_RESET_TI_SCI=y
CONFIG_PHY_XGENE=y
CONFIG_PHY_SUN4I_USB=y
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread