* [PATCH 5.10.y-cip 01/31] ASoC: dt-bindings: Document RZ/G2L bindings
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 02/31] ASoC: dt-bindings: sound: renesas,rz-ssi: Document DMA support Lad Prabhakar
` (29 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 2b761f476f3a6e0a212c8c88e7855f66edb177e0 upstream.
Document RZ/G2L ASoC serial sound interface bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210719134040.7964-2-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/sound/renesas,rz-ssi.yaml | 85 +++++++++++++++++++
1 file changed, 85 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
diff --git a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
new file mode 100644
index 000000000000..891f381ee5b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L ASoC Sound Serial Interface (SSIF-2)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-ssi # RZ/G2{L,LC}
+ - const: renesas,rz-ssi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 4
+
+ interrupt-names:
+ items:
+ - const: int_req
+ - const: dma_rx
+ - const: dma_tx
+ - const: dma_rt
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: ssi
+ - const: ssi_sfr
+ - const: audio_clk1
+ - const: audio_clk2
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#sound-dai-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - '#sound-dai-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ ssi0: ssi@10049c00 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0x10049c00 0x400>;
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
+ <&audio_clk1>,
+ <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
+ #sound-dai-cells = <0>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 02/31] ASoC: dt-bindings: sound: renesas,rz-ssi: Document DMA support
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 01/31] ASoC: dt-bindings: Document RZ/G2L bindings Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 03/31] ASoC: sh: Add RZ/G2L SSIF-2 driver Lad Prabhakar
` (28 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 5df6dfbb6de815ba3a75c788a916865212fd5221 upstream.
Document DMA support in binding document.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210719134040.7964-7-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/sound/renesas,rz-ssi.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
index 891f381ee5b8..471937cb8d05 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
@@ -45,6 +45,18 @@ properties:
resets:
maxItems: 1
+ dmas:
+ minItems: 1
+ maxItems: 2
+
+ dma-names:
+ oneOf:
+ - items:
+ - const: tx
+ - const: rx
+ - items:
+ - const: rt
+
'#sound-dai-cells':
const: 0
@@ -81,5 +93,8 @@ examples:
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
+ dmas = <&dmac 0x255>,
+ <&dmac 0x256>;
+ dma-names = "tx", "rx";
#sound-dai-cells = <0>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 03/31] ASoC: sh: Add RZ/G2L SSIF-2 driver
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 01/31] ASoC: dt-bindings: Document RZ/G2L bindings Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 02/31] ASoC: dt-bindings: sound: renesas,rz-ssi: Document DMA support Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-30 11:15 ` Pavel Machek
2021-12-29 10:15 ` [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel configuration parameter Lad Prabhakar
` (27 subsequent siblings)
30 siblings, 1 reply; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 03e786bd43410fa93e5d2459f7a43e90ff0ae801 upstream.
Add serial sound interface(SSIF-2) driver support for
RZ/G2L SoC.
Based on the work done by Chris Brandt for RZ/A SSI driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210813091156.10700-2-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
sound/soc/sh/Kconfig | 6 +
sound/soc/sh/Makefile | 4 +
sound/soc/sh/rz-ssi.c | 871 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 881 insertions(+)
create mode 100644 sound/soc/sh/rz-ssi.c
diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
index ef8a29b9f641..f19bd15c0900 100644
--- a/sound/soc/sh/Kconfig
+++ b/sound/soc/sh/Kconfig
@@ -44,6 +44,12 @@ config SND_SOC_RCAR
help
This option enables R-Car SRU/SCU/SSIU/SSI sound support
+config SND_SOC_RZ
+ tristate "RZ/G2L series SSIF-2 support"
+ depends on ARCH_R9A07G044 || COMPILE_TEST
+ help
+ This option enables RZ/G2L SSIF-2 sound support.
+
##
## Boards
##
diff --git a/sound/soc/sh/Makefile b/sound/soc/sh/Makefile
index 51bd7c81671c..f6fd79948f6a 100644
--- a/sound/soc/sh/Makefile
+++ b/sound/soc/sh/Makefile
@@ -22,3 +22,7 @@ snd-soc-migor-objs := migor.o
obj-$(CONFIG_SND_SH7760_AC97) += snd-soc-sh7760-ac97.o
obj-$(CONFIG_SND_SIU_MIGOR) += snd-soc-migor.o
+
+# RZ/G2L
+snd-soc-rz-ssi-objs := rz-ssi.o
+obj-$(CONFIG_SND_SOC_RZ) += snd-soc-rz-ssi.o
diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
new file mode 100644
index 000000000000..615fa81f061e
--- /dev/null
+++ b/sound/soc/sh/rz-ssi.c
@@ -0,0 +1,871 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver
+//
+// Copyright (C) 2021 Renesas Electronics Corp.
+// Copyright (C) 2019 Chris Brandt.
+//
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <sound/soc.h>
+
+/* REGISTER OFFSET */
+#define SSICR 0x000
+#define SSISR 0x004
+#define SSIFCR 0x010
+#define SSIFSR 0x014
+#define SSIFTDR 0x018
+#define SSIFRDR 0x01c
+#define SSIOFR 0x020
+#define SSISCR 0x024
+
+/* SSI REGISTER BITS */
+#define SSICR_DWL(x) (((x) & 0x7) << 19)
+#define SSICR_SWL(x) (((x) & 0x7) << 16)
+#define SSICR_MST BIT(14)
+#define SSICR_CKDV(x) (((x) & 0xf) << 4)
+
+#define SSICR_CKS BIT(30)
+#define SSICR_TUIEN BIT(29)
+#define SSICR_TOIEN BIT(28)
+#define SSICR_RUIEN BIT(27)
+#define SSICR_ROIEN BIT(26)
+#define SSICR_MST BIT(14)
+#define SSICR_BCKP BIT(13)
+#define SSICR_LRCKP BIT(12)
+#define SSICR_CKDV(x) (((x) & 0xf) << 4)
+#define SSICR_TEN BIT(1)
+#define SSICR_REN BIT(0)
+
+#define SSISR_TUIRQ BIT(29)
+#define SSISR_TOIRQ BIT(28)
+#define SSISR_RUIRQ BIT(27)
+#define SSISR_ROIRQ BIT(26)
+#define SSISR_IIRQ BIT(25)
+
+#define SSIFCR_AUCKE BIT(31)
+#define SSIFCR_SSIRST BIT(16)
+#define SSIFCR_TIE BIT(3)
+#define SSIFCR_RIE BIT(2)
+#define SSIFCR_TFRST BIT(1)
+#define SSIFCR_RFRST BIT(0)
+
+#define SSIFSR_TDC_MASK 0x3f
+#define SSIFSR_TDC_SHIFT 24
+#define SSIFSR_RDC_MASK 0x3f
+#define SSIFSR_RDC_SHIFT 8
+
+#define SSIFSR_TDC(x) (((x) & 0x1f) << 24)
+#define SSIFSR_TDE BIT(16)
+#define SSIFSR_RDC(x) (((x) & 0x1f) << 8)
+#define SSIFSR_RDF BIT(0)
+
+#define SSIOFR_LRCONT BIT(8)
+
+#define SSISCR_TDES(x) (((x) & 0x1f) << 8)
+#define SSISCR_RDFS(x) (((x) & 0x1f) << 0)
+
+/* Pre allocated buffers sizes */
+#define PREALLOC_BUFFER (SZ_32K)
+#define PREALLOC_BUFFER_MAX (SZ_32K)
+
+#define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */
+#define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE
+#define SSI_CHAN_MIN 2
+#define SSI_CHAN_MAX 2
+#define SSI_FIFO_DEPTH 32
+
+struct rz_ssi_priv;
+
+struct rz_ssi_stream {
+ struct rz_ssi_priv *priv;
+ struct snd_pcm_substream *substream;
+ int fifo_sample_size; /* sample capacity of SSI FIFO */
+ int period_counter; /* for keeping track of periods transferred */
+ int sample_width;
+ int buffer_pos; /* current frame position in the buffer */
+ int running; /* 0=stopped, 1=running */
+
+ int uerr_num;
+ int oerr_num;
+
+ int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
+};
+
+struct rz_ssi_priv {
+ void __iomem *base;
+ struct platform_device *pdev;
+ struct reset_control *rstc;
+ struct device *dev;
+ struct clk *sfr_clk;
+ struct clk *clk;
+
+ int irq_int;
+ int irq_tx;
+ int irq_rx;
+
+ spinlock_t lock;
+
+ /*
+ * The SSI supports full-duplex transmission and reception.
+ * However, if an error occurs, channel reset (both transmission
+ * and reception reset) is required.
+ * So it is better to use as half-duplex (playing and recording
+ * should be done on separate channels).
+ */
+ struct rz_ssi_stream playback;
+ struct rz_ssi_stream capture;
+
+ /* clock */
+ unsigned long audio_mck;
+ unsigned long audio_clk_1;
+ unsigned long audio_clk_2;
+
+ bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */
+ bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */
+};
+
+static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data)
+{
+ writel(data, (priv->base + reg));
+}
+
+static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg)
+{
+ return readl(priv->base + reg);
+}
+
+static void rz_ssi_reg_mask_setl(struct rz_ssi_priv __iomem *priv, uint reg,
+ u32 bclr, u32 bset)
+{
+ u32 val;
+
+ val = readl(priv->base + reg);
+ val = (val & ~bclr) | bset;
+ writel(val, (priv->base + reg));
+}
+
+static inline struct snd_soc_dai *
+rz_ssi_get_dai(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+
+ return asoc_rtd_to_cpu(rtd, 0);
+}
+
+static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi,
+ struct snd_pcm_substream *substream)
+{
+ return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+}
+
+static inline struct rz_ssi_stream *
+rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
+{
+ struct rz_ssi_stream *stream = &ssi->playback;
+
+ if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
+ stream = &ssi->capture;
+
+ return stream;
+}
+
+static int rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
+ struct rz_ssi_stream *strm)
+{
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&ssi->lock, flags);
+ ret = !!(strm->substream && strm->substream->runtime);
+ spin_unlock_irqrestore(&ssi->lock, flags);
+
+ return ret;
+}
+
+static int rz_ssi_stream_init(struct rz_ssi_priv *ssi,
+ struct rz_ssi_stream *strm,
+ struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+
+ strm->substream = substream;
+ strm->sample_width = samples_to_bytes(runtime, 1);
+ strm->period_counter = 0;
+ strm->buffer_pos = 0;
+
+ strm->oerr_num = 0;
+ strm->uerr_num = 0;
+ strm->running = 0;
+
+ /* fifo init */
+ strm->fifo_sample_size = SSI_FIFO_DEPTH;
+
+ return 0;
+}
+
+static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi,
+ struct rz_ssi_stream *strm)
+{
+ struct snd_soc_dai *dai = rz_ssi_get_dai(strm->substream);
+ unsigned long flags;
+
+ spin_lock_irqsave(&ssi->lock, flags);
+ strm->substream = NULL;
+ spin_unlock_irqrestore(&ssi->lock, flags);
+
+ if (strm->oerr_num > 0)
+ dev_info(dai->dev, "overrun = %d\n", strm->oerr_num);
+
+ if (strm->uerr_num > 0)
+ dev_info(dai->dev, "underrun = %d\n", strm->uerr_num);
+}
+
+static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
+ unsigned int channels)
+{
+ static s8 ckdv[16] = { 1, 2, 4, 8, 16, 32, 64, 128,
+ 6, 12, 24, 48, 96, -1, -1, -1 };
+ unsigned int channel_bits = 32; /* System Word Length */
+ unsigned long bclk_rate = rate * channels * channel_bits;
+ unsigned int div;
+ unsigned int i;
+ u32 ssicr = 0;
+ u32 clk_ckdv;
+
+ /* Clear AUCKE so we can set MST */
+ rz_ssi_reg_writel(ssi, SSIFCR, 0);
+
+ /* Continue to output LRCK pin even when idle */
+ rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT);
+ if (ssi->audio_clk_1 && ssi->audio_clk_2) {
+ if (ssi->audio_clk_1 % bclk_rate)
+ ssi->audio_mck = ssi->audio_clk_2;
+ else
+ ssi->audio_mck = ssi->audio_clk_1;
+ }
+
+ /* Clock setting */
+ ssicr |= SSICR_MST;
+ if (ssi->audio_mck == ssi->audio_clk_1)
+ ssicr |= SSICR_CKS;
+ if (ssi->bckp_rise)
+ ssicr |= SSICR_BCKP;
+ if (ssi->lrckp_fsync_fall)
+ ssicr |= SSICR_LRCKP;
+
+ /* Determine the clock divider */
+ clk_ckdv = 0;
+ div = ssi->audio_mck / bclk_rate;
+ /* try to find an match */
+ for (i = 0; i < ARRAY_SIZE(ckdv); i++) {
+ if (ckdv[i] == div) {
+ clk_ckdv = i;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(ckdv)) {
+ dev_err(ssi->dev, "Rate not divisible by audio clock source\n");
+ return -EINVAL;
+ }
+
+ /*
+ * DWL: Data Word Length = 16 bits
+ * SWL: System Word Length = 32 bits
+ */
+ ssicr |= SSICR_CKDV(clk_ckdv);
+ ssicr |= SSICR_DWL(1) | SSICR_SWL(3);
+ rz_ssi_reg_writel(ssi, SSICR, ssicr);
+ rz_ssi_reg_writel(ssi, SSIFCR,
+ (SSIFCR_AUCKE | SSIFCR_TFRST | SSIFCR_RFRST));
+
+ return 0;
+}
+
+static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
+{
+ bool is_play = rz_ssi_stream_is_play(ssi, strm->substream);
+ u32 ssicr, ssifcr;
+
+ ssicr = rz_ssi_reg_readl(ssi, SSICR);
+ ssifcr = rz_ssi_reg_readl(ssi, SSIFCR) & ~0xF;
+
+ /* FIFO interrupt thresholds */
+ rz_ssi_reg_writel(ssi, SSISCR,
+ SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
+ SSISCR_RDFS(0));
+
+ /* enable IRQ */
+ if (is_play) {
+ ssicr |= SSICR_TUIEN | SSICR_TOIEN;
+ ssifcr |= SSIFCR_TIE | SSIFCR_RFRST;
+ } else {
+ ssicr |= SSICR_RUIEN | SSICR_ROIEN;
+ ssifcr |= SSIFCR_RIE | SSIFCR_TFRST;
+ }
+
+ rz_ssi_reg_writel(ssi, SSICR, ssicr);
+ rz_ssi_reg_writel(ssi, SSIFCR, ssifcr);
+
+ /* Clear all error flags */
+ rz_ssi_reg_mask_setl(ssi, SSISR,
+ (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
+ SSISR_RUIRQ), 0);
+
+ strm->running = 1;
+ ssicr |= is_play ? SSICR_TEN : SSICR_REN;
+ rz_ssi_reg_writel(ssi, SSICR, ssicr);
+
+ return 0;
+}
+
+static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
+{
+ int timeout;
+
+ strm->running = 0;
+
+ /* Disable TX/RX */
+ rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
+
+ /* Disable irqs */
+ rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN |
+ SSICR_RUIEN | SSICR_ROIEN, 0);
+ rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0);
+
+ /* Clear all error flags */
+ rz_ssi_reg_mask_setl(ssi, SSISR,
+ (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
+ SSISR_RUIRQ), 0);
+
+ /* Wait for idle */
+ timeout = 100;
+ while (--timeout) {
+ if (rz_ssi_reg_readl(ssi, SSISR) | SSISR_IIRQ)
+ break;
+ udelay(1);
+ }
+
+ if (!timeout)
+ dev_info(ssi->dev, "timeout waiting for SSI idle\n");
+
+ /* Hold FIFOs in reset */
+ rz_ssi_reg_mask_setl(ssi, SSIFCR, 0,
+ SSIFCR_TFRST | SSIFCR_RFRST);
+
+ return 0;
+}
+
+static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames)
+{
+ struct snd_pcm_substream *substream = strm->substream;
+ struct snd_pcm_runtime *runtime;
+ int current_period;
+
+ if (!strm->running || !substream || !substream->runtime)
+ return;
+
+ runtime = substream->runtime;
+ strm->buffer_pos += frames;
+ WARN_ON(strm->buffer_pos > runtime->buffer_size);
+
+ /* ring buffer */
+ if (strm->buffer_pos == runtime->buffer_size)
+ strm->buffer_pos = 0;
+
+ current_period = strm->buffer_pos / runtime->period_size;
+ if (strm->period_counter != current_period) {
+ snd_pcm_period_elapsed(strm->substream);
+ strm->period_counter = current_period;
+ }
+}
+
+static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
+{
+ struct snd_pcm_substream *substream = strm->substream;
+ struct snd_pcm_runtime *runtime;
+ u16 *buf;
+ int fifo_samples;
+ int frames_left;
+ int samples = 0;
+ int i;
+
+ if (!rz_ssi_stream_is_valid(ssi, strm))
+ return -EINVAL;
+
+ runtime = substream->runtime;
+ /* frames left in this period */
+ frames_left = runtime->period_size - (strm->buffer_pos %
+ runtime->period_size);
+ if (frames_left == 0)
+ frames_left = runtime->period_size;
+
+ /* Samples in RX FIFO */
+ fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >>
+ SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK;
+
+ /* Only read full frames at a time */
+ while (frames_left && (fifo_samples >= runtime->channels)) {
+ samples += runtime->channels;
+ fifo_samples -= runtime->channels;
+ frames_left--;
+ }
+
+ /* not enough samples yet */
+ if (samples == 0)
+ return 0;
+
+ /* calculate new buffer index */
+ buf = (u16 *)(runtime->dma_area);
+ buf += strm->buffer_pos * runtime->channels;
+
+ /* Note, only supports 16-bit samples */
+ for (i = 0; i < samples; i++)
+ *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16);
+
+ rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
+ rz_ssi_pointer_update(strm, samples / runtime->channels);
+
+ /*
+ * If we finished this period, but there are more samples in
+ * the RX FIFO, call this function again
+ */
+ if (frames_left == 0 && fifo_samples >= runtime->channels)
+ rz_ssi_pio_recv(ssi, strm);
+
+ return 0;
+}
+
+static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
+{
+ struct snd_pcm_substream *substream = strm->substream;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ int sample_space;
+ int samples = 0;
+ int frames_left;
+ int i;
+ u32 ssifsr;
+ u16 *buf;
+
+ if (!rz_ssi_stream_is_valid(ssi, strm))
+ return -EINVAL;
+
+ /* frames left in this period */
+ frames_left = runtime->period_size - (strm->buffer_pos %
+ runtime->period_size);
+ if (frames_left == 0)
+ frames_left = runtime->period_size;
+
+ sample_space = strm->fifo_sample_size;
+ ssifsr = rz_ssi_reg_readl(ssi, SSIFSR);
+ sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK;
+
+ /* Only add full frames at a time */
+ while (frames_left && (sample_space >= runtime->channels)) {
+ samples += runtime->channels;
+ sample_space -= runtime->channels;
+ frames_left--;
+ }
+
+ /* no space to send anything right now */
+ if (samples == 0)
+ return 0;
+
+ /* calculate new buffer index */
+ buf = (u16 *)(runtime->dma_area);
+ buf += strm->buffer_pos * runtime->channels;
+
+ /* Note, only supports 16-bit samples */
+ for (i = 0; i < samples; i++)
+ rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16));
+
+ rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0);
+ rz_ssi_pointer_update(strm, samples / runtime->channels);
+
+ return 0;
+}
+
+static irqreturn_t rz_ssi_interrupt(int irq, void *data)
+{
+ struct rz_ssi_stream *strm = NULL;
+ struct rz_ssi_priv *ssi = data;
+ u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
+
+ if (ssi->playback.substream)
+ strm = &ssi->playback;
+ else if (ssi->capture.substream)
+ strm = &ssi->capture;
+ else
+ return IRQ_HANDLED; /* Left over TX/RX interrupt */
+
+ if (irq == ssi->irq_int) { /* error or idle */
+ if (ssisr & SSISR_TUIRQ)
+ strm->uerr_num++;
+ if (ssisr & SSISR_TOIRQ)
+ strm->oerr_num++;
+ if (ssisr & SSISR_RUIRQ)
+ strm->uerr_num++;
+ if (ssisr & SSISR_ROIRQ)
+ strm->oerr_num++;
+
+ if (ssisr & (SSISR_TUIRQ | SSISR_TOIRQ | SSISR_RUIRQ |
+ SSISR_ROIRQ)) {
+ /* Error handling */
+ /* You must reset (stop/restart) after each interrupt */
+ rz_ssi_stop(ssi, strm);
+
+ /* Clear all flags */
+ rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ |
+ SSISR_TUIRQ | SSISR_ROIRQ |
+ SSISR_RUIRQ, 0);
+
+ /* Add/remove more data */
+ strm->transfer(ssi, strm);
+
+ /* Resume */
+ rz_ssi_start(ssi, strm);
+ }
+ }
+
+ if (!strm->running)
+ return IRQ_HANDLED;
+
+ /* tx data empty */
+ if (irq == ssi->irq_tx)
+ strm->transfer(ssi, &ssi->playback);
+
+ /* rx data full */
+ if (irq == ssi->irq_rx) {
+ strm->transfer(ssi, &ssi->capture);
+ rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
+ struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
+ int ret = 0;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ /* Soft Reset */
+ rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST);
+ rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0);
+ udelay(5);
+
+ ret = rz_ssi_stream_init(ssi, strm, substream);
+ if (ret)
+ goto done;
+
+ ret = strm->transfer(ssi, strm);
+ if (ret)
+ goto done;
+
+ ret = rz_ssi_start(ssi, strm);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ rz_ssi_stop(ssi, strm);
+ rz_ssi_stream_quit(ssi, strm);
+ break;
+ }
+
+done:
+ return ret;
+}
+
+static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
+
+ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
+ case SND_SOC_DAIFMT_CBC_CFC:
+ break;
+ default:
+ dev_err(ssi->dev, "Codec should be clk and frame consumer\n");
+ return -EINVAL;
+ }
+
+ /*
+ * set clock polarity
+ *
+ * "normal" BCLK = Signal is available at rising edge of BCLK
+ * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge
+ */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ ssi->bckp_rise = false;
+ ssi->lrckp_fsync_fall = false;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ ssi->bckp_rise = false;
+ ssi->lrckp_fsync_fall = true;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ ssi->bckp_rise = true;
+ ssi->lrckp_fsync_fall = false;
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ ssi->bckp_rise = true;
+ ssi->lrckp_fsync_fall = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* only i2s support */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ break;
+ default:
+ dev_err(ssi->dev, "Only I2S mode is supported.\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
+ unsigned int sample_bits = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
+ unsigned int channels = params_channels(params);
+
+ if (sample_bits != 16) {
+ dev_err(ssi->dev, "Unsupported sample width: %d\n",
+ sample_bits);
+ return -EINVAL;
+ }
+
+ if (channels != 2) {
+ dev_err(ssi->dev, "Number of channels not matched: %d\n",
+ channels);
+ return -EINVAL;
+ }
+
+ return rz_ssi_clk_setup(ssi, params_rate(params),
+ params_channels(params));
+}
+
+static const struct snd_soc_dai_ops rz_ssi_dai_ops = {
+ .trigger = rz_ssi_dai_trigger,
+ .set_fmt = rz_ssi_dai_set_fmt,
+ .hw_params = rz_ssi_dai_hw_params,
+};
+
+static const struct snd_pcm_hardware rz_ssi_pcm_hardware = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID,
+ .buffer_bytes_max = PREALLOC_BUFFER,
+ .period_bytes_min = 32,
+ .period_bytes_max = 8192,
+ .channels_min = SSI_CHAN_MIN,
+ .channels_max = SSI_CHAN_MAX,
+ .periods_min = 1,
+ .periods_max = 32,
+ .fifo_size = 32 * 2,
+};
+
+static int rz_ssi_pcm_open(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware);
+
+ return snd_pcm_hw_constraint_integer(substream->runtime,
+ SNDRV_PCM_HW_PARAM_PERIODS);
+}
+
+static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component,
+ struct snd_pcm_substream *substream)
+{
+ struct snd_soc_dai *dai = rz_ssi_get_dai(substream);
+ struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
+ struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
+
+ return strm->buffer_pos;
+}
+
+static int rz_ssi_pcm_new(struct snd_soc_component *component,
+ struct snd_soc_pcm_runtime *rtd)
+{
+ snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
+ rtd->card->snd_card->dev,
+ PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
+ return 0;
+}
+
+static struct snd_soc_dai_driver rz_ssi_soc_dai[] = {
+ {
+ .name = "rz-ssi-dai",
+ .playback = {
+ .rates = SSI_RATES,
+ .formats = SSI_FMTS,
+ .channels_min = SSI_CHAN_MIN,
+ .channels_max = SSI_CHAN_MAX,
+ },
+ .capture = {
+ .rates = SSI_RATES,
+ .formats = SSI_FMTS,
+ .channels_min = SSI_CHAN_MIN,
+ .channels_max = SSI_CHAN_MAX,
+ },
+ .ops = &rz_ssi_dai_ops,
+ },
+};
+
+static const struct snd_soc_component_driver rz_ssi_soc_component = {
+ .name = "rz-ssi",
+ .open = rz_ssi_pcm_open,
+ .pointer = rz_ssi_pcm_pointer,
+ .pcm_construct = rz_ssi_pcm_new,
+};
+
+static int rz_ssi_probe(struct platform_device *pdev)
+{
+ struct rz_ssi_priv *ssi;
+ struct clk *audio_clk;
+ int ret;
+
+ ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
+ if (!ssi)
+ return -ENOMEM;
+
+ ssi->pdev = pdev;
+ ssi->dev = &pdev->dev;
+ ssi->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(ssi->base))
+ return PTR_ERR(ssi->base);
+
+ ssi->clk = devm_clk_get(&pdev->dev, "ssi");
+ if (IS_ERR(ssi->clk))
+ return PTR_ERR(ssi->clk);
+
+ ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr");
+ if (IS_ERR(ssi->sfr_clk))
+ return PTR_ERR(ssi->sfr_clk);
+
+ audio_clk = devm_clk_get(&pdev->dev, "audio_clk1");
+ if (IS_ERR(audio_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
+ "no audio clk1");
+
+ ssi->audio_clk_1 = clk_get_rate(audio_clk);
+ audio_clk = devm_clk_get(&pdev->dev, "audio_clk2");
+ if (IS_ERR(audio_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
+ "no audio clk2");
+
+ ssi->audio_clk_2 = clk_get_rate(audio_clk);
+ if (!(ssi->audio_clk_1 || ssi->audio_clk_2))
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "no audio clk1 or audio clk2");
+
+ ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2;
+
+ ssi->playback.transfer = rz_ssi_pio_send;
+ ssi->capture.transfer = rz_ssi_pio_recv;
+ ssi->playback.priv = ssi;
+ ssi->capture.priv = ssi;
+
+ /* Error Interrupt */
+ ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
+ if (ssi->irq_int < 0)
+ return dev_err_probe(&pdev->dev, -ENODEV,
+ "Unable to get SSI int_req IRQ\n");
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
+ 0, dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (int_req)\n");
+
+ /* Tx and Rx interrupts (pio only) */
+ ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
+ if (ssi->irq_tx < 0)
+ return dev_err_probe(&pdev->dev, -ENODEV,
+ "Unable to get SSI dma_tx IRQ\n");
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_tx, &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_tx)\n");
+
+ ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
+ if (ssi->irq_rx < 0)
+ return dev_err_probe(&pdev->dev, -ENODEV,
+ "Unable to get SSI dma_rx IRQ\n");
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_rx, &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_rx)\n");
+
+ ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(ssi->rstc))
+ return PTR_ERR(ssi->rstc);
+
+ reset_control_deassert(ssi->rstc);
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_resume_and_get(&pdev->dev);
+
+ spin_lock_init(&ssi->lock);
+ dev_set_drvdata(&pdev->dev, ssi);
+ ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component,
+ rz_ssi_soc_dai,
+ ARRAY_SIZE(rz_ssi_soc_dai));
+ if (ret < 0) {
+ pm_runtime_put(ssi->dev);
+ pm_runtime_disable(ssi->dev);
+ reset_control_assert(ssi->rstc);
+ dev_err(&pdev->dev, "failed to register snd component\n");
+ }
+
+ return ret;
+}
+
+static int rz_ssi_remove(struct platform_device *pdev)
+{
+ struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev);
+
+ pm_runtime_put(ssi->dev);
+ pm_runtime_disable(ssi->dev);
+ reset_control_assert(ssi->rstc);
+
+ return 0;
+}
+
+static const struct of_device_id rz_ssi_of_match[] = {
+ { .compatible = "renesas,rz-ssi", },
+ {/* Sentinel */},
+};
+MODULE_DEVICE_TABLE(of, rz_ssi_of_match);
+
+static struct platform_driver rz_ssi_driver = {
+ .driver = {
+ .name = "rz-ssi-pcm-audio",
+ .of_match_table = rz_ssi_of_match,
+ },
+ .probe = rz_ssi_probe,
+ .remove = rz_ssi_remove,
+};
+
+module_platform_driver(rz_ssi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver");
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 5.10.y-cip 03/31] ASoC: sh: Add RZ/G2L SSIF-2 driver
2021-12-29 10:15 ` [PATCH 5.10.y-cip 03/31] ASoC: sh: Add RZ/G2L SSIF-2 driver Lad Prabhakar
@ 2021-12-30 11:15 ` Pavel Machek
2021-12-30 14:18 ` Prabhakar Mahadev Lad
0 siblings, 1 reply; 42+ messages in thread
From: Pavel Machek @ 2021-12-30 11:15 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 5184 bytes --]
Hi!
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> commit 03e786bd43410fa93e5d2459f7a43e90ff0ae801 upstream.
>
> Add serial sound interface(SSIF-2) driver support for
> RZ/G2L SoC.
>
> Based on the work done by Chris Brandt for RZ/A SSI driver.
I'm not sure what the locking rules are here.
> --- /dev/null
> +++ b/sound/soc/sh/rz-ssi.c
> +static int rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
> + struct rz_ssi_stream *strm)
> +{
> + unsigned long flags;
> + int ret;
> +
> + spin_lock_irqsave(&ssi->lock, flags);
> + ret = !!(strm->substream && strm->substream->runtime);
> + spin_unlock_irqrestore(&ssi->lock, flags);
> +
> + return ret;
> +}
Nit: I don't think !!() is useful here, as it is boolean expression
anyway.
But I notice that code is very careful to access strm->substream with
spinlock held.
> +static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames)
> +{
> + struct snd_pcm_substream *substream = strm->substream;
> + struct snd_pcm_runtime *runtime;
> + int current_period;
> +
> + if (!strm->running || !substream || !substream->runtime)
> + return;
But here we do same checks, and this time without the spinlock?
> +static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
> +{
> + struct snd_pcm_substream *substream = strm->substream;
> + struct snd_pcm_runtime *runtime;
> + u16 *buf;
> + int fifo_samples;
> + int frames_left;
> + int samples = 0;
> + int i;
> +
> + if (!rz_ssi_stream_is_valid(ssi, strm))
> + return -EINVAL;
> +
> + runtime = substream->runtime;
Again, access without locking.
> + /*
> + * If we finished this period, but there are more samples in
> + * the RX FIFO, call this function again
> + */
> + if (frames_left == 0 && fifo_samples >= runtime->channels)
> + rz_ssi_pio_recv(ssi, strm);
Here we call ourselves recurively. Without checking the return
value.. but more importantly recursion is unwelcome in kernel due to
limited stack use.
> +static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
> +{
> + struct snd_pcm_substream *substream = strm->substream;
> + struct snd_pcm_runtime *runtime = substream->runtime;
> + int sample_space;
> + int samples = 0;
> + int frames_left;
> + int i;
> + u32 ssifsr;
> + u16 *buf;
> +
> + if (!rz_ssi_stream_is_valid(ssi, strm))
> + return -EINVAL;
Access without locking before verifying that stream is valid with the
lock. This is wrong.
> +static irqreturn_t rz_ssi_interrupt(int irq, void *data)
> +{
> + struct rz_ssi_stream *strm = NULL;
> + struct rz_ssi_priv *ssi = data;
> + u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
> +
> + if (ssi->playback.substream)
> + strm = &ssi->playback;
> + else if (ssi->capture.substream)
> + strm = &ssi->capture;
> + else
> + return IRQ_HANDLED; /* Left over TX/RX interrupt */
You mark interrupt as handled even when it is not. Probably not a
problem w/o shared interrupts.
> +static int rz_ssi_probe(struct platform_device *pdev)
> +{
...
> + /* Error Interrupt */
> + ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
> + if (ssi->irq_int < 0)
> + return dev_err_probe(&pdev->dev, -ENODEV,
> + "Unable to get SSI int_req IRQ\n");
> +
> + ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
> + 0, dev_name(&pdev->dev), ssi);
> + if (ret < 0)
> + return dev_err_probe(&pdev->dev, ret,
> + "irq request error (int_req)\n");
> +
> + /* Tx and Rx interrupts (pio only) */
> + ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
> + if (ssi->irq_tx < 0)
> + return dev_err_probe(&pdev->dev, -ENODEV,
> + "Unable to get SSI dma_tx IRQ\n");
...
So you registered interrupt handlers...
> +
> + ret = devm_request_irq(&pdev->dev, ssi->irq_tx, &rz_ssi_interrupt, 0,
> + dev_name(&pdev->dev), ssi);
> + if (ret < 0)
> + return dev_err_probe(&pdev->dev, ret,
> + "irq request error (dma_tx)\n");
> +
> + ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
> + if (ssi->irq_rx < 0)
> + return dev_err_probe(&pdev->dev, -ENODEV,
> + "Unable to get SSI dma_rx IRQ\n");
> +
> + ret = devm_request_irq(&pdev->dev, ssi->irq_rx, &rz_ssi_interrupt, 0,
> + dev_name(&pdev->dev), ssi);
> + if (ret < 0)
> + return dev_err_probe(&pdev->dev, ret,
> + "irq request error (dma_rx)\n");
> +
> + ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> + if (IS_ERR(ssi->rstc))
> + return PTR_ERR(ssi->rstc);
> +
> + reset_control_deassert(ssi->rstc);
> + pm_runtime_enable(&pdev->dev);
> + pm_runtime_resume_and_get(&pdev->dev);
> +
> + spin_lock_init(&ssi->lock);
> + dev_set_drvdata(&pdev->dev, ssi);
But only here you have data structures ready to handle the
interrupts. You won't see obvious problems w/o shared interrupts, but
I believe there are debugging modes that trigger this intentionally.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH 5.10.y-cip 03/31] ASoC: sh: Add RZ/G2L SSIF-2 driver
2021-12-30 11:15 ` Pavel Machek
@ 2021-12-30 14:18 ` Prabhakar Mahadev Lad
2021-12-30 20:07 ` Pavel Machek
0 siblings, 1 reply; 42+ messages in thread
From: Prabhakar Mahadev Lad @ 2021-12-30 14:18 UTC (permalink / raw)
To: Pavel Machek; +Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu, Biju Das
Hi Pavel,
Thank you for the review.
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 30 December 2021 11:15
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 03/31] ASoC: sh: Add RZ/G2L SSIF-2 driver
>
> Hi!
>
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > commit 03e786bd43410fa93e5d2459f7a43e90ff0ae801 upstream.
> >
> > Add serial sound interface(SSIF-2) driver support for RZ/G2L SoC.
> >
> > Based on the work done by Chris Brandt for RZ/A SSI driver.
>
> I'm not sure what the locking rules are here.
>
> > --- /dev/null
> > +++ b/sound/soc/sh/rz-ssi.c
> > +static int rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
> > + struct rz_ssi_stream *strm)
> > +{
> > + unsigned long flags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&ssi->lock, flags);
> > + ret = !!(strm->substream && strm->substream->runtime);
> > + spin_unlock_irqrestore(&ssi->lock, flags);
> > +
> > + return ret;
> > +}
>
> Nit: I don't think !!() is useful here, as it is boolean expression anyway.
>
Agreed can be dropped.
> But I notice that code is very careful to access strm->substream with spinlock held.
>
...
> > +static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int
> > +frames) {
> > + struct snd_pcm_substream *substream = strm->substream;
> > + struct snd_pcm_runtime *runtime;
> > + int current_period;
> > +
> > + if (!strm->running || !substream || !substream->runtime)
> > + return;
>
> But here we do same checks, and this time without the spinlock?
>
... agree we need to lock...
> > +static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct
> > +rz_ssi_stream *strm) {
> > + struct snd_pcm_substream *substream = strm->substream;
> > + struct snd_pcm_runtime *runtime;
> > + u16 *buf;
> > + int fifo_samples;
> > + int frames_left;
> > + int samples = 0;
> > + int i;
> > +
> > + if (!rz_ssi_stream_is_valid(ssi, strm))
> > + return -EINVAL;
> > +
> > + runtime = substream->runtime;
>
> Again, access without locking.
>
... and here too.
> > + /*
> > + * If we finished this period, but there are more samples in
> > + * the RX FIFO, call this function again
> > + */
> > + if (frames_left == 0 && fifo_samples >= runtime->channels)
> > + rz_ssi_pio_recv(ssi, strm);
>
> Here we call ourselves recurively. Without checking the return value.. but more importantly recursion
> is unwelcome in kernel due to limited stack use.
>
>
Agreed, this needs to be handled differently with recursion removed.
> > +static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct
> > +rz_ssi_stream *strm) {
> > + struct snd_pcm_substream *substream = strm->substream;
> > + struct snd_pcm_runtime *runtime = substream->runtime;
> > + int sample_space;
> > + int samples = 0;
> > + int frames_left;
> > + int i;
> > + u32 ssifsr;
> > + u16 *buf;
> > +
> > + if (!rz_ssi_stream_is_valid(ssi, strm))
> > + return -EINVAL;
>
> Access without locking before verifying that stream is valid with the lock. This is wrong.
>
rz_ssi_stream_is_valid() does lock/unlock to check stream validity.
> > +static irqreturn_t rz_ssi_interrupt(int irq, void *data) {
> > + struct rz_ssi_stream *strm = NULL;
> > + struct rz_ssi_priv *ssi = data;
> > + u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
> > +
> > + if (ssi->playback.substream)
> > + strm = &ssi->playback;
> > + else if (ssi->capture.substream)
> > + strm = &ssi->capture;
> > + else
> > + return IRQ_HANDLED; /* Left over TX/RX interrupt */
>
> You mark interrupt as handled even when it is not. Probably not a problem w/o shared interrupts.
>
ATM the interrupts aren't shared so this should be OK.
> > +static int rz_ssi_probe(struct platform_device *pdev) {
> ...
> > + /* Error Interrupt */
> > + ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
> > + if (ssi->irq_int < 0)
> > + return dev_err_probe(&pdev->dev, -ENODEV,
> > + "Unable to get SSI int_req IRQ\n");
> > +
> > + ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
> > + 0, dev_name(&pdev->dev), ssi);
> > + if (ret < 0)
> > + return dev_err_probe(&pdev->dev, ret,
> > + "irq request error (int_req)\n");
> > +
> > + /* Tx and Rx interrupts (pio only) */
> > + ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
> > + if (ssi->irq_tx < 0)
> > + return dev_err_probe(&pdev->dev, -ENODEV,
> > + "Unable to get SSI dma_tx IRQ\n");
> ...
>
> So you registered interrupt handlers...
>
> > +
> > + ret = devm_request_irq(&pdev->dev, ssi->irq_tx, &rz_ssi_interrupt, 0,
> > + dev_name(&pdev->dev), ssi);
> > + if (ret < 0)
> > + return dev_err_probe(&pdev->dev, ret,
> > + "irq request error (dma_tx)\n");
> > +
> > + ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
> > + if (ssi->irq_rx < 0)
> > + return dev_err_probe(&pdev->dev, -ENODEV,
> > + "Unable to get SSI dma_rx IRQ\n");
> > +
> > + ret = devm_request_irq(&pdev->dev, ssi->irq_rx, &rz_ssi_interrupt, 0,
> > + dev_name(&pdev->dev), ssi);
> > + if (ret < 0)
> > + return dev_err_probe(&pdev->dev, ret,
> > + "irq request error (dma_rx)\n");
> > +
> > + ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > + if (IS_ERR(ssi->rstc))
> > + return PTR_ERR(ssi->rstc);
> > +
> > + reset_control_deassert(ssi->rstc);
> > + pm_runtime_enable(&pdev->dev);
> > + pm_runtime_resume_and_get(&pdev->dev);
> > +
> > + spin_lock_init(&ssi->lock);
> > + dev_set_drvdata(&pdev->dev, ssi);
>
> But only here you have data structures ready to handle the interrupts. You won't see obvious problems
> w/o shared interrupts, but I believe there are debugging modes that trigger this intentionally.
>
But the devm_snd_soc_register_component() is after this so it should be OK I believe unless there is a spurious interrupt which will trigger the handler.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH 5.10.y-cip 03/31] ASoC: sh: Add RZ/G2L SSIF-2 driver
2021-12-30 14:18 ` Prabhakar Mahadev Lad
@ 2021-12-30 20:07 ` Pavel Machek
0 siblings, 0 replies; 42+ messages in thread
From: Pavel Machek @ 2021-12-30 20:07 UTC (permalink / raw)
To: Prabhakar Mahadev Lad
Cc: Pavel Machek, cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu,
Biju Das
[-- Attachment #1: Type: text/plain, Size: 3470 bytes --]
Hi!
> > > +static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct
> > > +rz_ssi_stream *strm) {
> > > + struct snd_pcm_substream *substream = strm->substream;
> > > + struct snd_pcm_runtime *runtime = substream->runtime;
> > > + int sample_space;
> > > + int samples = 0;
> > > + int frames_left;
> > > + int i;
> > > + u32 ssifsr;
> > > + u16 *buf;
> > > +
> > > + if (!rz_ssi_stream_is_valid(ssi, strm))
> > > + return -EINVAL;
> >
> > Access without locking before verifying that stream is valid with the lock. This is wrong.
> >
> rz_ssi_stream_is_valid() does lock/unlock to check stream validity.
Yes, but "struct snd_pcm_runtime *runtime = substream->runtime" above
already accessed that data without locking.
> > > +static int rz_ssi_probe(struct platform_device *pdev) {
> > ...
> > > + /* Error Interrupt */
> > > + ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
> > > + if (ssi->irq_int < 0)
> > > + return dev_err_probe(&pdev->dev, -ENODEV,
> > > + "Unable to get SSI int_req IRQ\n");
> > > +
> > > + ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
> > > + 0, dev_name(&pdev->dev), ssi);
> > > + if (ret < 0)
> > > + return dev_err_probe(&pdev->dev, ret,
> > > + "irq request error (int_req)\n");
> > > +
> > > + /* Tx and Rx interrupts (pio only) */
> > > + ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
> > > + if (ssi->irq_tx < 0)
> > > + return dev_err_probe(&pdev->dev, -ENODEV,
> > > + "Unable to get SSI dma_tx IRQ\n");
> > ...
> >
> > So you registered interrupt handlers...
> >
> > > +
> > > + ret = devm_request_irq(&pdev->dev, ssi->irq_tx, &rz_ssi_interrupt, 0,
> > > + dev_name(&pdev->dev), ssi);
> > > + if (ret < 0)
> > > + return dev_err_probe(&pdev->dev, ret,
> > > + "irq request error (dma_tx)\n");
> > > +
> > > + ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
> > > + if (ssi->irq_rx < 0)
> > > + return dev_err_probe(&pdev->dev, -ENODEV,
> > > + "Unable to get SSI dma_rx IRQ\n");
> > > +
> > > + ret = devm_request_irq(&pdev->dev, ssi->irq_rx, &rz_ssi_interrupt, 0,
> > > + dev_name(&pdev->dev), ssi);
> > > + if (ret < 0)
> > > + return dev_err_probe(&pdev->dev, ret,
> > > + "irq request error (dma_rx)\n");
> > > +
> > > + ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > > + if (IS_ERR(ssi->rstc))
> > > + return PTR_ERR(ssi->rstc);
> > > +
> > > + reset_control_deassert(ssi->rstc);
> > > + pm_runtime_enable(&pdev->dev);
> > > + pm_runtime_resume_and_get(&pdev->dev);
> > > +
> > > + spin_lock_init(&ssi->lock);
> > > + dev_set_drvdata(&pdev->dev, ssi);
> >
> > But only here you have data structures ready to handle the interrupts. You won't see obvious problems
> > w/o shared interrupts, but I believe there are debugging modes that trigger this intentionally.
> >
> But the devm_snd_soc_register_component() is after this so it should be OK I believe unless there is a spurious interrupt which will trigger the handler.
>
I believe your code will do fine in usual configurations. But
reordering it should be quite easy, and there are kernel options like
"irqpoll", "irqfixup" and CONFIG_DEBUG_SHIRQ.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel configuration parameter
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (2 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 03/31] ASoC: sh: Add RZ/G2L SSIF-2 driver Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-30 10:55 ` Pavel Machek
2021-12-29 10:15 ` [PATCH 5.10.y-cip 05/31] ASoC: sh: rz-ssi: Add SSI DMAC support Lad Prabhakar
` (26 subsequent siblings)
30 siblings, 1 reply; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit bed0b1c1e88a27b76c74584128cadebc6fa58622 upstream.
The DMAC on RZ/G2L has specific slave channel configuration
parameters for SSI.
This patch updates the dmas description and example node to include
the encoded slave channel configuration.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210813091156.10700-3-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/sound/renesas,rz-ssi.yaml | 22 +++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
index 471937cb8d05..414ff8035a4e 100644
--- a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
@@ -48,6 +48,24 @@ properties:
dmas:
minItems: 1
maxItems: 2
+ description:
+ The first cell represents a phandle to dmac
+ The second cell specifies the encoded MID/RID values of the SSI port
+ connected to the DMA client and the slave channel configuration
+ parameters.
+ bits[0:9] - Specifies MID/RID value of a SSI channel as below
+ MID/RID value of SSI rx0 = 0x256
+ MID/RID value of SSI tx0 = 0x255
+ MID/RID value of SSI rx1 = 0x25a
+ MID/RID value of SSI tx1 = 0x259
+ MID/RID value of SSI rt2 = 0x25f
+ MID/RID value of SSI rx3 = 0x262
+ MID/RID value of SSI tx3 = 0x261
+ bit[10] - HIEN = 1, Detects a request in response to the rising edge
+ of the signal
+ bit[11] - LVL = 0, Detects based on the edge
+ bits[12:14] - AM = 2, Bus cycle mode
+ bit[15] - TM = 0, Single transfer mode
dma-names:
oneOf:
@@ -93,8 +111,8 @@ examples:
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
- dmas = <&dmac 0x255>,
- <&dmac 0x256>;
+ dmas = <&dmac 0x2655>,
+ <&dmac 0x2656>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel configuration parameter
2021-12-29 10:15 ` [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel configuration parameter Lad Prabhakar
@ 2021-12-30 10:55 ` Pavel Machek
2021-12-30 13:36 ` Prabhakar Mahadev Lad
2022-01-04 10:25 ` Biju Das
0 siblings, 2 replies; 42+ messages in thread
From: Pavel Machek @ 2021-12-30 10:55 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 1775 bytes --]
Hi!
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> commit bed0b1c1e88a27b76c74584128cadebc6fa58622 upstream.
>
> The DMAC on RZ/G2L has specific slave channel configuration
> parameters for SSI.
> This patch updates the dmas description and example node to include
> the encoded slave channel configuration.
> +++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
> @@ -48,6 +48,24 @@ properties:
> dmas:
> minItems: 1
> maxItems: 2
> + description:
> + The first cell represents a phandle to dmac
> + The second cell specifies the encoded MID/RID values of the SSI port
> + connected to the DMA client and the slave channel configuration
> + parameters.
> + bits[0:9] - Specifies MID/RID value of a SSI channel as below
> + MID/RID value of SSI rx0 = 0x256
> + MID/RID value of SSI tx0 = 0x255
> + MID/RID value of SSI rx1 = 0x25a
> + MID/RID value of SSI tx1 = 0x259
> + MID/RID value of SSI rt2 = 0x25f
> + MID/RID value of SSI rx3 = 0x262
> + MID/RID value of SSI tx3 = 0x261
> + bit[10] - HIEN = 1, Detects a request in response to the rising edge
> + of the signal
> + bit[11] - LVL = 0, Detects based on the edge
> + bits[12:14] - AM = 2, Bus cycle mode
> + bit[15] - TM = 0, Single transfer mode
I wish there was better solution to this. Device tree sources are
quite human-readable, this really is not.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel configuration parameter
2021-12-30 10:55 ` Pavel Machek
@ 2021-12-30 13:36 ` Prabhakar Mahadev Lad
2022-01-04 10:25 ` Biju Das
1 sibling, 0 replies; 42+ messages in thread
From: Prabhakar Mahadev Lad @ 2021-12-30 13:36 UTC (permalink / raw)
To: Pavel Machek; +Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu, Biju Das
Hi Pavel,
Thank you for the review.
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 30 December 2021 10:55
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel
> configuration parameter
>
> Hi!
>
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > commit bed0b1c1e88a27b76c74584128cadebc6fa58622 upstream.
> >
> > The DMAC on RZ/G2L has specific slave channel configuration parameters
> > for SSI.
> > This patch updates the dmas description and example node to include
> > the encoded slave channel configuration.
>
> > +++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
> > @@ -48,6 +48,24 @@ properties:
> > dmas:
> > minItems: 1
> > maxItems: 2
> > + description:
> > + The first cell represents a phandle to dmac
> > + The second cell specifies the encoded MID/RID values of the SSI port
> > + connected to the DMA client and the slave channel configuration
> > + parameters.
> > + bits[0:9] - Specifies MID/RID value of a SSI channel as below
> > + MID/RID value of SSI rx0 = 0x256
> > + MID/RID value of SSI tx0 = 0x255
> > + MID/RID value of SSI rx1 = 0x25a
> > + MID/RID value of SSI tx1 = 0x259
> > + MID/RID value of SSI rt2 = 0x25f
> > + MID/RID value of SSI rx3 = 0x262
> > + MID/RID value of SSI tx3 = 0x261
> > + bit[10] - HIEN = 1, Detects a request in response to the rising edge
> > + of the signal
> > + bit[11] - LVL = 0, Detects based on the edge
> > + bits[12:14] - AM = 2, Bus cycle mode
> > + bit[15] - TM = 0, Single transfer mode
>
> I wish there was better solution to this. Device tree sources are quite human-readable, this really is
> not.
>
Do agree!
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel configuration parameter
2021-12-30 10:55 ` Pavel Machek
2021-12-30 13:36 ` Prabhakar Mahadev Lad
@ 2022-01-04 10:25 ` Biju Das
1 sibling, 0 replies; 42+ messages in thread
From: Biju Das @ 2022-01-04 10:25 UTC (permalink / raw)
To: Pavel Machek, Prabhakar Mahadev Lad
Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu
Hi Pavel,
> Subject: Re: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi:
> Update slave dma channel configuration parameter
>
> Hi!
>
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > commit bed0b1c1e88a27b76c74584128cadebc6fa58622 upstream.
> >
> > The DMAC on RZ/G2L has specific slave channel configuration parameters
> > for SSI.
> > This patch updates the dmas description and example node to include
> > the encoded slave channel configuration.
>
> > +++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml
> > @@ -48,6 +48,24 @@ properties:
> > dmas:
> > minItems: 1
> > maxItems: 2
> > + description:
> > + The first cell represents a phandle to dmac
> > + The second cell specifies the encoded MID/RID values of the SSI
> port
> > + connected to the DMA client and the slave channel configuration
> > + parameters.
> > + bits[0:9] - Specifies MID/RID value of a SSI channel as below
> > + MID/RID value of SSI rx0 = 0x256
> > + MID/RID value of SSI tx0 = 0x255
> > + MID/RID value of SSI rx1 = 0x25a
> > + MID/RID value of SSI tx1 = 0x259
> > + MID/RID value of SSI rt2 = 0x25f
> > + MID/RID value of SSI rx3 = 0x262
> > + MID/RID value of SSI tx3 = 0x261
> > + bit[10] - HIEN = 1, Detects a request in response to the
> rising edge
> > + of the signal
> > + bit[11] - LVL = 0, Detects based on the edge
> > + bits[12:14] - AM = 2, Bus cycle mode
> > + bit[15] - TM = 0, Single transfer mode
>
> I wish there was better solution to this. Device tree sources are quite
> human-readable, this really is not.
Can you please suggest the better solution?
Cheers,
Biju
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 5.10.y-cip 05/31] ASoC: sh: rz-ssi: Add SSI DMAC support
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (3 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel configuration parameter Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 06/31] ASoC: sh: rz-ssi: Fix dereference of noderef expression warning Lad Prabhakar
` (25 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 26ac471c5354583cf4fe0e42537a2c6b84d6d74e upstream.
Add SSI DMAC support to RZ/G2L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210813091156.10700-4-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
[PL: dropped modern terminology for clocking]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
sound/soc/sh/rz-ssi.c | 260 ++++++++++++++++++++++++++++++++++++------
1 file changed, 226 insertions(+), 34 deletions(-)
diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index 615fa81f061e..4e702b7d5b49 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -7,6 +7,7 @@
//
#include <linux/clk.h>
+#include <linux/dmaengine.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
@@ -86,6 +87,7 @@ struct rz_ssi_stream {
struct rz_ssi_priv *priv;
struct snd_pcm_substream *substream;
int fifo_sample_size; /* sample capacity of SSI FIFO */
+ int dma_buffer_pos; /* The address for the next DMA descriptor */
int period_counter; /* for keeping track of periods transferred */
int sample_width;
int buffer_pos; /* current frame position in the buffer */
@@ -94,6 +96,8 @@ struct rz_ssi_stream {
int uerr_num;
int oerr_num;
+ struct dma_chan *dma_ch;
+
int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
};
@@ -105,6 +109,7 @@ struct rz_ssi_priv {
struct clk *sfr_clk;
struct clk *clk;
+ phys_addr_t phys;
int irq_int;
int irq_tx;
int irq_rx;
@@ -128,8 +133,11 @@ struct rz_ssi_priv {
bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */
bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */
+ bool dma_rt;
};
+static void rz_ssi_dma_complete(void *data);
+
static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data)
{
writel(data, (priv->base + reg));
@@ -175,6 +183,11 @@ rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
return stream;
}
+static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi)
+{
+ return (ssi->playback.dma_ch || ssi->capture.dma_ch);
+}
+
static int rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
struct rz_ssi_stream *strm)
{
@@ -196,6 +209,7 @@ static int rz_ssi_stream_init(struct rz_ssi_priv *ssi,
strm->substream = substream;
strm->sample_width = samples_to_bytes(runtime, 1);
+ strm->dma_buffer_pos = 0;
strm->period_counter = 0;
strm->buffer_pos = 0;
@@ -297,9 +311,12 @@ static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
ssifcr = rz_ssi_reg_readl(ssi, SSIFCR) & ~0xF;
/* FIFO interrupt thresholds */
- rz_ssi_reg_writel(ssi, SSISCR,
- SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
- SSISCR_RDFS(0));
+ if (rz_ssi_is_dma_enabled(ssi))
+ rz_ssi_reg_writel(ssi, SSISCR, 0);
+ else
+ rz_ssi_reg_writel(ssi, SSISCR,
+ SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
+ SSISCR_RDFS(0));
/* enable IRQ */
if (is_play) {
@@ -334,6 +351,10 @@ static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
/* Disable TX/RX */
rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
+ /* Cancel all remaining DMA transactions */
+ if (rz_ssi_is_dma_enabled(ssi))
+ dmaengine_terminate_async(strm->dma_ch);
+
/* Disable irqs */
rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN |
SSICR_RUIEN | SSICR_ROIEN, 0);
@@ -549,12 +570,143 @@ static irqreturn_t rz_ssi_interrupt(int irq, void *data)
return IRQ_HANDLED;
}
+static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi,
+ struct dma_chan *dma_ch, bool is_play)
+{
+ struct dma_slave_config cfg;
+
+ memset(&cfg, 0, sizeof(cfg));
+
+ cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
+ cfg.dst_addr = ssi->phys + SSIFTDR;
+ cfg.src_addr = ssi->phys + SSIFRDR;
+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+
+ return dmaengine_slave_config(dma_ch, &cfg);
+}
+
+static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi,
+ struct rz_ssi_stream *strm)
+{
+ struct snd_pcm_substream *substream = strm->substream;
+ struct dma_async_tx_descriptor *desc;
+ struct snd_pcm_runtime *runtime;
+ enum dma_transfer_direction dir;
+ u32 dma_paddr, dma_size;
+ int amount;
+
+ if (!rz_ssi_stream_is_valid(ssi, strm))
+ return -EINVAL;
+
+ runtime = substream->runtime;
+ if (runtime->status->state == SNDRV_PCM_STATE_DRAINING)
+ /*
+ * Stream is ending, so do not queue up any more DMA
+ * transfers otherwise we play partial sound clips
+ * because we can't shut off the DMA quick enough.
+ */
+ return 0;
+
+ dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
+
+ /* Always transfer 1 period */
+ amount = runtime->period_size;
+
+ /* DMA physical address and size */
+ dma_paddr = runtime->dma_addr + frames_to_bytes(runtime,
+ strm->dma_buffer_pos);
+ dma_size = frames_to_bytes(runtime, amount);
+ desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size,
+ dir,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ if (!desc) {
+ dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n");
+ return -ENOMEM;
+ }
+
+ desc->callback = rz_ssi_dma_complete;
+ desc->callback_param = strm;
+
+ if (dmaengine_submit(desc) < 0) {
+ dev_err(ssi->dev, "dmaengine_submit() fail\n");
+ return -EIO;
+ }
+
+ /* Update DMA pointer */
+ strm->dma_buffer_pos += amount;
+ if (strm->dma_buffer_pos >= runtime->buffer_size)
+ strm->dma_buffer_pos = 0;
+
+ /* Start DMA */
+ dma_async_issue_pending(strm->dma_ch);
+
+ return 0;
+}
+
+static void rz_ssi_dma_complete(void *data)
+{
+ struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data;
+
+ if (!strm->running || !strm->substream || !strm->substream->runtime)
+ return;
+
+ /* Note that next DMA transaction has probably already started */
+ rz_ssi_pointer_update(strm, strm->substream->runtime->period_size);
+
+ /* Queue up another DMA transaction */
+ rz_ssi_dma_transfer(strm->priv, strm);
+}
+
+static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi)
+{
+ if (ssi->playback.dma_ch) {
+ dma_release_channel(ssi->playback.dma_ch);
+ ssi->playback.dma_ch = NULL;
+ if (ssi->dma_rt)
+ ssi->dma_rt = false;
+ }
+
+ if (ssi->capture.dma_ch) {
+ dma_release_channel(ssi->capture.dma_ch);
+ ssi->capture.dma_ch = NULL;
+ }
+}
+
+static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev)
+{
+ ssi->playback.dma_ch = dma_request_chan(dev, "tx");
+ ssi->capture.dma_ch = dma_request_chan(dev, "rx");
+ if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) {
+ ssi->playback.dma_ch = dma_request_chan(dev, "rt");
+ if (!ssi->playback.dma_ch)
+ goto no_dma;
+
+ ssi->dma_rt = true;
+ }
+
+ if (ssi->playback.dma_ch &&
+ (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0))
+ goto no_dma;
+
+ if (ssi->capture.dma_ch &&
+ (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0))
+ goto no_dma;
+
+ return 0;
+
+no_dma:
+ rz_ssi_release_dma_channels(ssi);
+
+ return -ENODEV;
+}
+
static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
- int ret = 0;
+ int ret = 0, i, num_transfer = 1;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
@@ -567,9 +719,29 @@ static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
if (ret)
goto done;
- ret = strm->transfer(ssi, strm);
- if (ret)
- goto done;
+ if (ssi->dma_rt) {
+ bool is_playback;
+
+ is_playback = rz_ssi_stream_is_play(ssi, substream);
+ ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch,
+ is_playback);
+ /* Fallback to pio */
+ if (ret < 0) {
+ ssi->playback.transfer = rz_ssi_pio_send;
+ ssi->capture.transfer = rz_ssi_pio_recv;
+ rz_ssi_release_dma_channels(ssi);
+ }
+ }
+
+ /* For DMA, queue up multiple DMA descriptors */
+ if (rz_ssi_is_dma_enabled(ssi))
+ num_transfer = 4;
+
+ for (i = 0; i < num_transfer; i++) {
+ ret = strm->transfer(ssi, strm);
+ if (ret)
+ goto done;
+ }
ret = rz_ssi_start(ssi, strm);
break;
@@ -587,8 +759,8 @@ static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
- switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
- case SND_SOC_DAIFMT_CBC_CFC:
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
dev_err(ssi->dev, "Codec should be clk and frame consumer\n");
@@ -737,6 +909,7 @@ static int rz_ssi_probe(struct platform_device *pdev)
{
struct rz_ssi_priv *ssi;
struct clk *audio_clk;
+ struct resource *res;
int ret;
ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
@@ -745,10 +918,11 @@ static int rz_ssi_probe(struct platform_device *pdev)
ssi->pdev = pdev;
ssi->dev = &pdev->dev;
- ssi->base = devm_platform_ioremap_resource(pdev, 0);
+ ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(ssi->base))
return PTR_ERR(ssi->base);
+ ssi->phys = res->start;
ssi->clk = devm_clk_get(&pdev->dev, "ssi");
if (IS_ERR(ssi->clk))
return PTR_ERR(ssi->clk);
@@ -775,8 +949,18 @@ static int rz_ssi_probe(struct platform_device *pdev)
ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2;
- ssi->playback.transfer = rz_ssi_pio_send;
- ssi->capture.transfer = rz_ssi_pio_recv;
+ /* Detect DMA support */
+ ret = rz_ssi_dma_request(ssi, &pdev->dev);
+ if (ret < 0) {
+ dev_warn(&pdev->dev, "DMA not available, using PIO\n");
+ ssi->playback.transfer = rz_ssi_pio_send;
+ ssi->capture.transfer = rz_ssi_pio_recv;
+ } else {
+ dev_info(&pdev->dev, "DMA enabled");
+ ssi->playback.transfer = rz_ssi_dma_transfer;
+ ssi->capture.transfer = rz_ssi_dma_transfer;
+ }
+
ssi->playback.priv = ssi;
ssi->capture.priv = ssi;
@@ -792,28 +976,32 @@ static int rz_ssi_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, ret,
"irq request error (int_req)\n");
- /* Tx and Rx interrupts (pio only) */
- ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
- if (ssi->irq_tx < 0)
- return dev_err_probe(&pdev->dev, -ENODEV,
- "Unable to get SSI dma_tx IRQ\n");
-
- ret = devm_request_irq(&pdev->dev, ssi->irq_tx, &rz_ssi_interrupt, 0,
- dev_name(&pdev->dev), ssi);
- if (ret < 0)
- return dev_err_probe(&pdev->dev, ret,
- "irq request error (dma_tx)\n");
-
- ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
- if (ssi->irq_rx < 0)
- return dev_err_probe(&pdev->dev, -ENODEV,
- "Unable to get SSI dma_rx IRQ\n");
-
- ret = devm_request_irq(&pdev->dev, ssi->irq_rx, &rz_ssi_interrupt, 0,
- dev_name(&pdev->dev), ssi);
- if (ret < 0)
- return dev_err_probe(&pdev->dev, ret,
- "irq request error (dma_rx)\n");
+ if (!rz_ssi_is_dma_enabled(ssi)) {
+ /* Tx and Rx interrupts (pio only) */
+ ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
+ if (ssi->irq_tx < 0)
+ return dev_err_probe(&pdev->dev, -ENODEV,
+ "Unable to get SSI dma_tx IRQ\n");
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
+ &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_tx)\n");
+
+ ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
+ if (ssi->irq_rx < 0)
+ return dev_err_probe(&pdev->dev, -ENODEV,
+ "Unable to get SSI dma_rx IRQ\n");
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
+ &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_rx)\n");
+ }
ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(ssi->rstc))
@@ -829,6 +1017,8 @@ static int rz_ssi_probe(struct platform_device *pdev)
rz_ssi_soc_dai,
ARRAY_SIZE(rz_ssi_soc_dai));
if (ret < 0) {
+ rz_ssi_release_dma_channels(ssi);
+
pm_runtime_put(ssi->dev);
pm_runtime_disable(ssi->dev);
reset_control_assert(ssi->rstc);
@@ -842,6 +1032,8 @@ static int rz_ssi_remove(struct platform_device *pdev)
{
struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev);
+ rz_ssi_release_dma_channels(ssi);
+
pm_runtime_put(ssi->dev);
pm_runtime_disable(ssi->dev);
reset_control_assert(ssi->rstc);
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 06/31] ASoC: sh: rz-ssi: Fix dereference of noderef expression warning
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (4 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 05/31] ASoC: sh: rz-ssi: Add SSI DMAC support Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 07/31] ASoC: sh: rz-ssi: Fix wrong operator used issue Lad Prabhakar
` (24 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit d40dfb860ad72a32b9c2aeae739a2725f8ce011a upstream.
Fix following sparse warning:
sound/soc/sh/rz-ssi.c:156:15: sparse: warning: dereference of
noderef expression
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20210816132049.28128-1-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
sound/soc/sh/rz-ssi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index 4e702b7d5b49..d96c1bea047c 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -148,7 +148,7 @@ static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg)
return readl(priv->base + reg);
}
-static void rz_ssi_reg_mask_setl(struct rz_ssi_priv __iomem *priv, uint reg,
+static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg,
u32 bclr, u32 bset)
{
u32 val;
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 07/31] ASoC: sh: rz-ssi: Fix wrong operator used issue
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (5 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 06/31] ASoC: sh: rz-ssi: Fix dereference of noderef expression warning Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 08/31] ASoC: sh: rz-ssi: Improve error handling in rz_ssi_dma_request function Lad Prabhakar
` (23 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 1b5d1d3a2f77250707225509cadc17997bab4353 upstream.
Fix wrong operator used issue reported by Coverity by replacing |
operator with & operator.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reported-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210816182336.29959-1-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
sound/soc/sh/rz-ssi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index d96c1bea047c..341815476244 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -368,7 +368,7 @@ static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
/* Wait for idle */
timeout = 100;
while (--timeout) {
- if (rz_ssi_reg_readl(ssi, SSISR) | SSISR_IIRQ)
+ if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ)
break;
udelay(1);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 08/31] ASoC: sh: rz-ssi: Improve error handling in rz_ssi_dma_request function
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (6 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 07/31] ASoC: sh: rz-ssi: Fix wrong operator used issue Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 09/31] dt-bindings: iio: adc: Add binding documentation for Renesas RZ/G2L A/D converter Lad Prabhakar
` (22 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 4b14f17912052a6963580dfba04781cfe6ccba02 upstream.
dma_request_chan() returns error pointer in case of failures, but
the rz_ssi_dma_request() checked for NULL pointer instead.
This patch fixes the issue by checking for ERR_PTR() instead of
NULL and sets the DMA pointers to NULL in error case so that ssi
can fallback to PIO mode.
Fixes: 26ac471c5354 ("ASoC: sh: rz-ssi: Add SSI DMAC support")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210818101450.15948-1-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
sound/soc/sh/rz-ssi.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index 341815476244..89c7e5e4cbf6 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -185,7 +185,7 @@ rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi)
{
- return (ssi->playback.dma_ch || ssi->capture.dma_ch);
+ return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch));
}
static int rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
@@ -676,15 +676,26 @@ static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi)
static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev)
{
ssi->playback.dma_ch = dma_request_chan(dev, "tx");
+ if (IS_ERR(ssi->playback.dma_ch))
+ ssi->playback.dma_ch = NULL;
+
ssi->capture.dma_ch = dma_request_chan(dev, "rx");
+ if (IS_ERR(ssi->capture.dma_ch))
+ ssi->capture.dma_ch = NULL;
+
if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) {
ssi->playback.dma_ch = dma_request_chan(dev, "rt");
- if (!ssi->playback.dma_ch)
+ if (IS_ERR(ssi->playback.dma_ch)) {
+ ssi->playback.dma_ch = NULL;
goto no_dma;
+ }
ssi->dma_rt = true;
}
+ if (!rz_ssi_is_dma_enabled(ssi))
+ goto no_dma;
+
if (ssi->playback.dma_ch &&
(rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0))
goto no_dma;
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 09/31] dt-bindings: iio: adc: Add binding documentation for Renesas RZ/G2L A/D converter
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (7 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 08/31] ASoC: sh: rz-ssi: Improve error handling in rz_ssi_dma_request function Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 10/31] iio: adc: Add driver " Lad Prabhakar
` (21 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 08080963162740abdd8a35f6c3aad0e744f71627 upstream.
Add binding documentation for Renesas RZ/G2L A/D converter block.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210804202118.25745-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/iio/adc/renesas,rzg2l-adc.yaml | 134 ++++++++++++++++++
1 file changed, 134 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
new file mode 100644
index 000000000000..c80201d6a716
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L ADC
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description: |
+ A/D Converter block is a successive approximation analog-to-digital converter
+ with a 12-bit accuracy. Up to eight analog input channels can be selected.
+ Conversions can be performed in single or repeat mode. Result of the ADC is
+ stored in a 32-bit data register corresponding to each channel.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-adc # RZ/G2{L,LC}
+ - const: renesas,rzg2l-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: converter clock
+ - description: peripheral clock
+
+ clock-names:
+ items:
+ - const: adclk
+ - const: pclk
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: presetn
+ - const: adrst-n
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
+
+patternProperties:
+ "^channel@[0-7]$":
+ $ref: "adc.yaml"
+ type: object
+ description: |
+ Represents the external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ The channel number. It can have up to 8 channels numbered from 0 to 7.
+ items:
+ - minimum: 0
+ maximum: 7
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ adc: adc@10059000 {
+ compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
+ reg = <0x10059000 0x400>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
+ <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_ADC_PRESETN>,
+ <&cpg R9A07G044_ADC_ADRST_N>;
+ reset-names = "presetn", "adrst-n";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ };
+ channel@4 {
+ reg = <4>;
+ };
+ channel@5 {
+ reg = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 10/31] iio: adc: Add driver for Renesas RZ/G2L A/D converter
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (8 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 09/31] dt-bindings: iio: adc: Add binding documentation for Renesas RZ/G2L A/D converter Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-30 11:00 ` Pavel Machek
2021-12-29 10:15 ` [PATCH 5.10.y-cip 11/31] iio: adc: rzg2l_adc: Fix -EBUSY timeout error return Lad Prabhakar
` (20 subsequent siblings)
30 siblings, 1 reply; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit d484c21bacfa8bd2fa9fc26393ec59108f508c4c upstream.
Add ADC driver support for Renesas RZ/G2L A/D converter in SW
trigger mode.
A/D Converter block is a successive approximation analog-to-digital
converter with a 12-bit accuracy and supports a maximum of 8 input
channels.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210804202118.25745-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[PL: Dropped read_label callback]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
MAINTAINERS | 8 +
drivers/iio/adc/Kconfig | 10 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/rzg2l_adc.c | 589 ++++++++++++++++++++++++++++++++++++
4 files changed, 608 insertions(+)
create mode 100644 drivers/iio/adc/rzg2l_adc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 591b401f4fbe..c0d2a2cfcfd6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14941,6 +14941,14 @@ L: linux-renesas-soc@vger.kernel.org
S: Maintained
F: drivers/phy/renesas/phy-rcar-gen3-usb*.c
+RENESAS RZ/G2L A/D DRIVER
+M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+L: linux-iio@vger.kernel.org
+L: linux-renesas-soc@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
+F: drivers/iio/adc/rzg2l_adc.c
+
RESET CONTROLLER FRAMEWORK
M: Philipp Zabel <p.zabel@pengutronix.de>
S: Maintained
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index e39b679126a2..dfa5e1d2a0ca 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -876,6 +876,16 @@ config ROCKCHIP_SARADC
To compile this driver as a module, choose M here: the
module will be called rockchip_saradc.
+config RZG2L_ADC
+ tristate "Renesas RZ/G2L ADC driver"
+ depends on ARCH_R9A07G044 || COMPILE_TEST
+ help
+ Say yes here to build support for the ADC found in Renesas
+ RZ/G2L family.
+
+ To compile this driver as a module, choose M here: the
+ module will be called rzg2l_adc.
+
config SC27XX_ADC
tristate "Spreadtrum SC27xx series PMICs ADC"
depends on MFD_SC27XX_PMIC || COMPILE_TEST
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 90f94ada7b30..9c106945e2e4 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o
obj-$(CONFIG_RCAR_GYRO_ADC) += rcar-gyroadc.o
obj-$(CONFIG_RN5T618_ADC) += rn5t618-adc.o
obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
+obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o
obj-$(CONFIG_SPEAR_ADC) += spear_adc.o
obj-$(CONFIG_STX104) += stx104.o
diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
new file mode 100644
index 000000000000..919108d798ba
--- /dev/null
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -0,0 +1,589 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L A/D Converter driver
+ *
+ * Copyright (c) 2021 Renesas Electronics Europe GmbH
+ *
+ * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/iio/iio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#define DRIVER_NAME "rzg2l-adc"
+
+#define RZG2L_ADM(n) ((n) * 0x4)
+#define RZG2L_ADM0_ADCE BIT(0)
+#define RZG2L_ADM0_ADBSY BIT(1)
+#define RZG2L_ADM0_PWDWNB BIT(2)
+#define RZG2L_ADM0_SRESB BIT(15)
+#define RZG2L_ADM1_TRG BIT(0)
+#define RZG2L_ADM1_MS BIT(2)
+#define RZG2L_ADM1_BS BIT(4)
+#define RZG2L_ADM1_EGA_MASK GENMASK(13, 12)
+#define RZG2L_ADM2_CHSEL_MASK GENMASK(7, 0)
+#define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24)
+#define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16)
+#define RZG2L_ADM3_ADCMP_E FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, 0xe)
+#define RZG2L_ADM3_ADSMP_MASK GENMASK(15, 0)
+
+#define RZG2L_ADINT 0x20
+#define RZG2L_ADINT_INTEN_MASK GENMASK(7, 0)
+#define RZG2L_ADINT_CSEEN BIT(16)
+#define RZG2L_ADINT_INTS BIT(31)
+
+#define RZG2L_ADSTS 0x24
+#define RZG2L_ADSTS_CSEST BIT(16)
+#define RZG2L_ADSTS_INTST_MASK GENMASK(7, 0)
+
+#define RZG2L_ADIVC 0x28
+#define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0)
+#define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4)
+
+#define RZG2L_ADFIL 0x2c
+
+#define RZG2L_ADCR(n) (0x30 + ((n) * 0x4))
+#define RZG2L_ADCR_AD_MASK GENMASK(11, 0)
+
+#define RZG2L_ADSMP_DEFUALT_SAMPLING 0x578
+
+#define RZG2L_ADC_MAX_CHANNELS 8
+#define RZG2L_ADC_CHN_MASK 0x7
+#define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4)
+
+struct rzg2l_adc_data {
+ const struct iio_chan_spec *channels;
+ u8 num_channels;
+};
+
+struct rzg2l_adc {
+ void __iomem *base;
+ struct clk *pclk;
+ struct clk *adclk;
+ struct reset_control *presetn;
+ struct reset_control *adrstn;
+ struct completion completion;
+ const struct rzg2l_adc_data *data;
+ struct mutex lock;
+ u16 last_val[RZG2L_ADC_MAX_CHANNELS];
+};
+
+static const char * const rzg2l_adc_channel_name[] = {
+ "adc0",
+ "adc1",
+ "adc2",
+ "adc3",
+ "adc4",
+ "adc5",
+ "adc6",
+ "adc7",
+};
+
+static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
+{
+ return readl(adc->base + reg);
+}
+
+static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
+{
+ writel(val, adc->base + reg);
+}
+
+static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)
+{
+ u32 reg;
+
+ reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
+ if (on)
+ reg |= RZG2L_ADM0_PWDWNB;
+ else
+ reg &= ~RZG2L_ADM0_PWDWNB;
+ rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
+ udelay(2);
+}
+
+static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)
+{
+ int timeout = 5;
+ u32 reg;
+
+ reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
+ if (start)
+ reg |= RZG2L_ADM0_ADCE;
+ else
+ reg &= ~RZG2L_ADM0_ADCE;
+ rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
+
+ if (start)
+ return;
+
+ do {
+ usleep_range(100, 200);
+ reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
+ timeout--;
+ if (!timeout) {
+ pr_err("%s stopping ADC timed out\n", __func__);
+ break;
+ }
+ } while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE)));
+}
+
+static void rzg2l_set_trigger(struct rzg2l_adc *adc)
+{
+ u32 reg;
+
+ /*
+ * Setup ADM1 for SW trigger
+ * EGA[13:12] - Set 00 to indicate hardware trigger is invalid
+ * BS[4] - Enable 1-buffer mode
+ * MS[1] - Enable Select mode
+ * TRG[0] - Enable software trigger mode
+ */
+ reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
+ reg &= ~RZG2L_ADM1_EGA_MASK;
+ reg &= ~RZG2L_ADM1_BS;
+ reg &= ~RZG2L_ADM1_TRG;
+ reg |= RZG2L_ADM1_MS;
+ rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
+}
+
+static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
+{
+ u32 reg;
+
+ if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
+ return -EBUSY;
+
+ rzg2l_set_trigger(adc);
+
+ /* Select analog input channel subjected to conversion. */
+ reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
+ reg &= ~RZG2L_ADM2_CHSEL_MASK;
+ reg |= BIT(ch);
+ rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
+
+ /*
+ * Setup ADINT
+ * INTS[31] - Select pulse signal
+ * CSEEN[16] - Enable channel select error interrupt
+ * INTEN[7:0] - Select channel interrupt
+ */
+ reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
+ reg &= ~RZG2L_ADINT_INTS;
+ reg &= ~RZG2L_ADINT_INTEN_MASK;
+ reg |= (RZG2L_ADINT_CSEEN | BIT(ch));
+ rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
+
+ return 0;
+}
+
+static int rzg2l_adc_set_power(struct iio_dev *indio_dev, bool on)
+{
+ struct device *dev = indio_dev->dev.parent;
+
+ if (on)
+ return pm_runtime_resume_and_get(dev);
+
+ return pm_runtime_put_sync(dev);
+}
+
+static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
+{
+ int ret;
+
+ ret = rzg2l_adc_set_power(indio_dev, true);
+ if (ret)
+ return ret;
+
+ ret = rzg2l_adc_conversion_setup(adc, ch);
+ if (ret) {
+ rzg2l_adc_set_power(indio_dev, false);
+ return ret;
+ }
+
+ reinit_completion(&adc->completion);
+
+ rzg2l_adc_start_stop(adc, true);
+
+ if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
+ rzg2l_adc_writel(adc, RZG2L_ADINT,
+ rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK);
+ rzg2l_adc_start_stop(adc, false);
+ rzg2l_adc_set_power(indio_dev, false);
+ return -ETIMEDOUT;
+ }
+
+ return rzg2l_adc_set_power(indio_dev, false);
+}
+
+static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ struct rzg2l_adc *adc = iio_priv(indio_dev);
+ int ret;
+ u8 ch;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ if (chan->type != IIO_VOLTAGE)
+ return -EINVAL;
+
+ mutex_lock(&adc->lock);
+ ch = chan->channel & RZG2L_ADC_CHN_MASK;
+ ret = rzg2l_adc_conversion(indio_dev, adc, ch);
+ if (ret) {
+ mutex_unlock(&adc->lock);
+ return ret;
+ }
+ *val = adc->last_val[ch];
+ mutex_unlock(&adc->lock);
+
+ return IIO_VAL_INT;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct iio_info rzg2l_adc_iio_info = {
+ .read_raw = rzg2l_adc_read_raw,
+};
+
+static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
+{
+ struct rzg2l_adc *adc = dev_id;
+ unsigned long intst;
+ u32 reg;
+ int ch;
+
+ reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);
+
+ /* A/D conversion channel select error interrupt */
+ if (reg & RZG2L_ADSTS_CSEST) {
+ rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
+ return IRQ_HANDLED;
+ }
+
+ intst = reg & RZG2L_ADSTS_INTST_MASK;
+ if (!intst)
+ return IRQ_NONE;
+
+ for_each_set_bit(ch, &intst, RZG2L_ADC_MAX_CHANNELS)
+ adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
+
+ /* clear the channel interrupt */
+ rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
+
+ complete(&adc->completion);
+
+ return IRQ_HANDLED;
+}
+
+static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
+{
+ struct iio_chan_spec *chan_array;
+ struct fwnode_handle *fwnode;
+ struct rzg2l_adc_data *data;
+ unsigned int channel;
+ int num_channels;
+ int ret;
+ u8 i;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ num_channels = device_get_child_node_count(&pdev->dev);
+ if (!num_channels) {
+ dev_err(&pdev->dev, "no channel children\n");
+ return -ENODEV;
+ }
+
+ if (num_channels > RZG2L_ADC_MAX_CHANNELS) {
+ dev_err(&pdev->dev, "num of channel children out of range\n");
+ return -EINVAL;
+ }
+
+ chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array),
+ GFP_KERNEL);
+ if (!chan_array)
+ return -ENOMEM;
+
+ i = 0;
+ device_for_each_child_node(&pdev->dev, fwnode) {
+ ret = fwnode_property_read_u32(fwnode, "reg", &channel);
+ if (ret)
+ return ret;
+
+ if (channel >= RZG2L_ADC_MAX_CHANNELS)
+ return -EINVAL;
+
+ chan_array[i].type = IIO_VOLTAGE;
+ chan_array[i].indexed = 1;
+ chan_array[i].channel = channel;
+ chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
+ chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel];
+ i++;
+ }
+
+ data->num_channels = num_channels;
+ data->channels = chan_array;
+ adc->data = data;
+
+ return 0;
+}
+
+static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)
+{
+ int timeout = 5;
+ u32 reg;
+ int ret;
+
+ ret = clk_prepare_enable(adc->pclk);
+ if (ret)
+ return ret;
+
+ /* SW reset */
+ reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
+ reg |= RZG2L_ADM0_SRESB;
+ rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
+
+ while (!(rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_SRESB)) {
+ if (!timeout) {
+ ret = -EBUSY;
+ goto exit_hw_init;
+ }
+ timeout--;
+ usleep_range(100, 200);
+ }
+
+ /* Only division by 4 can be set */
+ reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
+ reg &= ~RZG2L_ADIVC_DIVADC_MASK;
+ reg |= RZG2L_ADIVC_DIVADC_4;
+ rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
+
+ /*
+ * Setup AMD3
+ * ADIL[31:24] - Should be always set to 0
+ * ADCMP[23:16] - Should be always set to 0xe
+ * ADSMP[15:0] - Set default (0x578) sampling period
+ */
+ reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
+ reg &= ~RZG2L_ADM3_ADIL_MASK;
+ reg &= ~RZG2L_ADM3_ADCMP_MASK;
+ reg &= ~RZG2L_ADM3_ADSMP_MASK;
+ reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFUALT_SAMPLING);
+ rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
+
+exit_hw_init:
+ clk_disable_unprepare(adc->pclk);
+
+ return 0;
+}
+
+static void rzg2l_adc_pm_runtime_disable(void *data)
+{
+ struct device *dev = data;
+
+ pm_runtime_disable(dev->parent);
+}
+
+static void rzg2l_adc_pm_runtime_set_suspended(void *data)
+{
+ struct device *dev = data;
+
+ pm_runtime_set_suspended(dev->parent);
+}
+
+static void rzg2l_adc_reset_assert(void *data)
+{
+ reset_control_assert(data);
+}
+
+static int rzg2l_adc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iio_dev *indio_dev;
+ struct rzg2l_adc *adc;
+ int ret;
+ int irq;
+
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ adc = iio_priv(indio_dev);
+
+ ret = rzg2l_adc_parse_properties(pdev, adc);
+ if (ret)
+ return ret;
+
+ mutex_init(&adc->lock);
+
+ adc->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(adc->base))
+ return PTR_ERR(adc->base);
+
+ adc->pclk = devm_clk_get(dev, "pclk");
+ if (IS_ERR(adc->pclk)) {
+ dev_err(dev, "Failed to get pclk");
+ return PTR_ERR(adc->pclk);
+ }
+
+ adc->adclk = devm_clk_get(dev, "adclk");
+ if (IS_ERR(adc->adclk)) {
+ dev_err(dev, "Failed to get adclk");
+ return PTR_ERR(adc->adclk);
+ }
+
+ adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n");
+ if (IS_ERR(adc->adrstn)) {
+ dev_err(dev, "failed to get adrstn\n");
+ return PTR_ERR(adc->adrstn);
+ }
+
+ adc->presetn = devm_reset_control_get_exclusive(dev, "presetn");
+ if (IS_ERR(adc->presetn)) {
+ dev_err(dev, "failed to get presetn\n");
+ return PTR_ERR(adc->presetn);
+ }
+
+ ret = reset_control_deassert(adc->adrstn);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(&pdev->dev,
+ rzg2l_adc_reset_assert, adc->adrstn);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = reset_control_deassert(adc->presetn);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(&pdev->dev,
+ rzg2l_adc_reset_assert, adc->presetn);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = rzg2l_adc_hw_init(adc);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret);
+ return ret;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(dev, "no irq resource\n");
+ return irq;
+ }
+
+ ret = devm_request_irq(dev, irq, rzg2l_adc_isr,
+ 0, dev_name(dev), adc);
+ if (ret < 0)
+ return ret;
+
+ init_completion(&adc->completion);
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ indio_dev->name = DRIVER_NAME;
+ indio_dev->info = &rzg2l_adc_iio_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = adc->data->channels;
+ indio_dev->num_channels = adc->data->num_channels;
+
+ pm_runtime_set_suspended(dev);
+ ret = devm_add_action_or_reset(&pdev->dev,
+ rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev);
+ if (ret)
+ return ret;
+
+ pm_runtime_enable(dev);
+ ret = devm_add_action_or_reset(&pdev->dev,
+ rzg2l_adc_pm_runtime_disable, &indio_dev->dev);
+ if (ret)
+ return ret;
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static const struct of_device_id rzg2l_adc_match[] = {
+ { .compatible = "renesas,rzg2l-adc",},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_adc_match);
+
+static int __maybe_unused rzg2l_adc_pm_runtime_suspend(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct rzg2l_adc *adc = iio_priv(indio_dev);
+
+ rzg2l_adc_pwr(adc, false);
+ clk_disable_unprepare(adc->adclk);
+ clk_disable_unprepare(adc->pclk);
+
+ return 0;
+}
+
+static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct rzg2l_adc *adc = iio_priv(indio_dev);
+ int ret;
+
+ ret = clk_prepare_enable(adc->pclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(adc->adclk);
+ if (ret)
+ return ret;
+
+ rzg2l_adc_pwr(adc, true);
+
+ return 0;
+}
+
+static const struct dev_pm_ops rzg2l_adc_pm_ops = {
+ SET_RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend,
+ rzg2l_adc_pm_runtime_resume,
+ NULL)
+};
+
+static struct platform_driver rzg2l_adc_driver = {
+ .probe = rzg2l_adc_probe,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = rzg2l_adc_match,
+ .pm = &rzg2l_adc_pm_ops,
+ },
+};
+
+module_platform_driver(rzg2l_adc_driver);
+
+MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");
+MODULE_LICENSE("GPL v2");
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 5.10.y-cip 10/31] iio: adc: Add driver for Renesas RZ/G2L A/D converter
2021-12-29 10:15 ` [PATCH 5.10.y-cip 10/31] iio: adc: Add driver " Lad Prabhakar
@ 2021-12-30 11:00 ` Pavel Machek
2021-12-30 13:39 ` Prabhakar Mahadev Lad
0 siblings, 1 reply; 42+ messages in thread
From: Pavel Machek @ 2021-12-30 11:00 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 1828 bytes --]
Hi!
> commit d484c21bacfa8bd2fa9fc26393ec59108f508c4c upstream.
>
> Add ADC driver support for Renesas RZ/G2L A/D converter in SW
> trigger mode.
>
> A/D Converter block is a successive approximation analog-to-digital
> converter with a 12-bit accuracy and supports a maximum of 8 input
> channels.
>
> new file mode 100644
> index 000000000000..919108d798ba
> --- /dev/null
> +++ b/drivers/iio/adc/rzg2l_adc.c
...
> +
> +#define RZG2L_ADSMP_DEFUALT_SAMPLING 0x578
> +
This should be "DEFAULT".
> + do {
> + usleep_range(100, 200);
> + reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
> + timeout--;
> + if (!timeout) {
> + pr_err("%s stopping ADC timed out\n", __func__);
> + break;
> + }
> + } while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE)));
> +}
I'd write this as (reg & (RZG2L_ADM0_ADBSY | RZG2L_ADM0_ADCE)). Note
that we wait, then check for timeout without using the register
values. Which is strange and basically makes timeout one tick
lower. (But probably does not matter much).
> +static void rzg2l_set_trigger(struct rzg2l_adc *adc)
> +{
> + u32 reg;
> +
> + /*
> + * Setup ADM1 for SW trigger
> + * EGA[13:12] - Set 00 to indicate hardware trigger is invalid
> + * BS[4] - Enable 1-buffer mode
> + * MS[1] - Enable Select mode
> + * TRG[0] - Enable software trigger mode
> + */
> + reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
> + reg &= ~RZG2L_ADM1_EGA_MASK;
> + reg &= ~RZG2L_ADM1_BS;
> + reg &= ~RZG2L_ADM1_TRG;
reg &= ~(RZG2L_ADM1_EGA_MASK | RZG2L_ADM1_BS | ...) would be usual way
to write this. You can use it in more than one place in the file.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH 5.10.y-cip 10/31] iio: adc: Add driver for Renesas RZ/G2L A/D converter
2021-12-30 11:00 ` Pavel Machek
@ 2021-12-30 13:39 ` Prabhakar Mahadev Lad
0 siblings, 0 replies; 42+ messages in thread
From: Prabhakar Mahadev Lad @ 2021-12-30 13:39 UTC (permalink / raw)
To: Pavel Machek; +Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu, Biju Das
Hi Pavel,
Thank you for the review.
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 30 December 2021 11:01
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 10/31] iio: adc: Add driver for Renesas RZ/G2L A/D converter
>
> Hi!
>
> > commit d484c21bacfa8bd2fa9fc26393ec59108f508c4c upstream.
> >
> > Add ADC driver support for Renesas RZ/G2L A/D converter in SW trigger
> > mode.
> >
> > A/D Converter block is a successive approximation analog-to-digital
> > converter with a 12-bit accuracy and supports a maximum of 8 input
> > channels.
> >
> > new file mode 100644
> > index 000000000000..919108d798ba
> > --- /dev/null
> > +++ b/drivers/iio/adc/rzg2l_adc.c
> ...
> > +
> > +#define RZG2L_ADSMP_DEFUALT_SAMPLING 0x578
> > +
>
> This should be "DEFAULT".
>
Agreed.
> > + do {
> > + usleep_range(100, 200);
> > + reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
> > + timeout--;
> > + if (!timeout) {
> > + pr_err("%s stopping ADC timed out\n", __func__);
> > + break;
> > + }
> > + } while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE))); }
>
> I'd write this as (reg & (RZG2L_ADM0_ADBSY | RZG2L_ADM0_ADCE)). Note that we wait, then check for
> timeout without using the register values. Which is strange and basically makes timeout one tick
> lower. (But probably does not matter much).
>
Agreed.
> > +static void rzg2l_set_trigger(struct rzg2l_adc *adc) {
> > + u32 reg;
> > +
> > + /*
> > + * Setup ADM1 for SW trigger
> > + * EGA[13:12] - Set 00 to indicate hardware trigger is invalid
> > + * BS[4] - Enable 1-buffer mode
> > + * MS[1] - Enable Select mode
> > + * TRG[0] - Enable software trigger mode
> > + */
> > + reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
> > + reg &= ~RZG2L_ADM1_EGA_MASK;
> > + reg &= ~RZG2L_ADM1_BS;
> > + reg &= ~RZG2L_ADM1_TRG;
>
> reg &= ~(RZG2L_ADM1_EGA_MASK | RZG2L_ADM1_BS | ...) would be usual way to write this. You can use it
> in more than one place in the file.
>
Agreed.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 5.10.y-cip 11/31] iio: adc: rzg2l_adc: Fix -EBUSY timeout error return
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (9 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 10/31] iio: adc: Add driver " Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 12/31] iio: adc: rzg2l_adc: add missing clk_disable_unprepare() in rzg2l_adc_pm_runtime_resume() Lad Prabhakar
` (19 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Colin Ian King <colin.king@canonical.com>
commit 9909a395e9807aa79145c9289d0c13d0133359a2 upstream.
Currently when a timeout occurs in rzg2l_adc_hw_init the error -EBUSY is
assigned to ret but the error code is used as the function is hard-coded
to return 0. The variable ret is 0 before entering the while-loop hence
the fix is just to return ret at the end of the function to return the
success 0 or -EBUSY return code.
Addresses-Coverity: ("Unused value")
Fixes: d484c21bacfa ("iio: adc: Add driver for Renesas RZ/G2L A/D converter")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210817172111.495897-1-colin.king@canonical.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/iio/adc/rzg2l_adc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index 919108d798ba..6472170be9d1 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -390,7 +390,7 @@ static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)
exit_hw_init:
clk_disable_unprepare(adc->pclk);
- return 0;
+ return ret;
}
static void rzg2l_adc_pm_runtime_disable(void *data)
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 12/31] iio: adc: rzg2l_adc: add missing clk_disable_unprepare() in rzg2l_adc_pm_runtime_resume()
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (10 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 11/31] iio: adc: rzg2l_adc: Fix -EBUSY timeout error return Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 13/31] clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries Lad Prabhakar
` (18 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Yang Yingliang <yangyingliang@huawei.com>
commit fa002b364981b49d04e818abbc06fd47a5ec7b51 upstream.
Add clk_disable_unprepare() on error path in rzg2l_adc_pm_runtime_resume().
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210819132416.175644-1-yangyingliang@huawei.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/iio/adc/rzg2l_adc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index 6472170be9d1..e2cf11cb7495 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -559,8 +559,10 @@ static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev)
return ret;
ret = clk_prepare_enable(adc->adclk);
- if (ret)
+ if (ret) {
+ clk_disable_unprepare(adc->pclk);
return ret;
+ }
rzg2l_adc_pwr(adc, true);
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 13/31] clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (11 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 12/31] iio: adc: rzg2l_adc: add missing clk_disable_unprepare() in rzg2l_adc_pm_runtime_resume() Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 14/31] clk: renesas: r9a07g044: Add clock and reset entries for ADC Lad Prabhakar
` (17 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit d520af345189c04095bdd256d3601864601ac562 upstream.
Add SSIF-2 clock and reset entries in CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210702135010.5937-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0c45cad4ee65..f1e0be50283f 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -97,6 +97,22 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
0x52c, 0),
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
0x52c, 1),
+ DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
+ 0x570, 0),
+ DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
+ 0x570, 1),
+ DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
+ 0x570, 2),
+ DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
+ 0x570, 3),
+ DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
+ 0x570, 4),
+ DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
+ 0x570, 5),
+ DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
+ 0x570, 6),
+ DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
+ 0x570, 7),
DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
0x578, 0),
DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
@@ -137,6 +153,10 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
+ DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
+ DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
+ DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
+ DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 14/31] clk: renesas: r9a07g044: Add clock and reset entries for ADC
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (12 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 13/31] clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 15/31] arm64: dts: renesas: r9a07g044: Add ADC node Lad Prabhakar
` (16 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 1b87d5bba32c1f25a12ba0625546e5375e3f998d upstream.
Add clock and reset entries for ADC block in CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719085840.21842-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index f1e0be50283f..4c94b94c4125 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -145,6 +145,10 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
0x594, 0),
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
0x598, 0),
+ DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
+ 0x5a8, 0),
+ DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
+ 0x5a8, 1),
};
static struct rzg2l_reset r9a07g044_resets[] = {
@@ -176,6 +180,8 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
+ DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
+ DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
};
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 15/31] arm64: dts: renesas: r9a07g044: Add ADC node
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (13 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 14/31] clk: renesas: r9a07g044: Add clock and reset entries for ADC Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 16/31] arm64: dts: renesas: r9a07g044: Add external audio clock nodes Lad Prabhakar
` (15 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit b3f894354aa08eb853044a7f5029dbdfc7f3b792 upstream.
Add ADC node to R9A07G044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210804202118.25745-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 6eefba96f5c7..2fa29d81c2a7 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -218,6 +218,48 @@
status = "disabled";
};
+ adc: adc@10059000 {
+ compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
+ reg = <0 0x10059000 0 0x400>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
+ <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
+ clock-names = "adclk", "pclk";
+ resets = <&cpg R9A07G044_ADC_PRESETN>,
+ <&cpg R9A07G044_ADC_ADRST_N>;
+ reset-names = "presetn", "adrst-n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ };
+ channel@4 {
+ reg = <4>;
+ };
+ channel@5 {
+ reg = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 16/31] arm64: dts: renesas: r9a07g044: Add external audio clock nodes
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (14 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 15/31] arm64: dts: renesas: r9a07g044: Add ADC node Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 17/31] arm64: dts: renesas: r9a07g044: Add SSI support Lad Prabhakar
` (14 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 6f48272f11b1863e652530b7171a54fc9b24e275 upstream.
Add external audio clocks nodes to RZ/G2L (a.k.a R9A07G044) SoC DTSI.
The external audio clocks are configured as 0 Hz fixed frequency clocks by
default. Boards that provide audio clocks should override them.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210814135526.15561-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 2fa29d81c2a7..d6bbd7c5a5bf 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -13,6 +13,20 @@
#address-cells = <2>;
#size-cells = <2>;
+ audio_clk1: audio_clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio_clk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 17/31] arm64: dts: renesas: r9a07g044: Add SSI support
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (15 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 16/31] arm64: dts: renesas: r9a07g044: Add external audio clock nodes Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 18/31] arm64: dts: renesas: r9a07g044: Add DMA support to SSI Lad Prabhakar
` (13 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 92a341315afc9cc8e015fa201610d8dd73db4a01 upstream.
Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210814135526.15561-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 76 ++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index d6bbd7c5a5bf..49f579856f14 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -92,6 +92,82 @@
#size-cells = <2>;
ranges;
+ ssi0: ssi@10049c00 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x10049c00 0 0x400>;
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi1: ssi@1004a000 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a000 0 0x400>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@1004a400 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a400 0 0x400>;
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@1004a800 {
+ compatible = "renesas,r9a07g044-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x1004a800 0 0x400>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+ clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
+ <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 18/31] arm64: dts: renesas: r9a07g044: Add DMA support to SSI
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (16 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 17/31] arm64: dts: renesas: r9a07g044: Add SSI support Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 19/31] arm64: dts: renesas: rzg2l-smarc: Enable I2C{0,1,3} support Lad Prabhakar
` (12 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 89fe8d246a26a1a60e658a58e5099a90e4d56f6f upstream.
Add dmac phandles to SSI nodes to support DMA operation.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210921084605.16250-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 49f579856f14..4d4a23367529 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -106,6 +106,8 @@
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
+ dmas = <&dmac 0x2655>, <&dmac 0x2656>;
+ dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
@@ -125,6 +127,8 @@
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
+ dmas = <&dmac 0x2659>, <&dmac 0x265a>;
+ dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
@@ -144,6 +148,8 @@
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
+ dmas = <&dmac 0x265f>;
+ dma-names = "rt";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
@@ -163,6 +169,8 @@
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
+ dmas = <&dmac 0x2661>, <&dmac 0x2662>;
+ dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 19/31] arm64: dts: renesas: rzg2l-smarc: Enable I2C{0,1,3} support
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (17 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 18/31] arm64: dts: renesas: r9a07g044: Add DMA support to SSI Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 20/31] arm64: dts: renesas: rzg2l-smarc: Add WM8978 sound codec Lad Prabhakar
` (11 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 04637e2f73d1e77dc00aa046b4845af5fe7e7cef upstream.
Enable I2C{0,1,3} support on RZ/G2L SMARC EVK.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210920182955.13445-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 39 ++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 7ecd4a3f4175..8ecc5b45fc99 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -11,6 +11,9 @@
/ {
aliases {
serial0 = &scif0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c3 = &i2c3;
};
chosen {
@@ -45,6 +48,27 @@
status = "okay";
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
&ohci0 {
dr_mode = "otg";
status = "okay";
@@ -59,6 +83,21 @@
};
&pinctrl {
+ i2c0_pins: i2c0 {
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ input-enable;
+ };
+
+ i2c1_pins: i2c1 {
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ input-enable;
+ };
+
+ i2c3_pins: i2c3 {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
+ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
+ };
+
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 20/31] arm64: dts: renesas: rzg2l-smarc: Add WM8978 sound codec
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (18 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 19/31] arm64: dts: renesas: rzg2l-smarc: Enable I2C{0,1,3} support Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 21/31] arm64: dts: renesas: rzg2l-smarc: Enable audio Lad Prabhakar
` (10 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 1c8da81cc452075a21d4654f88264df8e8e89676 upstream.
Add WM8978 sound codec node to RZ/G2L SMARC EVK.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210921084605.16250-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 8ecc5b45fc99..85fd6dbabff2 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -65,8 +65,15 @@
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
+ clock-frequency = <400000>;
status = "okay";
+
+ wm8978: codec@1a {
+ compatible = "wlf,wm8978";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
+ };
};
&ohci0 {
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 21/31] arm64: dts: renesas: rzg2l-smarc: Enable audio
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (19 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 20/31] arm64: dts: renesas: rzg2l-smarc: Add WM8978 sound codec Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-30 11:02 ` Pavel Machek
2021-12-29 10:15 ` [PATCH 5.10.y-cip 22/31] arm64: dts: renesas: rzg2l-smarc: Add Mic routing Lad Prabhakar
` (9 subsequent siblings)
30 siblings, 1 reply; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit e396d6103343ff95874444bd8a67f031eafe0e38 upstream.
Enable audio on RZ/G2L SMARC EVK by linking SSI0 with WM8978
audio CODEC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210921084605.16250-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 66 ++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 85fd6dbabff2..1791c21dfe74 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -8,6 +8,19 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+/*
+ * SSI-WM8978
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer cset name='Left Input Mixer L2 Switch' on
+ * amixer cset name='Right Input Mixer R2 Switch' on
+ * amixer cset name='Headphone Playback Volume' 100
+ * amixer cset name='PCM Volume' 100%
+ * amixer cset name='Input PGA Volume' 25
+ *
+ */
+
/ {
aliases {
serial0 = &scif0;
@@ -21,6 +34,29 @@
stdout-path = "serial0:115200n8";
};
+ audio_mclock: audio_mclock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ snd_rzg2l: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&cpu_dai>;
+ simple-audio-card,frame-master = <&cpu_dai>;
+ simple-audio-card,mclk-fs = <256>;
+
+ cpu_dai: simple-audio-card,cpu {
+ sound-dai = <&ssi0>;
+ };
+
+ codec_dai: simple-audio-card,codec {
+ clocks = <&audio_mclock>;
+ sound-dai = <&wm8978>;
+ };
+ };
+
usb0_vbus_otg: regulator-usb0-vbus-otg {
compatible = "regulator-fixed";
@@ -30,6 +66,14 @@
};
};
+&audio_clk1{
+ clock-frequency = <11289600>;
+};
+
+&audio_clk2{
+ clock-frequency = <12288000>;
+};
+
&ehci0 {
dr_mode = "otg";
status = "okay";
@@ -90,6 +134,9 @@
};
&pinctrl {
+ pinctrl-0 = <&sound_clk_pins>;
+ pinctrl-names = "default";
+
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
@@ -110,6 +157,18 @@
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
+ sound_clk_pins: sound_clk {
+ pins = "AUDIO_CLK1", "AUDIO_CLK2";
+ input-enable;
+ };
+
+ ssi0_pins: ssi0 {
+ pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
+ <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
+ <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
+ <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
+ };
+
usb0_pins: usb0 {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
@@ -128,6 +187,13 @@
status = "okay";
};
+&ssi0 {
+ pinctrl-0 = <&ssi0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 5.10.y-cip 21/31] arm64: dts: renesas: rzg2l-smarc: Enable audio
2021-12-29 10:15 ` [PATCH 5.10.y-cip 21/31] arm64: dts: renesas: rzg2l-smarc: Enable audio Lad Prabhakar
@ 2021-12-30 11:02 ` Pavel Machek
2021-12-30 13:40 ` Prabhakar Mahadev Lad
0 siblings, 1 reply; 42+ messages in thread
From: Pavel Machek @ 2021-12-30 11:02 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 1195 bytes --]
Hi!
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> commit e396d6103343ff95874444bd8a67f031eafe0e38 upstream.
>
> Enable audio on RZ/G2L SMARC EVK by linking SSI0 with WM8978
> audio CODEC.
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> @@ -8,6 +8,19 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>
> +/*
> + * SSI-WM8978
> + *
> + * This command is required when Playback/Capture
> + *
> + * amixer cset name='Left Input Mixer L2 Switch' on
> + * amixer cset name='Right Input Mixer R2 Switch' on
> + * amixer cset name='Headphone Playback Volume' 100
> + * amixer cset name='PCM Volume' 100%
> + * amixer cset name='Input PGA Volume' 25
"These commands are required for Playback/Capture".
> @@ -30,6 +66,14 @@
> };
> };
>
> +&audio_clk1{
> + clock-frequency = <11289600>;
> +};
> +
> +&audio_clk2{
> + clock-frequency = <12288000>;
> +};
> +
I'd expect spaces before {. (And yes, I'm picking nits here).
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH 5.10.y-cip 21/31] arm64: dts: renesas: rzg2l-smarc: Enable audio
2021-12-30 11:02 ` Pavel Machek
@ 2021-12-30 13:40 ` Prabhakar Mahadev Lad
0 siblings, 0 replies; 42+ messages in thread
From: Prabhakar Mahadev Lad @ 2021-12-30 13:40 UTC (permalink / raw)
To: Pavel Machek; +Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu, Biju Das
Hi Pavel,
Thank you for the review.
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 30 December 2021 11:02
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 21/31] arm64: dts: renesas: rzg2l-smarc: Enable audio
>
> Hi!
>
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > commit e396d6103343ff95874444bd8a67f031eafe0e38 upstream.
> >
> > Enable audio on RZ/G2L SMARC EVK by linking SSI0 with WM8978 audio
> > CODEC.
>
> > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
> > @@ -8,6 +8,19 @@
> > #include <dt-bindings/gpio/gpio.h>
> > #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> >
> > +/*
> > + * SSI-WM8978
> > + *
> > + * This command is required when Playback/Capture
> > + *
> > + * amixer cset name='Left Input Mixer L2 Switch' on
> > + * amixer cset name='Right Input Mixer R2 Switch' on
> > + * amixer cset name='Headphone Playback Volume' 100
> > + * amixer cset name='PCM Volume' 100%
> > + * amixer cset name='Input PGA Volume' 25
>
> "These commands are required for Playback/Capture".
>
Will fix that.
> > @@ -30,6 +66,14 @@
> > };
> > };
> >
> > +&audio_clk1{
> > + clock-frequency = <11289600>;
> > +};
> > +
> > +&audio_clk2{
> > + clock-frequency = <12288000>;
> > +};
> > +
>
> I'd expect spaces before {. (And yes, I'm picking nits here).
>
Ditto.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 5.10.y-cip 22/31] arm64: dts: renesas: rzg2l-smarc: Add Mic routing
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (20 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 21/31] arm64: dts: renesas: rzg2l-smarc: Enable audio Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 23/31] arm64: dts: renesas: rzg2l-smarc-som: Move extal and memory nodes to SOM DTSI Lad Prabhakar
` (8 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 87b1e27af4c1e3422bb2189b5f8f72075e841d6f upstream.
Add audio routing for Mic with bias to reduce noise when doing
audio capture.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210921084605.16250-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 1791c21dfe74..39e05169aaaa 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -47,6 +47,12 @@
simple-audio-card,frame-master = <&cpu_dai>;
simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets = "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "L2", "Mic Bias",
+ "R2", "Mic Bias",
+ "Mic Bias", "Microphone Jack";
+
cpu_dai: simple-audio-card,cpu {
sound-dai = <&ssi0>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 23/31] arm64: dts: renesas: rzg2l-smarc-som: Move extal and memory nodes to SOM DTSI
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (21 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 22/31] arm64: dts: renesas: rzg2l-smarc: Add Mic routing Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 24/31] arm64: dts: renesas: rzg2l-smarc-som: Enable ADC on SMARC platform Lad Prabhakar
` (7 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 55c6826119f64be75c4b423a0092a8c1353a7a81 upstream.
Move extal and memory nodes to SOM DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922212049.19851-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 7 +------
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 18 ++++++++++++++++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 4 ----
3 files changed, 19 insertions(+), 10 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
index d3f72ec62f03..247b0b3f1b58 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -7,15 +7,10 @@
/dts-v1/;
#include "r9a07g044l2.dtsi"
+#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc.dtsi"
/ {
model = "Renesas SMARC EVK based on r9a07g044l2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
-
- memory@48000000 {
- device_type = "memory";
- /* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x78000000>;
- };
};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
new file mode 100644
index 000000000000..0748f2e7396a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC SOM common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/ {
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 39e05169aaaa..e895f6e7fa28 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -89,10 +89,6 @@
status = "okay";
};
-&extal_clk {
- clock-frequency = <24000000>;
-};
-
&hsusb {
dr_mode = "otg";
status = "okay";
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 24/31] arm64: dts: renesas: rzg2l-smarc-som: Enable ADC on SMARC platform
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (22 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 23/31] arm64: dts: renesas: rzg2l-smarc-som: Move extal and memory nodes to SOM DTSI Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 25/31] arm64: dts: renesas: rzg2l-smarc: Enable CANFD Lad Prabhakar
` (6 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 03f7d78e8850ddb8cb1e623ef93e9018e4049ad7 upstream.
Enable the ADC which is present on RZ/G2L SMARC SOM.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922212049.19851-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 0748f2e7396a..da1ee2206e1a 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2021 Renesas Electronics Corp.
*/
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
/ {
memory@48000000 {
device_type = "memory";
@@ -13,6 +15,21 @@
};
};
+&adc {
+ pinctrl-0 = <&adc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /delete-node/ channel@6;
+ /delete-node/ channel@7;
+};
+
&extal_clk {
clock-frequency = <24000000>;
};
+
+&pinctrl {
+ adc_pins: adc {
+ pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 25/31] arm64: dts: renesas: rzg2l-smarc: Enable CANFD
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (23 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 24/31] arm64: dts: renesas: rzg2l-smarc-som: Enable ADC on SMARC platform Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 26/31] arm64: defconfig: Enable SOUND_SOC_RZ Lad Prabhakar
` (5 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 7ae09309c324120b145224789102e730a98950d5 upstream.
Enable CANFD on RZ/G2L SMARC platform.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210924102338.11595-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 40 ++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index e895f6e7fa28..a02784fab46a 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -80,6 +80,20 @@
clock-frequency = <12288000>;
};
+&canfd {
+ pinctrl-0 = <&can0_pins &can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
&ehci0 {
dr_mode = "otg";
status = "okay";
@@ -139,6 +153,32 @@
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
+ can0_pins: can0 {
+ pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
+ <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
+ };
+
+ /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
+ can0-stb {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can0_stb";
+ };
+
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
+ <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
+ };
+
+ /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
+ can1-stb {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can1_stb";
+ };
+
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 26/31] arm64: defconfig: Enable SOUND_SOC_RZ
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (24 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 25/31] arm64: dts: renesas: rzg2l-smarc: Enable CANFD Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 27/31] arm64: defconfig: Enable SND_SOC_WM8978 Lad Prabhakar
` (4 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit be15aa5cc14f94b520c13ab3540fdf7e735bff47 upstream.
Enable sound driver support for Renesas RZ/G2L based platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210920093905.10878-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index afc696d94c89..6cd2171308af 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -707,6 +707,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
CONFIG_SND_SOC_SAMSUNG=y
CONFIG_SND_SOC_RCAR=m
+CONFIG_SND_SOC_RZ=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SOC_TEGRA=m
CONFIG_SND_SOC_TEGRA210_AHUB=m
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 27/31] arm64: defconfig: Enable SND_SOC_WM8978
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (25 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 26/31] arm64: defconfig: Enable SOUND_SOC_RZ Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 28/31] arm64: defconfig: Enable RZG2L_ADC Lad Prabhakar
` (3 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 3c158ec884d8d75526594c888997cabc3223f521 upstream.
WM8978 audio CODEC is supported on RZ/G2L SMARC EVK.
Enable it on arm64 defconfig as module.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210920093905.10878-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied the changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6cd2171308af..c9b0874a541e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -723,6 +723,7 @@ CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_SND_SOC_WCD934X=m
CONFIG_SND_SOC_WM8904=m
+CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WSA881X=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 28/31] arm64: defconfig: Enable RZG2L_ADC
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (26 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 27/31] arm64: defconfig: Enable SND_SOC_WM8978 Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 29/31] clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical Lad Prabhakar
` (2 subsequent siblings)
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 93207e415d134e6fbcee6a723ab4cf060ef3926e upstream.
Enable ADC driver support for Renesas RZ/G2L based platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210927193551.22422-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9b0874a541e..edf32d432541 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -975,6 +975,7 @@ CONFIG_EXYNOS_ADC=y
CONFIG_MAX9611=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_ROCKCHIP_SARADC=m
+CONFIG_RZG2L_ADC=m
CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
CONFIG_IIO_CROS_EC_LIGHT_PROX=m
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 29/31] clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (27 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 28/31] arm64: defconfig: Enable RZG2L_ADC Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 30/31] i2c: riic: Add RZ/G2L support Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 31/31] arm64: defconfig: Enable RIIC Lad Prabhakar
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 664bb2e45b89cd8213e3c9772713323f75e21892 upstream.
Add IA55_CLK and DMAC_ACLK as critical clocks.
Previously it worked ok, because of a bug in clock status function
and the following patch in this series fixes the original bug.
Fixes: c3e67ad6f5a2 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions")
Fixes: eb829e549ba6 ("clk: renesas: r9a07g044: Add DMAC clocks/resets")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922112405.26413-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 4c94b94c4125..1490446985e2 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -186,6 +186,8 @@ static struct rzg2l_reset r9a07g044_resets[] = {
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
+ MOD_CLK_BASE + R9A07G044_IA55_CLK,
+ MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
};
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 30/31] i2c: riic: Add RZ/G2L support
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (28 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 29/31] clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
2021-12-29 10:15 ` [PATCH 5.10.y-cip 31/31] arm64: defconfig: Enable RIIC Lad Prabhakar
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 010e765b406f8e08685ea5b687c63a5ea234719a upstream.
RZ/G2L i2c controller is compatible with RZ/A i2c controller.
By default IP is in reset state, so need to perform release
reset before accessing any register.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/i2c/busses/i2c-riic.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 4eccc0f69861..78b84445ee6a 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -42,8 +42,10 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/reset.h>
#define RIIC_ICCR1 0x00
#define RIIC_ICCR2 0x04
@@ -86,6 +88,11 @@
#define RIIC_INIT_MSG -1
+enum riic_type {
+ RIIC_RZ_A,
+ RIIC_RZ_G2L,
+};
+
struct riic_dev {
void __iomem *base;
u8 *buf;
@@ -395,7 +402,9 @@ static int riic_i2c_probe(struct platform_device *pdev)
struct i2c_adapter *adap;
struct resource *res;
struct i2c_timings i2c_t;
+ struct reset_control *rstc;
int i, ret;
+ enum riic_type type;
riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
if (!riic)
@@ -412,6 +421,17 @@ static int riic_i2c_probe(struct platform_device *pdev)
return PTR_ERR(riic->clk);
}
+ type = (enum riic_type)of_device_get_match_data(&pdev->dev);
+ if (type == RIIC_RZ_G2L) {
+ rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(rstc)) {
+ dev_err(&pdev->dev, "Error: missing reset ctrl\n");
+ return PTR_ERR(rstc);
+ }
+
+ reset_control_deassert(rstc);
+ }
+
for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
if (!res)
@@ -472,7 +492,8 @@ static int riic_i2c_remove(struct platform_device *pdev)
}
static const struct of_device_id riic_i2c_dt_ids[] = {
- { .compatible = "renesas,riic-rz" },
+ { .compatible = "renesas,riic-r9a07g044", .data = (void *)RIIC_RZ_G2L },
+ { .compatible = "renesas,riic-rz", .data = (void *)RIIC_RZ_A },
{ /* Sentinel */ },
};
--
2.17.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH 5.10.y-cip 31/31] arm64: defconfig: Enable RIIC
2021-12-29 10:14 [PATCH 5.10.y-cip 00/31] Add sound/adc support for RZ/G2L Lad Prabhakar
` (29 preceding siblings ...)
2021-12-29 10:15 ` [PATCH 5.10.y-cip 30/31] i2c: riic: Add RZ/G2L support Lad Prabhakar
@ 2021-12-29 10:15 ` Lad Prabhakar
30 siblings, 0 replies; 42+ messages in thread
From: Lad Prabhakar @ 2021-12-29 10:15 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
commit df364a82bf5b2dc2d78212c53205bbb91e40f850 upstream.
Enable RIIC driver support for Renesas RZ/G2L based platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210611165624.30749-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index edf32d432541..0957b725eb1b 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -443,6 +443,7 @@ CONFIG_I2C_PXA=y
CONFIG_I2C_QCOM_CCI=m
CONFIG_I2C_QCOM_GENI=m
CONFIG_I2C_QUP=y
+CONFIG_I2C_RIIC=y
CONFIG_I2C_RK3X=y
CONFIG_I2C_SH_MOBILE=y
CONFIG_I2C_TEGRA=y
--
2.17.1
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