[PATCH 5.10.y-cip 00/24] RZ/G2L Fixes from mainline

[PATCH 5.10.y-cip 00/24] RZ/G2L Fixes from mainline

[Biju Das]

This patch series are backported from Mainline for supporting
future SoCs as well as various bugs and improvements related to
RZ/g2L SMARC EVK Platform.

All these patches are cherry-picked from mainline.

Biju Das (6):
  dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC
  soc: renesas: Identify RZ/V2L SoC
  soc: renesas: Add support for reading product revision for RZ/G2L
    family
  ASoC: sh: Make SND_SOC_RZ depend on ARCH_RZG2L
  dt-bindings: dma: rz-dmac: Document RZ/V2L SoC
  arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions

Geert Uytterhoeven (2):
  soc: renesas: Consolidate product register handling
  arm64: dts: renesas: Fix pin controller node names

Heiner Kallweit (2):
  reset: renesas: Fix Runtime PM usage
  reset: renesas: Check return value of reset_control_deassert()

Jialin Zhang (1):
  iio: adc: rzg2l_adc: add missing fwnode_handle_put() in
    rzg2l_adc_parse_properties()

Lad Prabhakar (12):
  soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS
    configs
  soc: renesas: Kconfig: Introduce ARCH_RZG2L config option
  iio: adc: Kconfig: Make RZG2L_ADC depend on ARCH_RZG2L
  dmaengine: sh: Kconfig: Add ARCH_R9A07G054 dependency for RZ_DMAC
    config option
  dmaengine: sh: Kconfig: Make RZ_DMAC depend on ARCH_RZG2L
  reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add description for
    power-source property
  ASoC: sh: rz-ssi: Drop SSIFSR_TDC and SSIFSR_RDC macros
  ASoC: sh: rz-ssi: Propagate error codes returned from
    platform_get_irq_byname()
  ASoC: sh: rz-ssi: Release the DMA channels in rz_ssi_probe() error
    path
  iio: adc: rzg2l_adc: Fix typo
  i2c: riic: Simplify reset handling

Xu Wang (1):
  iio: adc: rzg2l_adc: Remove unnecessary print function dev_err()

 .../bindings/dma/renesas,rz-dmac.yaml         |   3 +-
 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   1 +
 .../bindings/power/renesas,rzg2l-sysc.yaml    |   7 +-
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |   2 +-
 .../boot/dts/renesas/r9a07g044l2-smarc.dts    |   1 +
 .../dts/renesas/rzg2l-smarc-pinfunction.dtsi  | 137 ++++++++++++++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  | 127 -------------
 drivers/dma/sh/Kconfig                        |   6 +-
 drivers/i2c/busses/i2c-riic.c                 |  34 ++--
 drivers/iio/adc/Kconfig                       |   2 +-
 drivers/iio/adc/rzg2l_adc.c                   |  16 +-
 drivers/reset/Kconfig                         |   2 +-
 drivers/reset/reset-rzg2l-usbphy-ctrl.c       |  11 +-
 drivers/soc/renesas/Kconfig                   |  12 ++
 drivers/soc/renesas/renesas-soc.c             | 173 ++++++++++--------
 sound/soc/sh/Kconfig                          |   2 +-
 sound/soc/sh/rz-ssi.c                         |  24 +--
 17 files changed, 309 insertions(+), 251 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi

-- 
2.25.1

[PATCH 5.10.y-cip 01/24] soc: renesas: Consolidate product register handling

[Biju Das]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 05b22caa7490e4f4c94bbde33c61cf72d187b8f7 upstream.

Currently renesas_soc_init() scans the whole device tree up to three
times, to find a device node describing a product register.
Furthermore, the product register handling for the different variants is
very similar, with the major difference being the location of the
product bitfield inside the product register.

Reduce scanning to a single pass using of_find_matching_node_and_match()
instead.  Switch to a common handling of product registers, by storing
the intrinsics of each product register type in the data field of the
corresponding match entry.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/057721f46c7499de4133135488f0f3da7fb39265.1636570669.git.geert+renesas@glider.be
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/soc/renesas/renesas-soc.c | 115 +++++++++++++++---------------
 1 file changed, 56 insertions(+), 59 deletions(-)

diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 8310fce7714e..95d5e7063ef4 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -317,94 +317,92 @@ static const struct of_device_id renesas_socs[] __initconst = {
 	{ /* sentinel */ }
 };
 
+struct renesas_id {
+	unsigned int offset;
+	u32 mask;
+};
+
+static const struct renesas_id id_bsid __initconst = {
+	.offset = 0,
+	.mask = 0xff0000,
+	/*
+	 * TODO: Upper 4 bits of BSID are for chip version, but the format is
+	 * not known at this time so we don't know how to specify eshi and eslo
+	 */
+};
+
+static const struct renesas_id id_rzg2l __initconst = {
+	.offset = 0xa04,
+	.mask = 0xfffffff,
+};
+
+static const struct renesas_id id_prr __initconst = {
+	.offset = 0,
+	.mask = 0xff00,
+};
+
+static const struct of_device_id renesas_ids[] __initconst = {
+	{ .compatible = "renesas,bsid",			.data = &id_bsid },
+	{ .compatible = "renesas,r9a07g044-sysc",	.data = &id_rzg2l },
+	{ .compatible = "renesas,prr",			.data = &id_prr },
+	{ /* sentinel */ }
+};
+
 static int __init renesas_soc_init(void)
 {
 	struct soc_device_attribute *soc_dev_attr;
+	unsigned int product, eshi = 0, eslo;
 	const struct renesas_family *family;
 	const struct of_device_id *match;
 	const struct renesas_soc *soc;
+	const struct renesas_id *id;
 	void __iomem *chipid = NULL;
 	struct soc_device *soc_dev;
 	struct device_node *np;
-	unsigned int product, eshi = 0, eslo;
+	const char *soc_id;
 
 	match = of_match_node(renesas_socs, of_root);
 	if (!match)
 		return -ENODEV;
 
+	soc_id = strchr(match->compatible, ',') + 1;
 	soc = match->data;
 	family = soc->family;
 
-	np = of_find_compatible_node(NULL, NULL, "renesas,bsid");
+	np = of_find_matching_node_and_match(NULL, renesas_ids, &match);
 	if (np) {
+		id = match->data;
 		chipid = of_iomap(np, 0);
 		of_node_put(np);
-
-		if (chipid) {
-			product = readl(chipid);
-			iounmap(chipid);
-
-			if (soc->id && ((product >> 16) & 0xff) != soc->id) {
-				pr_warn("SoC mismatch (product = 0x%x)\n",
-					product);
-				return -ENODEV;
-			}
-		}
-
-		/*
-		 * TODO: Upper 4 bits of BSID are for chip version, but the
-		 * format is not known at this time so we don't know how to
-		 * specify eshi and eslo
-		 */
-
-		goto done;
+	} else if (soc->id && family->reg) {
+		/* Try hardcoded CCCR/PRR fallback */
+		id = &id_prr;
+		chipid = ioremap(family->reg, 4);
 	}
 
-	np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc");
-	if (np) {
-		chipid = of_iomap(np, 0);
-		of_node_put(np);
+	if (chipid) {
+		product = readl(chipid + id->offset);
+		iounmap(chipid);
 
-		if (chipid) {
-			product = readl(chipid + 0x0a04);
-			iounmap(chipid);
+		if (id == &id_prr) {
+			/* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */
+			if ((product & 0x7fff) == 0x5210)
+				product ^= 0x11;
+			/* R-Car M3-W ES1.3 incorrectly identifies as ES2.1 */
+			if ((product & 0x7fff) == 0x5211)
+				product ^= 0x12;
 
-			if (soc->id && (product & 0xfffffff) != soc->id) {
-				pr_warn("SoC mismatch (product = 0x%x)\n",
-					product);
-				return -ENODEV;
-			}
+			eshi = ((product >> 4) & 0x0f) + 1;
+			eslo = product & 0xf;
 		}
 
-		goto done;
-	}
-
-	/* Try PRR first, then hardcoded fallback */
-	np = of_find_compatible_node(NULL, NULL, "renesas,prr");
-	if (np) {
-		chipid = of_iomap(np, 0);
-		of_node_put(np);
-	} else if (soc->id && family->reg) {
-		chipid = ioremap(family->reg, 4);
-	}
-	if (chipid) {
-		product = readl(chipid);
-		iounmap(chipid);
-		/* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */
-		if ((product & 0x7fff) == 0x5210)
-			product ^= 0x11;
-		/* R-Car M3-W ES1.3 incorrectly identifies as ES2.1 */
-		if ((product & 0x7fff) == 0x5211)
-			product ^= 0x12;
-		if (soc->id && ((product >> 8) & 0xff) != soc->id) {
+		if (soc->id &&
+		    ((product & id->mask) >> __ffs(id->mask)) != soc->id) {
 			pr_warn("SoC mismatch (product = 0x%x)\n", product);
 			return -ENODEV;
 		}
-		eshi = ((product >> 4) & 0x0f) + 1;
-		eslo = product & 0xf;
 	}
 
-done:
 	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 	if (!soc_dev_attr)
 		return -ENOMEM;
@@ -414,8 +412,7 @@ static int __init renesas_soc_init(void)
 	of_node_put(np);
 
 	soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
-	soc_dev_attr->soc_id = kstrdup_const(strchr(match->compatible, ',') + 1,
-					     GFP_KERNEL);
+	soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL);
 	if (eshi)
 		soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi,
 						   eslo);
-- 
2.25.1

Re: [PATCH 5.10.y-cip 01/24] soc: renesas: Consolidate product register handling

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 1657 bytes --]

Hi!

> From: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> commit 05b22caa7490e4f4c94bbde33c61cf72d187b8f7 upstream.
> 
> Currently renesas_soc_init() scans the whole device tree up to three
> times, to find a device node describing a product register.
> Furthermore, the product register handling for the different variants is
> very similar, with the major difference being the location of the
> product bitfield inside the product register.
> 
> Reduce scanning to a single pass using of_find_matching_node_and_match()
> instead.  Switch to a common handling of product registers, by storing
> the intrinsics of each product register type in the data field of the
> corresponding match entry.
>
...

> +static const struct of_device_id renesas_ids[] __initconst = {
> +	{ .compatible = "renesas,bsid",			.data = &id_bsid },
> +	{ .compatible = "renesas,r9a07g044-sysc",	.data = &id_rzg2l },
> +	{ .compatible = "renesas,prr",			.data = &id_prr },
> +	{ /* sentinel */ }
> +};
> +


>  	match = of_match_node(renesas_socs, of_root);
>  	if (!match)
>  		return -ENODEV;
>  
> +	soc_id = strchr(match->compatible, ',') + 1;
>  	soc = match->data;
>  	family = soc->family;
>

This is quite tricky code. ',' will always be in the compatible with
the current table, but if this ever changes, it will crash. I would
not mind something like.

	soc_id = strchr(match->compatible, ',');
	if (!soc_id)
	        return -EIO;
	soc_id++;

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

RE: [PATCH 5.10.y-cip 01/24] soc: renesas: Consolidate product register handling

[Biju Das]

Hi Pavel,

Thanks for the feedback.

> Subject: Re: [PATCH 5.10.y-cip 01/24] soc: renesas: Consolidate product
> register handling
> 
> Hi!
> 
> > From: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > commit 05b22caa7490e4f4c94bbde33c61cf72d187b8f7 upstream.
> >
> > Currently renesas_soc_init() scans the whole device tree up to three
> > times, to find a device node describing a product register.
> > Furthermore, the product register handling for the different variants
> > is very similar, with the major difference being the location of the
> > product bitfield inside the product register.
> >
> > Reduce scanning to a single pass using
> > of_find_matching_node_and_match() instead.  Switch to a common
> > handling of product registers, by storing the intrinsics of each
> > product register type in the data field of the corresponding match
> entry.
> >
> ...
> 
> > +static const struct of_device_id renesas_ids[] __initconst = {
> > +	{ .compatible = "renesas,bsid",			.data = &id_bsid },
> > +	{ .compatible = "renesas,r9a07g044-sysc",	.data = &id_rzg2l },
> > +	{ .compatible = "renesas,prr",			.data = &id_prr },
> > +	{ /* sentinel */ }
> > +};
> > +
> 
> 
> >  	match = of_match_node(renesas_socs, of_root);
> >  	if (!match)
> >  		return -ENODEV;
> >
> > +	soc_id = strchr(match->compatible, ',') + 1;
> >  	soc = match->data;
> >  	family = soc->family;
> >
> 
> This is quite tricky code. ',' will always be in the compatible with the
> current table, but if this ever changes, it will crash. I would not mind
> something like.

I agree it is tricky. But we will never be going to change {vendor},{soc_id}
format for the renesas SoC's in mainline.

Cheers,
Biju

[PATCH 5.10.y-cip 02/24] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC

[Biju Das]

commit 4b4a0fd666303a06bbe159552bc055b490b77cdc upstream.

Add DT binding documentation for the SYSC controller found on the RZ/V2L
SoC.  This SYSC controller is almost identical to the one found on the
RZ/G2L SoC, the only difference being that SYSC on RZ/V2L has an
additional register to control the DRP-AI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220110134659.30424-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml      | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
index 84ddc772b003..bb433e75a0ee 100644
--- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
@@ -4,14 +4,14 @@
 $id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
-title: Renesas RZ/G2L System Controller (SYSC)
+title: Renesas RZ/{G2L,V2L} System Controller (SYSC)
 
 maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
 description:
-  The RZ/G2L System Controller (SYSC) performs system control of the LSI and
-  supports following functions,
+  The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI
+  and supports following functions,
   - External terminal state capture function
   - 34-bit address space access function
   - Low power consumption control
@@ -21,6 +21,7 @@ properties:
   compatible:
     enum:
       - renesas,r9a07g044-sysc # RZ/G2{L,LC}
+      - renesas,r9a07g054-sysc # RZ/V2L
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH 5.10.y-cip 03/24] soc: renesas: Identify RZ/V2L SoC

[Biju Das]

commit 860122d80251c64484883324128ca82fa35423ef upstream.

Add support for identifying the RZ/V2L (R9A07G054) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220110134659.30424-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig       |  5 +++++
 drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 71b44c31b012..bddf91db18fe 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -284,6 +284,11 @@ config ARCH_R9A07G044
 	help
 	  This enables support for the Renesas RZ/G2L SoC variants.
 
+config ARCH_R9A07G054
+	bool "ARM64 Platform support for RZ/V2L"
+	help
+	  This enables support for the Renesas RZ/V2L SoC variants.
+
 endif # ARM64
 
 config RST_RCAR
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 95d5e7063ef4..f06a6a160215 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -60,6 +60,10 @@ static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
 	.name	= "RZ/G2L",
 };
 
+static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
+	.name	= "RZ/V2L",
+};
+
 static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
 	.name	= "SH-Mobile",
 	.reg	= 0xe600101c,		/* CCCR (Common Chip Code Register) */
@@ -140,6 +144,11 @@ static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
 	.id     = 0x841c447,
 };
 
+static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
+	.family = &fam_rzv2l,
+	.id     = 0x8447447,
+};
+
 static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
 	.family	= &fam_rcar_gen1,
 };
@@ -311,6 +320,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
 #if defined(CONFIG_ARCH_R9A07G044)
 	{ .compatible = "renesas,r9a07g044",	.data = &soc_rz_g2l },
 #endif
+#if defined(CONFIG_ARCH_R9A07G054)
+	{ .compatible = "renesas,r9a07g054",	.data = &soc_rz_v2l },
+#endif
 #ifdef CONFIG_ARCH_SH73A0
 	{ .compatible = "renesas,sh73a0",	.data = &soc_shmobile_ag5 },
 #endif
@@ -344,6 +356,7 @@ static const struct renesas_id id_prr __initconst = {
 static const struct of_device_id renesas_ids[] __initconst = {
 	{ .compatible = "renesas,bsid",			.data = &id_bsid },
 	{ .compatible = "renesas,r9a07g044-sysc",	.data = &id_rzg2l },
+	{ .compatible = "renesas,r9a07g054-sysc",	.data = &id_rzg2l },
 	{ .compatible = "renesas,prr",			.data = &id_prr },
 	{ /* sentinel */ }
 };
-- 
2.25.1

[PATCH 5.10.y-cip 04/24] soc: renesas: Add support for reading product revision for RZ/G2L family

[Biju Das]

commit cb5508e47e60b85ac033edd8c52245ad51360eb4 upstream.

As per RZ/G2L HW manual (Rev.1.00 Sep, 2021) DEV_ID [31:28] indicates
product revision. Use this information to populate the revision info
for RZ/G2L family.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220121014117.21248-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/soc/renesas/renesas-soc.c | 55 ++++++++++++++++++-------------
 1 file changed, 33 insertions(+), 22 deletions(-)

diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index f06a6a160215..1ab78deaa239 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -370,9 +370,11 @@ static int __init renesas_soc_init(void)
 	const struct renesas_soc *soc;
 	const struct renesas_id *id;
 	void __iomem *chipid = NULL;
+	const char *rev_prefix = "";
 	struct soc_device *soc_dev;
 	struct device_node *np;
 	const char *soc_id;
+	int ret;
 
 	match = of_match_node(renesas_socs, of_root);
 	if (!match)
@@ -393,6 +395,17 @@ static int __init renesas_soc_init(void)
 		chipid = ioremap(family->reg, 4);
 	}
 
+	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+	if (!soc_dev_attr)
+		return -ENOMEM;
+
+	np = of_find_node_by_path("/");
+	of_property_read_string(np, "model", &soc_dev_attr->machine);
+	of_node_put(np);
+
+	soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
+	soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL);
+
 	if (chipid) {
 		product = readl(chipid + id->offset);
 		iounmap(chipid);
@@ -407,41 +420,39 @@ static int __init renesas_soc_init(void)
 
 			eshi = ((product >> 4) & 0x0f) + 1;
 			eslo = product & 0xf;
+			soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
+							   eshi, eslo);
+		}  else if (id == &id_rzg2l) {
+			eshi =  ((product >> 28) & 0x0f);
+			soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u",
+							   eshi);
+			rev_prefix = "Rev ";
 		}
 
 		if (soc->id &&
 		    ((product & id->mask) >> __ffs(id->mask)) != soc->id) {
 			pr_warn("SoC mismatch (product = 0x%x)\n", product);
-			return -ENODEV;
+			ret = -ENODEV;
+			goto free_soc_dev_attr;
 		}
 	}
 
-	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
-	if (!soc_dev_attr)
-		return -ENOMEM;
-
-	np = of_find_node_by_path("/");
-	of_property_read_string(np, "model", &soc_dev_attr->machine);
-	of_node_put(np);
-
-	soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL);
-	soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL);
-	if (eshi)
-		soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi,
-						   eslo);
-
-	pr_info("Detected Renesas %s %s %s\n", soc_dev_attr->family,
-		soc_dev_attr->soc_id, soc_dev_attr->revision ?: "");
+	pr_info("Detected Renesas %s %s %s%s\n", soc_dev_attr->family,
+		soc_dev_attr->soc_id, rev_prefix, soc_dev_attr->revision ?: "");
 
 	soc_dev = soc_device_register(soc_dev_attr);
 	if (IS_ERR(soc_dev)) {
-		kfree(soc_dev_attr->revision);
-		kfree_const(soc_dev_attr->soc_id);
-		kfree_const(soc_dev_attr->family);
-		kfree(soc_dev_attr);
-		return PTR_ERR(soc_dev);
+		ret = PTR_ERR(soc_dev);
+		goto free_soc_dev_attr;
 	}
 
 	return 0;
+
+free_soc_dev_attr:
+	kfree(soc_dev_attr->revision);
+	kfree_const(soc_dev_attr->soc_id);
+	kfree_const(soc_dev_attr->family);
+	kfree(soc_dev_attr);
+	return ret;
 }
 early_initcall(renesas_soc_init);
-- 
2.25.1

[PATCH 5.10.y-cip 05/24] soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configs

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit b89acaf8cad188d9a1387d3049ae036a10d9a1f3 upstream.

Explicitly select PM and PM_GENERIC_DOMAINS configs for ARCH_R9A07G044
and ARCH_R9A07G054 configs.  PM and PM_GENERIC_DOMAINS configs are
required for RZ/{G2L,V2L} SoC without these configs the SMARC EVK's
won't boot.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220221222450.5393-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index bddf91db18fe..3469021427dd 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -281,11 +281,15 @@ config ARCH_R8A774B1
 
 config ARCH_R9A07G044
 	bool "ARM64 Platform support for RZ/G2L"
+	select PM
+	select PM_GENERIC_DOMAINS
 	help
 	  This enables support for the Renesas RZ/G2L SoC variants.
 
 config ARCH_R9A07G054
 	bool "ARM64 Platform support for RZ/V2L"
+	select PM
+	select PM_GENERIC_DOMAINS
 	help
 	  This enables support for the Renesas RZ/V2L SoC variants.
 
-- 
2.25.1

[PATCH 5.10.y-cip 06/24] soc: renesas: Kconfig: Introduce ARCH_RZG2L config option

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 088659ad2a830124407edc38da278010c95bcc96 upstream.

The Renesas RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L SoCs have identical IP
blocks for which drivers are common.  To avoid updating the Kconfig
files for drivers in common to each SoC, introduce the ARCH_RZG2L config
option.
The ARCH_RZG2L config option will be selected by the above mentioned
SoCs, and the ARCH_RZG2L config option will be used as a dependency for
the drivers in common.

While at it, move PM and PM_GENERIC_DOMAINS under the ARCH_RZG2L config
option insteadĀ of keeping it for individual SoCs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220224092114.25737-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 3469021427dd..cf695f624d79 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -40,6 +40,11 @@ config ARCH_RMOBILE
 	select SYS_SUPPORTS_SH_TMU
 	select SYSC_RMOBILE
 
+config ARCH_RZG2L
+	bool
+	select PM
+	select PM_GENERIC_DOMAINS
+
 config ARCH_RZN1
 	bool
 	select ARM_AMBA
@@ -281,15 +286,13 @@ config ARCH_R8A774B1
 
 config ARCH_R9A07G044
 	bool "ARM64 Platform support for RZ/G2L"
-	select PM
-	select PM_GENERIC_DOMAINS
+	select ARCH_RZG2L
 	help
 	  This enables support for the Renesas RZ/G2L SoC variants.
 
 config ARCH_R9A07G054
 	bool "ARM64 Platform support for RZ/V2L"
-	select PM
-	select PM_GENERIC_DOMAINS
+	select ARCH_RZG2L
 	help
 	  This enables support for the Renesas RZ/V2L SoC variants.
 
-- 
2.25.1

[PATCH 5.10.y-cip 07/24] ASoC: sh: Make SND_SOC_RZ depend on ARCH_RZG2L

[Biju Das]

commit cc691ba94cf8d6c586076ed489bb9d385a2650ad upstream.

The SSI block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so
instead of adding dependency for each SoC's add dependency on ARCH_RZG2L.
The ARCH_RZG2L config option is already selected by ARCH_R9A07G043,
ARCH_R9A07G044 and ARCH_R9A07G054.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220423164443.146299-1-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 sound/soc/sh/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
index f19bd15c0900..96d9d7160f30 100644
--- a/sound/soc/sh/Kconfig
+++ b/sound/soc/sh/Kconfig
@@ -46,7 +46,7 @@ config SND_SOC_RCAR
 
 config SND_SOC_RZ
 	tristate "RZ/G2L series SSIF-2 support"
-	depends on ARCH_R9A07G044 || COMPILE_TEST
+	depends on ARCH_RZG2L || COMPILE_TEST
 	help
 	  This option enables RZ/G2L SSIF-2 sound support.
 
-- 
2.25.1

[PATCH 5.10.y-cip 08/24] iio: adc: Kconfig: Make RZG2L_ADC depend on ARCH_RZG2L

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 024b58a30274a9e28d5c7c17b1ec405714047f2a upstream.

ADC block is common on Renesas RZ/G2L and RZ/V2L SoC's, so instead of
adding dependency for each SoC's add dependency on ARCH_RZG2L. The
ARCH_RZG2L config option is already selected by ARCH_R9A07G044 and
ARCH_R9A07G054.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220406070315.13862-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/iio/adc/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index dfa5e1d2a0ca..cbf3defb0732 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -878,7 +878,7 @@ config ROCKCHIP_SARADC
 
 config RZG2L_ADC
 	tristate "Renesas RZ/G2L ADC driver"
-	depends on ARCH_R9A07G044 || COMPILE_TEST
+	depends on ARCH_RZG2L || COMPILE_TEST
 	help
 	  Say yes here to build support for the ADC found in Renesas
 	  RZ/G2L family.
-- 
2.25.1

[PATCH 5.10.y-cip 09/24] dt-bindings: dma: rz-dmac: Document RZ/V2L SoC

[Biju Das]

commit 12bf2f9f7fdd3709b327fa1a62f63fa6100bc26f upstream.

Document RZ/V2L DMAC bindings. RZ/V2L DMAC is identical to one found on
the RZ/G2L SoC. No driver changes are required as generic compatible
string "renesas,rz-dmac" will be used as a fallback.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220110134659.30424-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index 7a4f415d74dc..e353377084aa 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/G2L DMA Controller
+title: Renesas RZ/{G2L,V2L} DMA Controller
 
 maintainers:
   - Biju Das <biju.das.jz@bp.renesas.com>
@@ -17,6 +17,7 @@ properties:
     items:
       - enum:
           - renesas,r9a07g044-dmac # RZ/G2{L,LC}
+          - renesas,r9a07g054-dmac # RZ/V2L
       - const: renesas,rz-dmac
 
   reg:
-- 
2.25.1

[PATCH 5.10.y-cip 10/24] dmaengine: sh: Kconfig: Add ARCH_R9A07G054 dependency for RZ_DMAC config option

[Biju Das]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="maccentraleurope", Size: 1399 bytes --]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 386fe06c39e843ba1a3274d3cc72fc87835b6cc9 upstream.

RZ/V2L DMA block is identical to one found on RZ/G2L SoC. This patch adds
ARCH_R9A07G054 dependency for RZ_DMAC config option so that the driver
can be enabled on RZ/V2L SoC. While at it, also update config help text.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220221224321.11939-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/dma/sh/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig
index a46296285307..b35d705f79e7 100644
--- a/drivers/dma/sh/Kconfig
+++ b/drivers/dma/sh/Kconfig
@@ -49,10 +49,10 @@ config RENESAS_USB_DMAC
 	  SoCs.
 
 config RZ_DMAC
-	tristate "Renesas RZ/G2L DMA Controller"
-	depends on ARCH_R9A07G044 || COMPILE_TEST
+	tristate "Renesas RZ/{G2L,V2L} DMA Controller"
+	depends on ARCH_R9A07G044 || ARCH_R9A07G054 || COMPILE_TEST
 	select RENESAS_DMA
 	select DMA_VIRTUAL_CHANNELS
 	help
 	  This driver supports the general purpose DMA controller found in the
-	  Renesas RZ/G2L SoC variants.
+	  Renesas RZ/{G2L,V2L} SoC variants.
-- 
2.25.1

[PATCH 5.10.y-cip 11/24] dmaengine: sh: Kconfig: Make RZ_DMAC depend on ARCH_RZG2L

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 448a0994cc698d41d056f14fb9065305b14f3c75 upstream.

The DMAC block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so
instead of adding dependency for each SoC's add dependency on ARCH_RZG2L.
The ARCH_RZG2L config option is already selected by ARCH_R9A07G043,
ARCH_R9A07G044 and ARCH_R9A07G054.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220406080417.14593-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/dma/sh/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig
index b35d705f79e7..c0b2997ab7fd 100644
--- a/drivers/dma/sh/Kconfig
+++ b/drivers/dma/sh/Kconfig
@@ -50,7 +50,7 @@ config RENESAS_USB_DMAC
 
 config RZ_DMAC
 	tristate "Renesas RZ/{G2L,V2L} DMA Controller"
-	depends on ARCH_R9A07G044 || ARCH_R9A07G054 || COMPILE_TEST
+	depends on ARCH_RZG2L || COMPILE_TEST
 	select RENESAS_DMA
 	select DMA_VIRTUAL_CHANNELS
 	help
-- 
2.25.1

[PATCH 5.10.y-cip 12/24] reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 9fe7dd4e94f0bb76ec96224e8813695bdf019fa5 upstream.

The USBPHY Control block is identical on Renesas RZ/G2L and RZ/V2L SoC's,
so instead of adding dependency for each SoC's add dependency on
ARCH_RZG2L. The ARCH_RZG2L config option is already selected by
ARCH_R9A07G044 and ARCH_R9A07G054.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20220406071647.14037-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/reset/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 9a759b0e5a79..a1ecaa3b5ef2 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -156,7 +156,7 @@ config RESET_RASPBERRYPI
 
 config RESET_RZG2L_USBPHY_CTRL
 	tristate "Renesas RZ/G2L USBPHY control driver"
-	depends on ARCH_R9A07G044 || COMPILE_TEST
+	depends on ARCH_RZG2L || COMPILE_TEST
 	help
 	  Support for USBPHY Control found on RZ/G2L family. It mainly
 	  controls reset and power down of the USB/PHY.
-- 
2.25.1

[PATCH 5.10.y-cip 13/24] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add description for power-source property

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 1dcb6b782ff02b966b3ff45c597b8dec56cbc2b2 upstream.

Add description for "power-source" property mentioning the values in
enum are in millivolt.

Suggested-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211222145901.23661-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 3a66fd214c17..83488cd8673d 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -76,6 +76,7 @@ additionalProperties:
         output-impedance-ohms:
           enum: [ 33, 50, 66, 100 ]
         power-source:
+          description: I/O voltage in millivolt.
           enum: [ 1800, 2500, 3300 ]
         slew-rate: true
         gpio-hog: true
-- 
2.25.1

[PATCH 5.10.y-cip 14/24] ASoC: sh: rz-ssi: Drop SSIFSR_TDC and SSIFSR_RDC macros

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 17a1fef58c65ec9c9a15dd60386712567ff28d45 upstream.

The mask values of SSIFSR_TDC and SSIFSR_RDC macros are incorrect and
they are unused in the file so just drop them.

Reported-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220426074922.13319-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 sound/soc/sh/rz-ssi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index 7a9de98b7857..b787a788ad79 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -59,9 +59,7 @@
 #define SSIFSR_RDC_MASK		0x3f
 #define SSIFSR_RDC_SHIFT	8
 
-#define SSIFSR_TDC(x)		(((x) & 0x1f) << 24)
 #define SSIFSR_TDE		BIT(16)
-#define SSIFSR_RDC(x)		(((x) & 0x1f) << 8)
 #define SSIFSR_RDF		BIT(0)
 
 #define SSIOFR_LRCONT		BIT(8)
-- 
2.25.1

[PATCH 5.10.y-cip 15/24] ASoC: sh: rz-ssi: Propagate error codes returned from platform_get_irq_byname()

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 91686a3984f34df0ab844cdbaa7e4d9621129f5d upstream.

Propagate error codes returned from platform_get_irq_byname() instead of
returning -ENODEV. platform_get_irq_byname() may return -EPROBE_DEFER, to
handle such cases propagate the error codes.

While at it drop the dev_err_probe() messages as platform_get_irq_byname()
already does this for us in case of error.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220426074922.13319-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 sound/soc/sh/rz-ssi.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index b787a788ad79..caeb236b8372 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -977,8 +977,7 @@ static int rz_ssi_probe(struct platform_device *pdev)
 	/* Error Interrupt */
 	ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
 	if (ssi->irq_int < 0)
-		return dev_err_probe(&pdev->dev, -ENODEV,
-				     "Unable to get SSI int_req IRQ\n");
+		return ssi->irq_int;
 
 	ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
 			       0, dev_name(&pdev->dev), ssi);
@@ -990,8 +989,7 @@ static int rz_ssi_probe(struct platform_device *pdev)
 		/* Tx and Rx interrupts (pio only) */
 		ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
 		if (ssi->irq_tx < 0)
-			return dev_err_probe(&pdev->dev, -ENODEV,
-					     "Unable to get SSI dma_tx IRQ\n");
+			return ssi->irq_tx;
 
 		ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
 				       &rz_ssi_interrupt, 0,
@@ -1002,8 +1000,7 @@ static int rz_ssi_probe(struct platform_device *pdev)
 
 		ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
 		if (ssi->irq_rx < 0)
-			return dev_err_probe(&pdev->dev, -ENODEV,
-					     "Unable to get SSI dma_rx IRQ\n");
+			return ssi->irq_rx;
 
 		ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
 				       &rz_ssi_interrupt, 0,
-- 
2.25.1

[PATCH 5.10.y-cip 16/24] ASoC: sh: rz-ssi: Release the DMA channels in rz_ssi_probe() error path

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 767e6f26204d3f5406630e86b720d01818b8616d upstream.

DMA channels requested by rz_ssi_dma_request() in rz_ssi_probe() were
never released in the error path apart from one place. This patch fixes
this issue by calling rz_ssi_release_dma_channels() in the error path.

Fixes: 26ac471c5354 ("ASoC: sh: rz-ssi: Add SSI DMAC support")
Reported-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220426074922.13319-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 sound/soc/sh/rz-ssi.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index caeb236b8372..ae57c7aa580e 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -976,14 +976,18 @@ static int rz_ssi_probe(struct platform_device *pdev)
 
 	/* Error Interrupt */
 	ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
-	if (ssi->irq_int < 0)
+	if (ssi->irq_int < 0) {
+		rz_ssi_release_dma_channels(ssi);
 		return ssi->irq_int;
+	}
 
 	ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt,
 			       0, dev_name(&pdev->dev), ssi);
-	if (ret < 0)
+	if (ret < 0) {
+		rz_ssi_release_dma_channels(ssi);
 		return dev_err_probe(&pdev->dev, ret,
 				     "irq request error (int_req)\n");
+	}
 
 	if (!rz_ssi_is_dma_enabled(ssi)) {
 		/* Tx and Rx interrupts (pio only) */
@@ -1011,13 +1015,16 @@ static int rz_ssi_probe(struct platform_device *pdev)
 	}
 
 	ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-	if (IS_ERR(ssi->rstc))
+	if (IS_ERR(ssi->rstc)) {
+		rz_ssi_release_dma_channels(ssi);
 		return PTR_ERR(ssi->rstc);
+	}
 
 	reset_control_deassert(ssi->rstc);
 	pm_runtime_enable(&pdev->dev);
 	ret = pm_runtime_resume_and_get(&pdev->dev);
 	if (ret < 0) {
+		rz_ssi_release_dma_channels(ssi);
 		pm_runtime_disable(ssi->dev);
 		reset_control_assert(ssi->rstc);
 		return dev_err_probe(ssi->dev, ret, "pm_runtime_resume_and_get failed\n");
-- 
2.25.1

Re: [PATCH 5.10.y-cip 16/24] ASoC: sh: rz-ssi: Release the DMA channels in rz_ssi_probe() error path

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 1608 bytes --]

Hi!

> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> commit 767e6f26204d3f5406630e86b720d01818b8616d upstream.
> 
> DMA channels requested by rz_ssi_dma_request() in rz_ssi_probe() were
> never released in the error path apart from one place. This patch fixes
> this issue by calling rz_ssi_release_dma_channels() in the error
> path.

I believe this is correct, but...
> +++ b/sound/soc/sh/rz-ssi.c
> @@ -976,14 +976,18 @@ static int rz_ssi_probe(struct platform_device *pdev)
> -	if (ssi->irq_int < 0)
> +	if (ssi->irq_int < 0) {
> +		rz_ssi_release_dma_channels(ssi);
>  		return ssi->irq_int;
> +	}

> +	if (ret < 0) {
> +		rz_ssi_release_dma_channels(ssi);
>  		return dev_err_probe(&pdev->dev, ret,
>  				     "irq request error (int_req)\n");
> +	}

>  	ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> -	if (IS_ERR(ssi->rstc))
> +	if (IS_ERR(ssi->rstc)) {
> +		rz_ssi_release_dma_channels(ssi);
>  		return PTR_ERR(ssi->rstc);
> +	}

I believe we have enough cases to use "goto cleanup" style to reduce
code duplication.

>  	if (ret < 0) {
> +		rz_ssi_release_dma_channels(ssi);
>  		pm_runtime_disable(ssi->dev);
>  		reset_control_assert(ssi->rstc);
>  		return dev_err_probe(ssi->dev, ret,
> "pm_runtime_resume_and_get failed\n");

Plus, we usually do cleanup in reverse order of init.

Best regards,
                                                        Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

RE: [cip-dev] [PATCH 5.10.y-cip 16/24] ASoC: sh: rz-ssi: Release the DMA channels in rz_ssi_probe() error path

[Biju Das]

Hi Pavel,

Thanks for the feedback.

> Subject: Re: [cip-dev] [PATCH 5.10.y-cip 16/24] ASoC: sh: rz-ssi:
> Release the DMA channels in rz_ssi_probe() error path
> 
> Hi!
> 
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > commit 767e6f26204d3f5406630e86b720d01818b8616d upstream.
> >
> > DMA channels requested by rz_ssi_dma_request() in rz_ssi_probe() were
> > never released in the error path apart from one place. This patch
> > fixes this issue by calling rz_ssi_release_dma_channels() in the error
> > path.
> 
> I believe this is correct, but...
> > +++ b/sound/soc/sh/rz-ssi.c
> > @@ -976,14 +976,18 @@ static int rz_ssi_probe(struct platform_device
> *pdev)
> > -	if (ssi->irq_int < 0)
> > +	if (ssi->irq_int < 0) {
> > +		rz_ssi_release_dma_channels(ssi);
> >  		return ssi->irq_int;
> > +	}
> 
> > +	if (ret < 0) {
> > +		rz_ssi_release_dma_channels(ssi);
> >  		return dev_err_probe(&pdev->dev, ret,
> >  				     "irq request error (int_req)\n");
> > +	}
> 
> >  	ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > -	if (IS_ERR(ssi->rstc))
> > +	if (IS_ERR(ssi->rstc)) {
> > +		rz_ssi_release_dma_channels(ssi);
> >  		return PTR_ERR(ssi->rstc);
> > +	}
> 
> I believe we have enough cases to use "goto cleanup" style to reduce
> code duplication.

OK.

> 
> >  	if (ret < 0) {
> > +		rz_ssi_release_dma_channels(ssi);
> >  		pm_runtime_disable(ssi->dev);
> >  		reset_control_assert(ssi->rstc);
> >  		return dev_err_probe(ssi->dev, ret,
> "pm_runtime_resume_and_get
> > failed\n");
> 
> Plus, we usually do cleanup in reverse order of init.
> 

OK, Will fix this in mainline.

Cheers,
Biju

[PATCH 5.10.y-cip 17/24] iio: adc: rzg2l_adc: Remove unnecessary print function dev_err()

[Biju Das]

From: Xu Wang <vulab@iscas.ac.cn>

commit 471d040defb243e59a2cee42069ca4e8d6d3e94b upstream.

The print function dev_err() is redundant because
platform_get_irq() already prints an error.

Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211105015504.39226-1-vulab@iscas.ac.cn
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/iio/adc/rzg2l_adc.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index e2cf11cb7495..4955a91128c8 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -495,10 +495,8 @@ static int rzg2l_adc_probe(struct platform_device *pdev)
 	}
 
 	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
-		dev_err(dev, "no irq resource\n");
+	if (irq < 0)
 		return irq;
-	}
 
 	ret = devm_request_irq(dev, irq, rzg2l_adc_isr,
 			       0, dev_name(dev), adc);
-- 
2.25.1

[PATCH 5.10.y-cip 18/24] iio: adc: rzg2l_adc: Fix typo

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 2553340bd208cc2e54a9e6a27d948a2b51dbf3a1 upstream.

Fix typo RZG2L_ADSMP_DEFUALT_SAMPLING -> RZG2L_ADSMP_DEFAULT_SAMPLING.

Reported-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Link: https://lore.kernel.org/r/20220107172529.12361-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/iio/adc/rzg2l_adc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index 4955a91128c8..38fccb7bcd65 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -55,7 +55,7 @@
 #define RZG2L_ADCR(n)			(0x30 + ((n) * 0x4))
 #define RZG2L_ADCR_AD_MASK		GENMASK(11, 0)
 
-#define RZG2L_ADSMP_DEFUALT_SAMPLING	0x578
+#define RZG2L_ADSMP_DEFAULT_SAMPLING	0x578
 
 #define RZG2L_ADC_MAX_CHANNELS		8
 #define RZG2L_ADC_CHN_MASK		0x7
@@ -384,7 +384,7 @@ static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)
 	reg &= ~RZG2L_ADM3_ADIL_MASK;
 	reg &= ~RZG2L_ADM3_ADCMP_MASK;
 	reg &= ~RZG2L_ADM3_ADSMP_MASK;
-	reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFUALT_SAMPLING);
+	reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFAULT_SAMPLING);
 	rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
 
 exit_hw_init:
-- 
2.25.1

[PATCH 5.10.y-cip 19/24] iio: adc: rzg2l_adc: add missing fwnode_handle_put() in rzg2l_adc_parse_properties()

[Biju Das]

From: Jialin Zhang <zhangjialin11@huawei.com>

commit d836715f588ea15f905f607c27bc693587058db4 upstream.

fwnode_handle_put() should be used when terminating
device_for_each_child_node() iteration with break or return to prevent
stale device node references from being left behind.

Fixes: d484c21bacfa ("iio: adc: Add driver for Renesas RZ/G2L A/D converter")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220517033526.2035735-1-zhangjialin11@huawei.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/iio/adc/rzg2l_adc.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
index 38fccb7bcd65..b36048d7015d 100644
--- a/drivers/iio/adc/rzg2l_adc.c
+++ b/drivers/iio/adc/rzg2l_adc.c
@@ -323,11 +323,15 @@ static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l
 	i = 0;
 	device_for_each_child_node(&pdev->dev, fwnode) {
 		ret = fwnode_property_read_u32(fwnode, "reg", &channel);
-		if (ret)
+		if (ret) {
+			fwnode_handle_put(fwnode);
 			return ret;
+		}
 
-		if (channel >= RZG2L_ADC_MAX_CHANNELS)
+		if (channel >= RZG2L_ADC_MAX_CHANNELS) {
+			fwnode_handle_put(fwnode);
 			return -EINVAL;
+		}
 
 		chan_array[i].type = IIO_VOLTAGE;
 		chan_array[i].indexed = 1;
-- 
2.25.1

[PATCH 5.10.y-cip 20/24] reset: renesas: Fix Runtime PM usage

[Biju Das]

From: Heiner Kallweit <hkallweit1@gmail.com>

commit 92c959bae2e54ba1e2540ba5f813f7752bd76be1 upstream.

If pm_runtime_resume_and_get() fails then it returns w/o the RPM usage
counter being incremented. In this case call pm_runtime_put() in
remove() will result in a usage counter imbalance. Therefore check the
return code of pm_runtime_resume_and_get() and bail out in case of error.

Fixes: bee08559701f ("reset: renesas: Add RZ/G2L usbphy control driver")
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/ec24e13f-0530-b091-7a08-864577b9b3be@gmail.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/reset/reset-rzg2l-usbphy-ctrl.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
index e0704fd2b533..1e8315038850 100644
--- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -137,7 +137,12 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
 	dev_set_drvdata(dev, priv);
 
 	pm_runtime_enable(&pdev->dev);
-	pm_runtime_resume_and_get(&pdev->dev);
+	error = pm_runtime_resume_and_get(&pdev->dev);
+	if (error < 0) {
+		pm_runtime_disable(&pdev->dev);
+		reset_control_assert(priv->rstc);
+		return dev_err_probe(&pdev->dev, error, "pm_runtime_resume_and_get failed");
+	}
 
 	/* put pll and phy into reset state */
 	spin_lock_irqsave(&priv->lock, flags);
-- 
2.25.1

[PATCH 5.10.y-cip 21/24] reset: renesas: Check return value of reset_control_deassert()

[Biju Das]

From: Heiner Kallweit <hkallweit1@gmail.com>

commit da18980a855edf44270f05455e0ec3f2472f64cc upstream.

Deasserting the reset is vital, therefore bail out in case of error.

Suggested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/b2131908-0110-006b-862f-080517f3e2d8@gmail.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/reset/reset-rzg2l-usbphy-ctrl.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
index 1e8315038850..a8dde4606360 100644
--- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -121,7 +121,9 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
 		return dev_err_probe(dev, PTR_ERR(priv->rstc),
 				     "failed to get reset\n");
 
-	reset_control_deassert(priv->rstc);
+	error = reset_control_deassert(priv->rstc);
+	if (error)
+		return error;
 
 	priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops;
 	priv->rcdev.of_reset_n_cells = 1;
-- 
2.25.1

[PATCH 5.10.y-cip 22/24] i2c: riic: Simplify reset handling

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit da2e86c0bd7bc6fdb116dd03c041cf816205cbdc upstream.

Read reset phandle as optional instead of exclusive so that all the DT's
passing the reset phandle can be used to assert/deassert the reset line.
With this change we don't have to differentiate the RZ/G2L SoC.

With the above changes we no longer need the "renesas,riic-r9a07g044"
compatible string, so drop it from riic_i2c_dt_ids[]. No changes are
required to the r9a07g044.dtsi as we already have "renesas,riic-rz" as a
fallback compatible string.

While at it, check the return code of reset_control_deassert() as it might
fail and also add a devres action to assert the reset line.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 78b84445ee6a..3675ad12d45c 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -88,11 +88,6 @@
 
 #define RIIC_INIT_MSG	-1
 
-enum riic_type {
-	RIIC_RZ_A,
-	RIIC_RZ_G2L,
-};
-
 struct riic_dev {
 	void __iomem *base;
 	u8 *buf;
@@ -396,6 +391,11 @@ static struct riic_irq_desc riic_irqs[] = {
 	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
 };
 
+static void riic_reset_control_assert(void *data)
+{
+	reset_control_assert(data);
+}
+
 static int riic_i2c_probe(struct platform_device *pdev)
 {
 	struct riic_dev *riic;
@@ -404,7 +404,6 @@ static int riic_i2c_probe(struct platform_device *pdev)
 	struct i2c_timings i2c_t;
 	struct reset_control *rstc;
 	int i, ret;
-	enum riic_type type;
 
 	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
 	if (!riic)
@@ -421,16 +420,18 @@ static int riic_i2c_probe(struct platform_device *pdev)
 		return PTR_ERR(riic->clk);
 	}
 
-	type = (enum riic_type)of_device_get_match_data(&pdev->dev);
-	if (type == RIIC_RZ_G2L) {
-		rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-		if (IS_ERR(rstc)) {
-			dev_err(&pdev->dev, "Error: missing reset ctrl\n");
-			return PTR_ERR(rstc);
-		}
+	rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+	if (IS_ERR(rstc))
+		return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
+				     "Error: missing reset ctrl\n");
 
-		reset_control_deassert(rstc);
-	}
+	ret = reset_control_deassert(rstc);
+	if (ret)
+		return ret;
+
+	ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc);
+	if (ret)
+		return ret;
 
 	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
 		res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
@@ -492,8 +493,7 @@ static int riic_i2c_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id riic_i2c_dt_ids[] = {
-	{ .compatible = "renesas,riic-r9a07g044", .data = (void *)RIIC_RZ_G2L },
-	{ .compatible = "renesas,riic-rz", .data = (void *)RIIC_RZ_A },
+	{ .compatible = "renesas,riic-rz", },
 	{ /* Sentinel */ },
 };
 
-- 
2.25.1

[PATCH 5.10.y-cip 23/24] arm64: dts: renesas: Fix pin controller node names

[Biju Das]

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit c9b7011768b5dbb68792b4bacad5ae913059ed74 upstream.

Align all pin controller node names with the expectations of the DT
bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be
[Biju: Manually applied the changes]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 3859337989b7..63bf5bb62554 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -589,7 +589,7 @@ sysc: system-controller@11020000 {
 			status = "disabled";
 		};
 
-		pinctrl: pin-controller@11030000 {
+		pinctrl: pinctrl@11030000 {
 			compatible = "renesas,r9a07g044-pinctrl";
 			reg = <0 0x11030000 0 0x10000>;
 			gpio-controller;
-- 
2.25.1

[PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions

[Biju Das]

commit 65d2bc885b01642bbd0898b8af573783ab84f835 upstream.

RZ/G2L and RZ/G2LC SMARC EVK use the same carrier board, but the pin
mappings between the RZ/G2L and the RZ/G2LC SMARC SoM are different.
Therefore we need to update the carrier board pin definitions based
on the corresponding SoM pin mapping.

Move pinctrl definitions out of the RZ/G2L SMARC common file, so that
we can reuse the common file to support RZ/G2LC SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211216114305.5842-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../boot/dts/renesas/r9a07g044l2-smarc.dts    |   1 +
 .../dts/renesas/rzg2l-smarc-pinfunction.dtsi  | 137 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  | 127 ----------------
 3 files changed, 138 insertions(+), 127 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
index 247b0b3f1b58..886d38886d05 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 #include "r9a07g044l2.dtsi"
 #include "rzg2l-smarc-som.dtsi"
+#include "rzg2l-smarc-pinfunction.dtsi"
 #include "rzg2l-smarc.dtsi"
 
 / {
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
new file mode 100644
index 000000000000..71d83e447670
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC pincontrol parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&pinctrl {
+	pinctrl-0 = <&sound_clk_pins>;
+	pinctrl-names = "default";
+
+	can0_pins: can0 {
+		pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
+			 <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
+	};
+
+	/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
+	can0-stb {
+		gpio-hog;
+		gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "can0_stb";
+	};
+
+	can1_pins: can1 {
+		pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
+			 <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
+	};
+
+	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
+	can1-stb {
+		gpio-hog;
+		gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "can1_stb";
+	};
+
+	i2c0_pins: i2c0 {
+		pins = "RIIC0_SDA", "RIIC0_SCL";
+		input-enable;
+	};
+
+	i2c1_pins: i2c1 {
+		pins = "RIIC1_SDA", "RIIC1_SCL";
+		input-enable;
+	};
+
+	i2c3_pins: i2c3 {
+		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
+			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
+	};
+
+	scif0_pins: scif0 {
+		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
+			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
+	};
+
+	scif2_pins: scif2 {
+		pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
+			 <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
+			 <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
+			 <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
+	};
+
+	sd1-pwr-en-hog {
+		gpio-hog;
+		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "sd1_pwr_en";
+	};
+
+	sdhi1_pins: sd1 {
+		sd1_data {
+			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+			power-source = <3300>;
+		};
+
+		sd1_ctrl {
+			pins = "SD1_CLK", "SD1_CMD";
+			power-source = <3300>;
+		};
+
+		sd1_mux {
+			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
+		};
+	};
+
+	sdhi1_pins_uhs: sd1_uhs {
+		sd1_data_uhs {
+			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+			power-source = <1800>;
+		};
+
+		sd1_ctrl_uhs {
+			pins = "SD1_CLK", "SD1_CMD";
+			power-source = <1800>;
+		};
+
+		sd1_mux_uhs {
+			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
+		};
+	};
+
+	sound_clk_pins: sound_clk {
+		pins = "AUDIO_CLK1", "AUDIO_CLK2";
+		input-enable;
+	};
+
+	spi1_pins: spi1 {
+		pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
+			 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
+			 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
+			 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
+	};
+
+	ssi0_pins: ssi0 {
+		pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
+			 <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
+			 <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
+			 <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
+	};
+
+	usb0_pins: usb0 {
+		pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
+			 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
+			 <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
+	};
+
+	usb1_pins: usb1 {
+		pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
+			 <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
+	};
+};
+
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 6f2a8bdfa225..46abb29718cc 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -162,133 +162,6 @@ &phyrst {
 	status = "okay";
 };
 
-&pinctrl {
-	pinctrl-0 = <&sound_clk_pins>;
-	pinctrl-names = "default";
-
-	can0_pins: can0 {
-		pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
-			 <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
-	};
-
-	/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
-	can0-stb {
-		gpio-hog;
-		gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
-		output-low;
-		line-name = "can0_stb";
-	};
-
-	can1_pins: can1 {
-		pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
-			 <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
-	};
-
-	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
-	can1-stb {
-		gpio-hog;
-		gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
-		output-low;
-		line-name = "can1_stb";
-	};
-
-	i2c0_pins: i2c0 {
-		pins = "RIIC0_SDA", "RIIC0_SCL";
-		input-enable;
-	};
-
-	i2c1_pins: i2c1 {
-		pins = "RIIC1_SDA", "RIIC1_SCL";
-		input-enable;
-	};
-
-	i2c3_pins: i2c3 {
-		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
-			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
-	};
-
-	scif0_pins: scif0 {
-		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
-			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
-	};
-
-	scif2_pins: scif2 {
-		pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
-			 <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
-			 <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
-			 <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
-	};
-
-	sd1-pwr-en-hog {
-		gpio-hog;
-		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "sd1_pwr_en";
-	};
-
-	sdhi1_pins: sd1 {
-		sd1_data {
-			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
-			power-source = <3300>;
-		};
-
-		sd1_ctrl {
-			pins = "SD1_CLK", "SD1_CMD";
-			power-source = <3300>;
-		};
-
-		sd1_mux {
-			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
-		};
-	};
-
-	sdhi1_pins_uhs: sd1_uhs {
-		sd1_data_uhs {
-			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
-			power-source = <1800>;
-		};
-
-		sd1_ctrl_uhs {
-			pins = "SD1_CLK", "SD1_CMD";
-			power-source = <1800>;
-		};
-
-		sd1_mux_uhs {
-			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
-		};
-	};
-
-	sound_clk_pins: sound_clk {
-		pins = "AUDIO_CLK1", "AUDIO_CLK2";
-		input-enable;
-	};
-
-	spi1_pins: spi1 {
-		pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
-			 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
-			 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
-			 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
-	};
-
-	ssi0_pins: ssi0 {
-		pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
-			 <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
-			 <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
-			 <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
-	};
-
-	usb0_pins: usb0 {
-		pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
-			 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
-			 <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
-	};
-
-	usb1_pins: usb1 {
-		pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
-			 <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
-	};
-};
-
 &scif0 {
 	pinctrl-0 = <&scif0_pins>;
 	pinctrl-names = "default";
-- 
2.25.1

Re: [cip-dev] [PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 1025 bytes --]

Hi!
> 
> RZ/G2L and RZ/G2LC SMARC EVK use the same carrier board, but the pin
> mappings between the RZ/G2L and the RZ/G2LC SMARC SoM are different.
> Therefore we need to update the carrier board pin definitions based
> on the corresponding SoM pin mapping.
> 
> Move pinctrl definitions out of the RZ/G2L SMARC common file, so that
> we can reuse the common file to support RZ/G2LC SMARC EVK.
...

This really needs subsequent patches to be useful; plus, git complains
about blank line at EOF. Anyway, I believe we can still take it.

> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
> new file mode 100644
> index 000000000000..71d83e447670
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
> +	};
> +};
> +

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

RE: [cip-dev] [PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions

[Biju Das]

Hi Pavel,

Thanks for the feedback.

> Subject: Re: [cip-dev] [PATCH 5.10.y-cip 24/24] arm64: dts: renesas:
> rzg2l-smarc: Move pinctrl definitions
> 
> Hi!
> >
> > RZ/G2L and RZ/G2LC SMARC EVK use the same carrier board, but the pin
> > mappings between the RZ/G2L and the RZ/G2LC SMARC SoM are different.
> > Therefore we need to update the carrier board pin definitions based on
> > the corresponding SoM pin mapping.
> >
> > Move pinctrl definitions out of the RZ/G2L SMARC common file, so that
> > we can reuse the common file to support RZ/G2LC SMARC EVK.
> ...
> 
> This really needs subsequent patches to be useful; plus, git complains
> about blank line at EOF. Anyway, I believe we can still take it.

Will send support for RZ/G2LC next week. Regarding blank line, Will fix it in mainline.

Cheers,
Biju


> 
> > diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
> > b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
> > new file mode 100644
> > index 000000000000..71d83e447670
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
> > +	};
> > +};
> > +
> 
> Best regards,
> 								Pavel
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Re: [cip-dev] [PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 504 bytes --]

Hi!

> > This really needs subsequent patches to be useful; plus, git complains
> > about blank line at EOF. Anyway, I believe we can still take it.
> 
> Will send support for RZ/G2LC next week. Regarding blank line, Will fix it in mainline.

Thank you. The blank line may be "too trivial" to fix in separate
patch.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

RE: [cip-dev] [PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions

[Biju Das]

Hi Pavel,

> Subject: Re: [cip-dev] [PATCH 5.10.y-cip 24/24] arm64: dts: renesas:
> rzg2l-smarc: Move pinctrl definitions
> 
> Hi!
> 
> > > This really needs subsequent patches to be useful; plus, git
> > > complains about blank line at EOF. Anyway, I believe we can still
> take it.
> >
> > Will send support for RZ/G2LC next week. Regarding blank line, Will
> fix it in mainline.
> 
> Thank you. The blank line may be "too trivial" to fix in separate patch.

Ok, Next time when I get a chance to touch this file. Will fix this as well.

Cheers,
Biju

Re: [PATCH 5.10.y-cip 00/24] RZ/G2L Fixes from mainline

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 485 bytes --]

Hi!

> This patch series are backported from Mainline for supporting
> future SoCs as well as various bugs and improvements related to
> RZ/g2L SMARC EVK Platform.

I made some comments, but nothing serious. I'm currently running
test. If it passes and there are no other comments, I can apply it.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
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RE: [PATCH 5.10.y-cip 00/24] RZ/G2L Fixes from mainline

[nobuhiro1.iwamatsu]

Hi all,

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: Friday, July 15, 2022 4:22 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯Ａ
> ＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> Cc: Chris Paterson <chris.paterson2@renesas.com>; Biju Das
> <biju.das.jz@bp.renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [PATCH 5.10.y-cip 00/24] RZ/G2L Fixes from mainline
> 
> This patch series are backported from Mainline for supporting future SoCs as
> well as various bugs and improvements related to RZ/g2L SMARC EVK
> Platform.
> 
> All these patches are cherry-picked from mainline.
> 
> Biju Das (6):
>   dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC
>   soc: renesas: Identify RZ/V2L SoC
>   soc: renesas: Add support for reading product revision for RZ/G2L
>     family
>   ASoC: sh: Make SND_SOC_RZ depend on ARCH_RZG2L
>   dt-bindings: dma: rz-dmac: Document RZ/V2L SoC
>   arm64: dts: renesas: rzg2l-smarc: Move pinctrl definitions
> 
> Geert Uytterhoeven (2):
>   soc: renesas: Consolidate product register handling
>   arm64: dts: renesas: Fix pin controller node names
> 
> Heiner Kallweit (2):
>   reset: renesas: Fix Runtime PM usage
>   reset: renesas: Check return value of reset_control_deassert()
> 
> Jialin Zhang (1):
>   iio: adc: rzg2l_adc: add missing fwnode_handle_put() in
>     rzg2l_adc_parse_properties()
> 
> Lad Prabhakar (12):
>   soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS
>     configs
>   soc: renesas: Kconfig: Introduce ARCH_RZG2L config option
>   iio: adc: Kconfig: Make RZG2L_ADC depend on ARCH_RZG2L
>   dmaengine: sh: Kconfig: Add ARCH_R9A07G054 dependency for RZ_DMAC
>     config option
>   dmaengine: sh: Kconfig: Make RZ_DMAC depend on ARCH_RZG2L
>   reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on
> ARCH_RZG2L
>   dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add description for
>     power-source property
>   ASoC: sh: rz-ssi: Drop SSIFSR_TDC and SSIFSR_RDC macros
>   ASoC: sh: rz-ssi: Propagate error codes returned from
>     platform_get_irq_byname()
>   ASoC: sh: rz-ssi: Release the DMA channels in rz_ssi_probe() error
>     path
>   iio: adc: rzg2l_adc: Fix typo
>   i2c: riic: Simplify reset handling
> 
> Xu Wang (1):
>   iio: adc: rzg2l_adc: Remove unnecessary print function dev_err()
> 

I reviewed this series, so I don't have any pointing out.
I can push to CIP tree.

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Best regards,
  Nobuhiro

>  .../bindings/dma/renesas,rz-dmac.yaml         |   3 +-
>  .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   1 +
>  .../bindings/power/renesas,rzg2l-sysc.yaml    |   7 +-
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |   2 +-
>  .../boot/dts/renesas/r9a07g044l2-smarc.dts    |   1 +
>  .../dts/renesas/rzg2l-smarc-pinfunction.dtsi  | 137 ++++++++++++++
> arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  | 127 -------------
>  drivers/dma/sh/Kconfig                        |   6 +-
>  drivers/i2c/busses/i2c-riic.c                 |  34 ++--
>  drivers/iio/adc/Kconfig                       |   2 +-
>  drivers/iio/adc/rzg2l_adc.c                   |  16 +-
>  drivers/reset/Kconfig                         |   2 +-
>  drivers/reset/reset-rzg2l-usbphy-ctrl.c       |  11 +-
>  drivers/soc/renesas/Kconfig                   |  12 ++
>  drivers/soc/renesas/renesas-soc.c             | 173
> ++++++++++--------
>  sound/soc/sh/Kconfig                          |   2 +-
>  sound/soc/sh/rz-ssi.c                         |  24 +--
>  17 files changed, 309 insertions(+), 251 deletions(-)  create mode 100644
> arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
> 
> --
> 2.25.1

Re: [PATCH 5.10.y-cip 00/24] RZ/G2L Fixes from mainline

[Pavel Machek]

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Hi!

> > Xu Wang (1):
> >   iio: adc: rzg2l_adc: Remove unnecessary print function dev_err()
> 
> I reviewed this series, so I don't have any pointing out.
> I can push to CIP tree.

Thank you. I already had series applied and tested, so I did the push.

Best regards,
									Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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