* [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support
@ 2022-08-02 11:08 Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 01/24] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC Biju Das
` (24 more replies)
0 siblings, 25 replies; 33+ messages in thread
From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw)
To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev
This patch series aims to add Basic board support for SMARC EVK
based on RZ/G2LC and RZ/V2L SoC. RZ/{G2L, G2LC, V2L} share the same
SMARC EVK board, but SoM is different and pin mapping of SoM
module is different.
All these patches are cherry-picked from the mainline.
Subsequent patch series will add more functionality to these platforms.
RZ/G2LC SMARC EVK logs:
root@smarc-rzg2lc:~# cat /sys/devices/soc0/family
RZ/G2L
root@smarc-rzg2lc:~# cat /sys/devices/soc0/machine
Renesas SMARC EVK based on r9a07g044c2
root@smarc-rzg2lc:~# cat /sys/devices/soc0/revision
1
root@smarc-rzg2lc:~# cat /sys/devices/soc0/soc_id
r9a07g044
root@smarc-rzg2lc:~# dmesg | grep Detect
[ 0.003208] Detected Renesas RZ/G2L r9a07g044 Rev 1
RZ/V2L SMARC EVK logs:
root@smarc-rzv2l:~# cat /sys/devices/soc0/family
RZ/V2L
root@smarc-rzv2l:~# cat /sys/devices/soc0/machine
Renesas SMARC EVK based on r9a07g054l2
root@smarc-rzv2l:~# cat /sys/devices/soc0/revision
0
root@smarc-rzv2l:~# cat /sys/devices/soc0/soc_id
r9a07g054
root@smarc-rzv2l:~# dmesg | grep Detect
[ 0.003260] Detected Renesas RZ/V2L r9a07g054 Rev 0
Biju Das (20):
arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC
arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK
arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform
arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform
clk: renesas: r9a07g044: Add mux and divider for G clock
clk: renesas: r9a07g044: Add GPU clock and reset entries
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
dt-bindings: clock: renesas: Document RZ/V2L SoC
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
dt-bindings: serial: renesas,scif: Document RZ/V2L SoC
dt-bindings: serial: renesas,sci: Document RZ/V2L SoC
dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl
pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is
enabled
pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register()
dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC
arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings
arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board
Geert Uytterhoeven (1):
clk: renesas: rzg2l: Simplify multiplication/shift logic
Lad Prabhakar (2):
clk: renesas: r9a07g044: Update multiplier and divider values for
PLL2/3
arm64: defconfig: Enable ARCH_R9A07G054
Phil Edworthy (1):
clk: renesas: rzg2l: Remove unused notifiers
.../bindings/clock/renesas,rzg2l-cpg.yaml | 14 +-
.../bindings/net/renesas,etheravb.yaml | 3 +-
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +-
.../bindings/serial/renesas,sci.yaml | 2 +
.../bindings/serial/renesas,scif.yaml | 7 +
arch/arm64/boot/dts/renesas/Makefile | 3 +
arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 32 ++
.../boot/dts/renesas/r9a07g044c2-smarc.dts | 97 ++++
arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi | 20 +
.../boot/dts/renesas/r9a07g044l2-smarc.dts | 1 +
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 491 ++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 25 +
.../boot/dts/renesas/r9a07g054l2-smarc.dts | 26 +
arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi | 13 +
.../boot/dts/renesas/rz-smarc-common.dtsi | 207 ++++++++
.../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 2 +-
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 2 +-
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 195 +------
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 71 +++
.../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 218 ++++++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 62 +++
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g044-cpg.c | 421 ++++++++-------
drivers/clk/renesas/rzg2l-cpg.c | 10 +-
drivers/clk/renesas/rzg2l-cpg.h | 5 +
drivers/pinctrl/renesas/Kconfig | 6 +-
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 +-
include/dt-bindings/clock/r9a07g054-cpg.h | 229 ++++++++
30 files changed, 1795 insertions(+), 395 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
create mode 100644 include/dt-bindings/clock/r9a07g054-cpg.h
--
2.25.1
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH 5.10.y-cip 01/24] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Biju Das ` (23 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 3a3c2a48d8c6ba586a2eda249b0e2f5f19609dfd upstream. The RZ/G2L and RZ/G2LC SoCs are similar and they share the same DEVID. RZ/G2LC has fewer peripherals compared to RZ/G2L. SSI (3 channels vs 4 channels) GbEthernet (1 channel vs 2 channels) SCIFA (4 channels vs 5 channels) ADC is only supported in RZ/G2L. Add the initial DTSI for the RZ/G2LC SoC by reusing the common r9a07g044.dtsi file with unsupported device nodes deleted in the below SoC specific dtsi files. r9a07g044c1.dtsi => RZ/G2LC R9A07G044C1 SoC specific parts r9a07g044c2.dtsi => RZ/G2LC R9A07G044C2 SoC specific parts Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211216114305.5842-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 32 ++++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi | 20 ++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi new file mode 100644 index 000000000000..1d57df706939 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044c1", "renesas,r9a07g044"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&soc { + /delete-node/ ssi@1004a800; + /delete-node/ serial@1004c800; + /delete-node/ adc@10059000; + /delete-node/ ethernet@11c30000; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi new file mode 100644 index 000000000000..7bb8917fe421 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC R9A07G044C2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044c2", "renesas,r9a07g044"; +}; + +&soc { + /delete-node/ ssi@1004a800; + /delete-node/ serial@1004c800; + /delete-node/ adc@10059000; + /delete-node/ ethernet@11c30000; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 01/24] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 16:46 ` Pavel Machek 2022-08-02 11:08 ` [PATCH 5.10.y-cip 03/24] arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform Biju Das ` (22 subsequent siblings) 24 siblings, 1 reply; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit ce0c63b6a5ef86208d1008ce6c42a7a7180aaf75 upstream. Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2): - memory - External input clock - SCIF - GbEthernet - Audio Clock It shares the same carrier board with RZ/G2L, but the pin mapping is different. Disable the device nodes which are not tested and delete the corresponding pinctrl definitions. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211216114305.5842-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../boot/dts/renesas/r9a07g044c2-smarc.dts | 114 ++++++++++++++++++ .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 25 ++++ .../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 76 ++++++++++++ 4 files changed, 216 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 8a5bc12a6d8d..962a66332236 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -57,4 +57,5 @@ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts new file mode 100644 index 000000000000..728a2275ea8d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044c2.dtsi" +#include "rzg2lc-smarc-som.dtsi" +#include "rzg2lc-smarc-pinfunction.dtsi" +#include "rzg2l-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g044c2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; + +}; + +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&hsusb { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c3 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&phyrst { + status = "disabled"; +}; + +&scif2 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&sdhi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-1; + /delete-property/ pinctrl-names; + /delete-property/ vmmc-supply; + status = "disabled"; +}; + +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ssi0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi new file mode 100644 index 000000000000..5333a1f9a0e7 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC pincontrol parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; +}; + diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi new file mode 100644 index 000000000000..e1d7a3a689c6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC SOM common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/ { + aliases { + ethernet0 = ð0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ + <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ + <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ + <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ + <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ + <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ + <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ + <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ + <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ + <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ + <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ + <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ + <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ + <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + }; +}; + -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK 2022-08-02 11:08 ` [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Biju Das @ 2022-08-02 16:46 ` Pavel Machek 2022-08-03 7:19 ` Biju Das 0 siblings, 1 reply; 33+ messages in thread From: Pavel Machek @ 2022-08-02 16:46 UTC (permalink / raw) To: Biju Das; +Cc: Pavel Machek, nobuhiro1.iwamatsu, Lad Prabhakar, cip-dev [-- Attachment #1: Type: text/plain, Size: 900 bytes --] Hi! > > Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2): > - memory > - External input clock > - SCIF > - GbEthernet > - Audio Clock > > It shares the same carrier board with RZ/G2L, but the pin mapping is > different. Disable the device nodes which are not tested and delete the > corresponding pinctrl definitions. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Git is a bit unhappy with blank lines -- Applying: arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK .git/rebase-apply/patch:171: new blank line at EOF. + .git/rebase-apply/patch:253: new blank line at EOF. + -- but as before that is probably not worth solving in separate patch. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK 2022-08-02 16:46 ` Pavel Machek @ 2022-08-03 7:19 ` Biju Das 0 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-03 7:19 UTC (permalink / raw) To: Pavel Machek Cc: nobuhiro1.iwamatsu@toshiba.co.jp, Prabhakar Mahadev Lad, cip-dev@lists.cip-project.org Hi Pavel, Thanks for the feedback. > Subject: Re: [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial > device tree for RZ/G2LC SMARC EVK > > Hi! > > > > Add basic support for the RZ/G2LC SMARC EVK (based on R9A07G044C2): > > - memory > > - External input clock > > - SCIF > > - GbEthernet > > - Audio Clock > > > > It shares the same carrier board with RZ/G2L, but the pin mapping is > > different. Disable the device nodes which are not tested and delete > > the corresponding pinctrl definitions. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Git is a bit unhappy with blank lines -- > > Applying: arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC > EVK > .git/rebase-apply/patch:171: new blank line at EOF. > + > .git/rebase-apply/patch:253: new blank line at EOF. > + > > -- but as before that is probably not worth solving in separate patch. OK, will fix this in mainline when I get a chance to work on this file. Cheers, Biju ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 03/24] arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 01/24] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 04/24] arm64: dts: renesas: rzg2lc-smarc: Enable microSD " Biju Das ` (21 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 7ca0ce6478c6803c9f86e7366f5634de9c096207 upstream. RZ/G2LC SoM has both 64 GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on the XOR between GPIO_SD0_DEV_SEL and SW1[2] switch position. This patch sets GPIO_SD0_DEV_SEL to high in DT. Use the below switch setting logic for device selection between eMMC and microSD slot connected to SDHI0. Set SW1[2] to position OFF for selecting eMMC Set SW1[2] to position ON for selecting microSD This patch enables eMMC on RZ/G2LC SMARC platform by default. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220117075130.6198-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index e1d7a3a689c6..6ebda3724f2c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -8,6 +8,16 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> +/* SW1[2] should be at OFF position to enable 64 GB eMMC */ +#define EMMC 1 + +/* + * To enable uSD card on CN3, + * SW1[2] should be at ON position. + * Disable eMMC by setting "#define EMMC 0" above. + */ +#define SDHI (!EMMC) + / { aliases { ethernet0 = ð0; @@ -22,6 +32,36 @@ memory@48000000 { /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; }; ð0 { @@ -72,5 +112,107 @@ eth0_pins: eth0 { <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ }; + + gpio-sd0-pwr-en-hog { + gpio-hog; + gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "gpio_sd0_pwr_en"; + }; + + /* + * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] + * The below switch logic can be used to select the device between + * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. + * SW1[2] should be at OFF position to enable 64 GB eMMC + * SW1[2] should be at position ON to enable uSD card CN3 + */ + gpio-sd0-dev-sel-hog { + gpio-hog; + gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "gpio_sd0_dev_sel"; + }; + + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ + }; + }; +}; + +#if SDHI +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + +#if EMMC +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; }; +#endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 04/24] arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (2 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 03/24] arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 05/24] clk: renesas: r9a07g044: Add mux and divider for G clock Biju Das ` (20 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 81a27b1f69022174567e8237d3de2534821671ba upstream. Enable the microSD card slot connected to SDHI1 on the RZ/G2LC SMARC platform by removing the sdhi1 override which disabled it, and by adding the necessary pinmux required for SDHI1. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220117075130.6198-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/r9a07g044c2-smarc.dts | 8 ---- .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 39 +++++++++++++++++++ 2 files changed, 39 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 728a2275ea8d..8d671111d973 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -81,14 +81,6 @@ &scif2 { status = "disabled"; }; -&sdhi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-1; - /delete-property/ pinctrl-names; - /delete-property/ vmmc-supply; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 5333a1f9a0e7..1032f6563515 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -17,6 +17,45 @@ scif0_pins: scif0 { <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ }; + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ + }; + }; + sound_clk_pins: sound_clk { pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 05/24] clk: renesas: r9a07g044: Add mux and divider for G clock 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (3 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 04/24] arm64: dts: renesas: rzg2lc-smarc: Enable microSD " Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 06/24] clk: renesas: r9a07g044: Add GPU clock and reset entries Biju Das ` (19 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 7ef9c45a23a9071dee23ca1a769c53ec2cdc07c0 upstream. G clock is sourced from PLL3 and PLL6. The output of the mux is connected to divider. This patch adds a mux and divider for getting different rates from this clock sources. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 6 ++++++ drivers/clk/renesas/rzg2l-cpg.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 0962f25cd3f0..85132b6c97b7 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -50,6 +50,7 @@ enum clk_ids { CLK_PLL2_SDHI_266, CLK_SD0_DIV4, CLK_SD1_DIV4, + CLK_SEL_GPU2, /* Module Clocks */ MOD_CLK_BASE, @@ -77,6 +78,7 @@ static const struct clk_div_table dtable_1_32[] = { static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; +static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { /* External Clock Inputs */ @@ -116,6 +118,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), + DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, + sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), /* Core output clk */ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, @@ -141,6 +145,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { sel_shdi, ARRAY_SIZE(sel_shdi)), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), + DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, + CLK_DIVIDER_HIWORD_MASK), }; static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index fce4a8f35410..5729d102034b 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -12,9 +12,11 @@ #define CPG_PL1_DDIV (0x200) #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) +#define CPG_PL6_DDIV (0x210) #define CPG_PL2SDHI_DSEL (0x218) #define CPG_CLKSTATUS (0x280) #define CPG_PL3_SSEL (0x408) +#define CPG_PL6_SSEL (0x414) #define CPG_PL6_ETH_SSEL (0x418) #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) @@ -35,12 +37,14 @@ #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) +#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) #define SEL_PLL_PACK(offset, bitpos, size) \ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) +#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 06/24] clk: renesas: r9a07g044: Add GPU clock and reset entries 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (4 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 05/24] clk: renesas: r9a07g044: Add mux and divider for G clock Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 Biju Das ` (18 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit f0b62b0bbedcdfde18116080605cebd9beec4ee9 upstream. Add GPU clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 85132b6c97b7..79042bf46fe8 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -198,6 +198,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x554, 6), DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, 0x554, 7), + DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, + 0x558, 0), + DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, + 0x558, 1), + DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, + 0x558, 2), DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 0x570, 0), DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, @@ -285,6 +291,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_SPI_RST, 0x850, 0), DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1), + DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), + DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), + DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2), -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (5 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 06/24] clk: renesas: r9a07g044: Add GPU clock and reset entries Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 08/24] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions Biju Das ` (17 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit b289cdecc7c3e25e001cde260c882e4d9a8b0772 upstream. As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600 MHz, but with current multiplier and divider values this resulted to 1596 MHz. This patch updates the multiplier and divider values for PLL2 and PLL3 so that we get the exact (1600 MHz) values. Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC") Suggested-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 79042bf46fe8..46359afef0d4 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -88,8 +88,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), - DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), - DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 08/24] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (6 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 09/24] dt-bindings: clock: renesas: Document RZ/V2L SoC Biju Das ` (16 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 4decd2e54b61686787f36b727d2772e067a46ea5 upstream. Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev. 1.00, Nov. 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220126211003.6675-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- include/dt-bindings/clock/r9a07g054-cpg.h | 229 ++++++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 include/dt-bindings/clock/r9a07g054-cpg.h diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h new file mode 100644 index 000000000000..43f4dbda872c --- /dev/null +++ b/include/dt-bindings/clock/r9a07g054-cpg.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A07G054 CPG Core Clocks */ +#define R9A07G054_CLK_I 0 +#define R9A07G054_CLK_I2 1 +#define R9A07G054_CLK_G 2 +#define R9A07G054_CLK_S0 3 +#define R9A07G054_CLK_S1 4 +#define R9A07G054_CLK_SPI0 5 +#define R9A07G054_CLK_SPI1 6 +#define R9A07G054_CLK_SD0 7 +#define R9A07G054_CLK_SD1 8 +#define R9A07G054_CLK_M0 9 +#define R9A07G054_CLK_M1 10 +#define R9A07G054_CLK_M2 11 +#define R9A07G054_CLK_M3 12 +#define R9A07G054_CLK_M4 13 +#define R9A07G054_CLK_HP 14 +#define R9A07G054_CLK_TSU 15 +#define R9A07G054_CLK_ZT 16 +#define R9A07G054_CLK_P0 17 +#define R9A07G054_CLK_P1 18 +#define R9A07G054_CLK_P2 19 +#define R9A07G054_CLK_AT 20 +#define R9A07G054_OSCCLK 21 +#define R9A07G054_CLK_P0_DIV2 22 +#define R9A07G054_CLK_DRP_M 23 +#define R9A07G054_CLK_DRP_D 24 +#define R9A07G054_CLK_DRP_A 25 + +/* R9A07G054 Module Clocks */ +#define R9A07G054_CA55_SCLK 0 +#define R9A07G054_CA55_PCLK 1 +#define R9A07G054_CA55_ATCLK 2 +#define R9A07G054_CA55_GICCLK 3 +#define R9A07G054_CA55_PERICLK 4 +#define R9A07G054_CA55_ACLK 5 +#define R9A07G054_CA55_TSCLK 6 +#define R9A07G054_GIC600_GICCLK 7 +#define R9A07G054_IA55_CLK 8 +#define R9A07G054_IA55_PCLK 9 +#define R9A07G054_MHU_PCLK 10 +#define R9A07G054_SYC_CNT_CLK 11 +#define R9A07G054_DMAC_ACLK 12 +#define R9A07G054_DMAC_PCLK 13 +#define R9A07G054_OSTM0_PCLK 14 +#define R9A07G054_OSTM1_PCLK 15 +#define R9A07G054_OSTM2_PCLK 16 +#define R9A07G054_MTU_X_MCK_MTU3 17 +#define R9A07G054_POE3_CLKM_POE 18 +#define R9A07G054_GPT_PCLK 19 +#define R9A07G054_POEG_A_CLKP 20 +#define R9A07G054_POEG_B_CLKP 21 +#define R9A07G054_POEG_C_CLKP 22 +#define R9A07G054_POEG_D_CLKP 23 +#define R9A07G054_WDT0_PCLK 24 +#define R9A07G054_WDT0_CLK 25 +#define R9A07G054_WDT1_PCLK 26 +#define R9A07G054_WDT1_CLK 27 +#define R9A07G054_WDT2_PCLK 28 +#define R9A07G054_WDT2_CLK 29 +#define R9A07G054_SPI_CLK2 30 +#define R9A07G054_SPI_CLK 31 +#define R9A07G054_SDHI0_IMCLK 32 +#define R9A07G054_SDHI0_IMCLK2 33 +#define R9A07G054_SDHI0_CLK_HS 34 +#define R9A07G054_SDHI0_ACLK 35 +#define R9A07G054_SDHI1_IMCLK 36 +#define R9A07G054_SDHI1_IMCLK2 37 +#define R9A07G054_SDHI1_CLK_HS 38 +#define R9A07G054_SDHI1_ACLK 39 +#define R9A07G054_GPU_CLK 40 +#define R9A07G054_GPU_AXI_CLK 41 +#define R9A07G054_GPU_ACE_CLK 42 +#define R9A07G054_ISU_ACLK 43 +#define R9A07G054_ISU_PCLK 44 +#define R9A07G054_H264_CLK_A 45 +#define R9A07G054_H264_CLK_P 46 +#define R9A07G054_CRU_SYSCLK 47 +#define R9A07G054_CRU_VCLK 48 +#define R9A07G054_CRU_PCLK 49 +#define R9A07G054_CRU_ACLK 50 +#define R9A07G054_MIPI_DSI_PLLCLK 51 +#define R9A07G054_MIPI_DSI_SYSCLK 52 +#define R9A07G054_MIPI_DSI_ACLK 53 +#define R9A07G054_MIPI_DSI_PCLK 54 +#define R9A07G054_MIPI_DSI_VCLK 55 +#define R9A07G054_MIPI_DSI_LPCLK 56 +#define R9A07G054_LCDC_CLK_A 57 +#define R9A07G054_LCDC_CLK_P 58 +#define R9A07G054_LCDC_CLK_D 59 +#define R9A07G054_SSI0_PCLK2 60 +#define R9A07G054_SSI0_PCLK_SFR 61 +#define R9A07G054_SSI1_PCLK2 62 +#define R9A07G054_SSI1_PCLK_SFR 63 +#define R9A07G054_SSI2_PCLK2 64 +#define R9A07G054_SSI2_PCLK_SFR 65 +#define R9A07G054_SSI3_PCLK2 66 +#define R9A07G054_SSI3_PCLK_SFR 67 +#define R9A07G054_SRC_CLKP 68 +#define R9A07G054_USB_U2H0_HCLK 69 +#define R9A07G054_USB_U2H1_HCLK 70 +#define R9A07G054_USB_U2P_EXR_CPUCLK 71 +#define R9A07G054_USB_PCLK 72 +#define R9A07G054_ETH0_CLK_AXI 73 +#define R9A07G054_ETH0_CLK_CHI 74 +#define R9A07G054_ETH1_CLK_AXI 75 +#define R9A07G054_ETH1_CLK_CHI 76 +#define R9A07G054_I2C0_PCLK 77 +#define R9A07G054_I2C1_PCLK 78 +#define R9A07G054_I2C2_PCLK 79 +#define R9A07G054_I2C3_PCLK 80 +#define R9A07G054_SCIF0_CLK_PCK 81 +#define R9A07G054_SCIF1_CLK_PCK 82 +#define R9A07G054_SCIF2_CLK_PCK 83 +#define R9A07G054_SCIF3_CLK_PCK 84 +#define R9A07G054_SCIF4_CLK_PCK 85 +#define R9A07G054_SCI0_CLKP 86 +#define R9A07G054_SCI1_CLKP 87 +#define R9A07G054_IRDA_CLKP 88 +#define R9A07G054_RSPI0_CLKB 89 +#define R9A07G054_RSPI1_CLKB 90 +#define R9A07G054_RSPI2_CLKB 91 +#define R9A07G054_CANFD_PCLK 92 +#define R9A07G054_GPIO_HCLK 93 +#define R9A07G054_ADC_ADCLK 94 +#define R9A07G054_ADC_PCLK 95 +#define R9A07G054_TSU_PCLK 96 +#define R9A07G054_STPAI_INITCLK 97 +#define R9A07G054_STPAI_ACLK 98 +#define R9A07G054_STPAI_MCLK 99 +#define R9A07G054_STPAI_DCLKIN 100 +#define R9A07G054_STPAI_ACLK_DRP 101 + +/* R9A07G054 Resets */ +#define R9A07G054_CA55_RST_1_0 0 +#define R9A07G054_CA55_RST_1_1 1 +#define R9A07G054_CA55_RST_3_0 2 +#define R9A07G054_CA55_RST_3_1 3 +#define R9A07G054_CA55_RST_4 4 +#define R9A07G054_CA55_RST_5 5 +#define R9A07G054_CA55_RST_6 6 +#define R9A07G054_CA55_RST_7 7 +#define R9A07G054_CA55_RST_8 8 +#define R9A07G054_CA55_RST_9 9 +#define R9A07G054_CA55_RST_10 10 +#define R9A07G054_CA55_RST_11 11 +#define R9A07G054_CA55_RST_12 12 +#define R9A07G054_GIC600_GICRESET_N 13 +#define R9A07G054_GIC600_DBG_GICRESET_N 14 +#define R9A07G054_IA55_RESETN 15 +#define R9A07G054_MHU_RESETN 16 +#define R9A07G054_DMAC_ARESETN 17 +#define R9A07G054_DMAC_RST_ASYNC 18 +#define R9A07G054_SYC_RESETN 19 +#define R9A07G054_OSTM0_PRESETZ 20 +#define R9A07G054_OSTM1_PRESETZ 21 +#define R9A07G054_OSTM2_PRESETZ 22 +#define R9A07G054_MTU_X_PRESET_MTU3 23 +#define R9A07G054_POE3_RST_M_REG 24 +#define R9A07G054_GPT_RST_C 25 +#define R9A07G054_POEG_A_RST 26 +#define R9A07G054_POEG_B_RST 27 +#define R9A07G054_POEG_C_RST 28 +#define R9A07G054_POEG_D_RST 29 +#define R9A07G054_WDT0_PRESETN 30 +#define R9A07G054_WDT1_PRESETN 31 +#define R9A07G054_WDT2_PRESETN 32 +#define R9A07G054_SPI_RST 33 +#define R9A07G054_SDHI0_IXRST 34 +#define R9A07G054_SDHI1_IXRST 35 +#define R9A07G054_GPU_RESETN 36 +#define R9A07G054_GPU_AXI_RESETN 37 +#define R9A07G054_GPU_ACE_RESETN 38 +#define R9A07G054_ISU_ARESETN 39 +#define R9A07G054_ISU_PRESETN 40 +#define R9A07G054_H264_X_RESET_VCP 41 +#define R9A07G054_H264_CP_PRESET_P 42 +#define R9A07G054_CRU_CMN_RSTB 43 +#define R9A07G054_CRU_PRESETN 44 +#define R9A07G054_CRU_ARESETN 45 +#define R9A07G054_MIPI_DSI_CMN_RSTB 46 +#define R9A07G054_MIPI_DSI_ARESET_N 47 +#define R9A07G054_MIPI_DSI_PRESET_N 48 +#define R9A07G054_LCDC_RESET_N 49 +#define R9A07G054_SSI0_RST_M2_REG 50 +#define R9A07G054_SSI1_RST_M2_REG 51 +#define R9A07G054_SSI2_RST_M2_REG 52 +#define R9A07G054_SSI3_RST_M2_REG 53 +#define R9A07G054_SRC_RST 54 +#define R9A07G054_USB_U2H0_HRESETN 55 +#define R9A07G054_USB_U2H1_HRESETN 56 +#define R9A07G054_USB_U2P_EXL_SYSRST 57 +#define R9A07G054_USB_PRESETN 58 +#define R9A07G054_ETH0_RST_HW_N 59 +#define R9A07G054_ETH1_RST_HW_N 60 +#define R9A07G054_I2C0_MRST 61 +#define R9A07G054_I2C1_MRST 62 +#define R9A07G054_I2C2_MRST 63 +#define R9A07G054_I2C3_MRST 64 +#define R9A07G054_SCIF0_RST_SYSTEM_N 65 +#define R9A07G054_SCIF1_RST_SYSTEM_N 66 +#define R9A07G054_SCIF2_RST_SYSTEM_N 67 +#define R9A07G054_SCIF3_RST_SYSTEM_N 68 +#define R9A07G054_SCIF4_RST_SYSTEM_N 69 +#define R9A07G054_SCI0_RST 70 +#define R9A07G054_SCI1_RST 71 +#define R9A07G054_IRDA_RST 72 +#define R9A07G054_RSPI0_RST 73 +#define R9A07G054_RSPI1_RST 74 +#define R9A07G054_RSPI2_RST 75 +#define R9A07G054_CANFD_RSTP_N 76 +#define R9A07G054_CANFD_RSTC_N 77 +#define R9A07G054_GPIO_RSTN 78 +#define R9A07G054_GPIO_PORT_RESETN 79 +#define R9A07G054_GPIO_SPARE_RESETN 80 +#define R9A07G054_ADC_PRESETN 81 +#define R9A07G054_ADC_ADRST_N 82 +#define R9A07G054_TSU_PRESETN 83 +#define R9A07G054_STPAI_ARESETN 84 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 09/24] dt-bindings: clock: renesas: Document RZ/V2L SoC 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (7 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 08/24] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for " Biju Das ` (15 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 678eb67513a963e5ce00a4ed6a07a5722bd1267e upstream. Document the device tree binding for the Renesas RZ/V2L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220110134659.30424-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../bindings/clock/renesas,rzg2l-cpg.yaml | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 30b2e3d0d25d..bd3af8fc616b 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -4,13 +4,13 @@ $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode +title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> description: | - On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module + On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module Standby Mode share the same register block. They provide the following functionalities: @@ -22,7 +22,9 @@ description: | properties: compatible: - const: renesas,r9a07g044-cpg # RZ/G2{L,LC} + enum: + - renesas,r9a07g044-cpg # RZ/G2{L,LC} + - renesas,r9a07g054-cpg # RZ/V2L reg: maxItems: 1 @@ -40,9 +42,9 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - <dt-bindings/clock/r9a07g044-cpg.h> + <dt-bindings/clock/r9a07g*-cpg.h> - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>. + a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>. const: 2 '#power-domain-cells': @@ -56,7 +58,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the <dt-bindings/clock/r9a07g044-cpg.h>. + the <dt-bindings/clock/r9a07g0*-cpg.h>. const: 1 required: -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (8 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 09/24] dt-bindings: clock: renesas: Document RZ/V2L SoC Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 16:54 ` Pavel Machek 2022-08-02 11:08 ` [PATCH 5.10.y-cip 11/24] clk: renesas: rzg2l: Remove unused notifiers Biju Das ` (14 subsequent siblings) 24 siblings, 1 reply; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd upstream. The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a07g044-cpg.c | 426 +++++++++++++++------------- drivers/clk/renesas/rzg2l-cpg.c | 6 + drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 250 insertions(+), 191 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 4d8de55bc6f4..162ea716b9a5 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -33,6 +33,7 @@ config CLK_RENESAS select CLK_R8A779A0 if ARCH_R8A779A0 select CLK_R9A06G032 if ARCH_R9A06G032 select CLK_R9A07G044 if ARCH_R9A07G044 + select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_SH73A0 if ARCH_SH73A0 if CLK_RENESAS @@ -160,6 +161,10 @@ config CLK_R9A07G044 bool "RZ/G2L clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A07G054 + bool "RZ/V2L clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP @@ -183,7 +188,7 @@ config CLK_RCAR_USB2_CLOCK_SEL This is a driver for R-Car USB2 clock selector config CLK_RZG2L - bool "Renesas RZ/G2L family clock support" if COMPILE_TEST + bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER # Generic diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index cd104e75dab6..7cb90ed1e1db 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o +obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 46359afef0d4..bdfabb992a20 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -11,12 +11,13 @@ #include <linux/kernel.h> #include <dt-bindings/clock/r9a07g044-cpg.h> +#include <dt-bindings/clock/r9a07g054-cpg.h> #include "rzg2l-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2, + LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, /* External Input Clocks */ CLK_EXTAL, @@ -80,200 +81,222 @@ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; -static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { - /* External Clock Inputs */ - DEF_INPUT("extal", CLK_EXTAL), +static const struct { + struct cpg_core_clk common[44]; +#ifdef CONFIG_CLK_R9A07G054 + struct cpg_core_clk drp[0]; +#endif +} core_clks __initconst = { + .common = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), - /* Internal Core Clocks */ - DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), - DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), - DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), - DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), - DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), - DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), - DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), + /* Internal Core Clocks */ + DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), + DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), + DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), - DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), - DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), + DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), + DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), - DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), - DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), - DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), - DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), - DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), - DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), + DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), + DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), + DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), - DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), - DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), + DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), + DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), - DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), - DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), - DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), - DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), - DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, - sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), - DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, - DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), + DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), + DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), + DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, + sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), + DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, + DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), - DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), - DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), - DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, - sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), + DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), + DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), + DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, + sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), - /* Core output clk */ - DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, - CLK_DIVIDER_HIWORD_MASK), - DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, - dtable_1_32, CLK_DIVIDER_HIWORD_MASK), - DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), - DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), - DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, - DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), - DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), - DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, - DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), - DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), - DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), - DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, - sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), - DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), - DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), - DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, - sel_shdi, ARRAY_SIZE(sel_shdi)), - DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, - sel_shdi, ARRAY_SIZE(sel_shdi)), - DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), - DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), - DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, - CLK_DIVIDER_HIWORD_MASK), + /* Core output clk */ + DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, + CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, + dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), + DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), + DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, + DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), + DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, + DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), + DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), + DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, + sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), + DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), + DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), + DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, + sel_shdi, ARRAY_SIZE(sel_shdi)), + DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, + sel_shdi, ARRAY_SIZE(sel_shdi)), + DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), + DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), + DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, + CLK_DIVIDER_HIWORD_MASK), + }, +#ifdef CONFIG_CLK_R9A07G054 + .drp = { + }, +#endif }; -static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { - DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, - 0x514, 0), - DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, - 0x518, 0), - DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, - 0x518, 1), - DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, - 0x52c, 0), - DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, - 0x52c, 1), - DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, - 0x534, 0), - DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, - 0x534, 1), - DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, - 0x534, 2), - DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, - 0x548, 0), - DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, - 0x548, 1), - DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, - 0x548, 2), - DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, - 0x548, 3), - DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0, - 0x548, 4), - DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK, - 0x548, 5), - DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, - 0x550, 0), - DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, - 0x550, 1), - DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, - 0x554, 0), - DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, - 0x554, 1), - DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, - 0x554, 2), - DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, - 0x554, 3), - DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, - 0x554, 4), - DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, - 0x554, 5), - DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, - 0x554, 6), - DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, - 0x554, 7), - DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, - 0x558, 0), - DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, - 0x558, 1), - DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, - 0x558, 2), - DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, - 0x570, 0), - DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, - 0x570, 1), - DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, - 0x570, 2), - DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, - 0x570, 3), - DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, - 0x570, 4), - DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, - 0x570, 5), - DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, - 0x570, 6), - DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, - 0x570, 7), - DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, - 0x578, 0), - DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, - 0x578, 1), - DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, - 0x578, 2), - DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, - 0x578, 3), - DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, - 0x57c, 0), - DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, - 0x57c, 0), - DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, - 0x57c, 1), - DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, - 0x57c, 1), - DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, - 0x580, 0), - DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, - 0x580, 1), - DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, - 0x580, 2), - DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, - 0x580, 3), - DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 0), - DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 1), - DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 2), - DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 3), - DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 4), - DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, - 0x588, 0), - DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, - 0x588, 1), - DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, - 0x590, 0), - DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, - 0x590, 1), - DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, - 0x590, 2), - DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, - 0x594, 0), - DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, - 0x598, 0), - DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, - 0x5a8, 0), - DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, - 0x5a8, 1), - DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, - 0x5ac, 0), +static const struct { + struct rzg2l_mod_clk common[62]; +#ifdef CONFIG_CLK_R9A07G054 + struct rzg2l_mod_clk drp[0]; +#endif +} mod_clks = { + .common = { + DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, + 0x514, 0), + DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, + 0x518, 0), + DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, + 0x518, 1), + DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, + 0x52c, 0), + DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, + 0x52c, 1), + DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, + 0x534, 0), + DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, + 0x534, 1), + DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, + 0x534, 2), + DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, + 0x548, 0), + DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, + 0x548, 1), + DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, + 0x548, 2), + DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, + 0x548, 3), + DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0, + 0x548, 4), + DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK, + 0x548, 5), + DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, + 0x550, 0), + DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, + 0x550, 1), + DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, + 0x554, 0), + DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, + 0x554, 1), + DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, + 0x554, 2), + DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, + 0x554, 3), + DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, + 0x554, 4), + DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, + 0x554, 5), + DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, + 0x554, 6), + DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, + 0x554, 7), + DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, + 0x558, 0), + DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, + 0x558, 1), + DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, + 0x558, 2), + DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, + 0x570, 0), + DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 1), + DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, + 0x570, 2), + DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 3), + DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, + 0x570, 4), + DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 5), + DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, + 0x570, 6), + DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 7), + DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, + 0x578, 0), + DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, + 0x578, 1), + DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, + 0x578, 2), + DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, + 0x578, 3), + DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, + 0x57c, 0), + DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, + 0x57c, 0), + DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, + 0x57c, 1), + DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, + 0x57c, 1), + DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, + 0x580, 0), + DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, + 0x580, 1), + DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, + 0x580, 2), + DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, + 0x580, 3), + DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 0), + DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 1), + DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 2), + DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 3), + DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 4), + DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, + 0x588, 0), + DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, + 0x588, 1), + DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, + 0x590, 0), + DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, + 0x590, 1), + DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, + 0x590, 2), + DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, + 0x594, 0), + DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, + 0x598, 0), + DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, + 0x5a8, 0), + DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, + 0x5a8, 1), + DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, + 0x5ac, 0), + }, +#ifdef CONFIG_CLK_R9A07G054 + .drp = { + }, +#endif }; static struct rzg2l_reset r9a07g044_resets[] = { @@ -336,8 +359,8 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Core Clocks */ - .core_clks = r9a07g044_core_clks, - .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks), + .core_clks = core_clks.common, + .num_core_clks = ARRAY_SIZE(core_clks.common), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, @@ -346,11 +369,34 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), /* Module Clocks */ - .mod_clks = r9a07g044_mod_clks, - .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks), + .mod_clks = mod_clks.common, + .num_mod_clks = ARRAY_SIZE(mod_clks.common), .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, /* Resets */ .resets = r9a07g044_resets, - .num_resets = ARRAY_SIZE(r9a07g044_resets), + .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ +}; + +#ifdef CONFIG_CLK_R9A07G054 +const struct rzg2l_cpg_info r9a07g054_cpg_info = { + /* Core Clocks */ + .core_clks = core_clks.common, + .num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a07g044_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = mod_clks.common, + .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp), + .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1, + + /* Resets */ + .resets = r9a07g044_resets, + .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ }; +#endif diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index edd0abe34a37..486d0656c58a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -952,6 +952,12 @@ static const struct of_device_id rzg2l_cpg_match[] = { .compatible = "renesas,r9a07g044-cpg", .data = &r9a07g044_cpg_info, }, +#endif +#ifdef CONFIG_CLK_R9A07G054 + { + .compatible = "renesas,r9a07g054-cpg", + .data = &r9a07g054_cpg_info, + }, #endif { /* sentinel */ } }; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 5729d102034b..ce657beaf160 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -203,5 +203,6 @@ struct rzg2l_cpg_info { }; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; +extern const struct rzg2l_cpg_info r9a07g054_cpg_info; #endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC 2022-08-02 11:08 ` [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for " Biju Das @ 2022-08-02 16:54 ` Pavel Machek 2022-08-03 7:16 ` Biju Das 0 siblings, 1 reply; 33+ messages in thread From: Pavel Machek @ 2022-08-02 16:54 UTC (permalink / raw) To: Biju Das; +Cc: Pavel Machek, nobuhiro1.iwamatsu, Lad Prabhakar, cip-dev [-- Attachment #1: Type: text/plain, Size: 3488 bytes --] Hi! > commit a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd upstream. > > The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. > The only difference being that RZ/V2L has additional registers to > control clocks and resets for the DRP-AI block. > > Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same > between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take > care of the DRP-AI clocks/resets. Ok, so this reuse is quite interesting. > +++ b/drivers/clk/renesas/Makefile > @@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o > obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o > obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o > obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o > +obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o > obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o They share the same source file, but the file will be different basen on config options. If you enable CONFIG_CLK_R9A07G044, you get g044 support but not g054 support. If you enable CONFIG_CLK_R9A07G054, you get both g044 and g054 support, you can't disable g044. This is quite strange, but probably not a problem. For symmetry, I'd not mind conditional compilation of g044 parts; or perhaps even better get rid of condtional compilation of g045 parts -- I don't believe space savings are significant. Best regards, Pavel > index 46359afef0d4..bdfabb992a20 100644 > --- a/drivers/clk/renesas/r9a07g044-cpg.c > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > + > +#ifdef CONFIG_CLK_R9A07G054 > +const struct rzg2l_cpg_info r9a07g054_cpg_info = { > + /* Core Clocks */ > + .core_clks = core_clks.common, > + .num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp), > + .last_dt_core_clk = LAST_DT_CORE_CLK, > + .num_total_core_clks = MOD_CLK_BASE, > + > + /* Critical Module Clocks */ > + .crit_mod_clks = r9a07g044_crit_mod_clks, > + .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), > + > + /* Module Clocks */ > + .mod_clks = mod_clks.common, > + .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp), > + .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1, > + > + /* Resets */ > + .resets = r9a07g044_resets, > + .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ > }; > +#endif > diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c > index edd0abe34a37..486d0656c58a 100644 > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -952,6 +952,12 @@ static const struct of_device_id rzg2l_cpg_match[] = { > .compatible = "renesas,r9a07g044-cpg", > .data = &r9a07g044_cpg_info, > }, > +#endif > +#ifdef CONFIG_CLK_R9A07G054 > + { > + .compatible = "renesas,r9a07g054-cpg", > + .data = &r9a07g054_cpg_info, > + }, > #endif > { /* sentinel */ } > }; > diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h > index 5729d102034b..ce657beaf160 100644 > --- a/drivers/clk/renesas/rzg2l-cpg.h > +++ b/drivers/clk/renesas/rzg2l-cpg.h > @@ -203,5 +203,6 @@ struct rzg2l_cpg_info { > }; > > extern const struct rzg2l_cpg_info r9a07g044_cpg_info; > +extern const struct rzg2l_cpg_info r9a07g054_cpg_info; > > #endif > -- > 2.25.1 > -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC 2022-08-02 16:54 ` Pavel Machek @ 2022-08-03 7:16 ` Biju Das 2022-08-03 13:50 ` Pavel Machek 0 siblings, 1 reply; 33+ messages in thread From: Biju Das @ 2022-08-03 7:16 UTC (permalink / raw) To: Pavel Machek Cc: nobuhiro1.iwamatsu@toshiba.co.jp, Prabhakar Mahadev Lad, cip-dev@lists.cip-project.org Hi Pavel, Thanks for the feedback. > Subject: Re: [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add > support for RZ/V2L SoC > > Hi! > > > commit a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd upstream. > > > > The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. > > The only difference being that RZ/V2L has additional registers to > > control clocks and resets for the DRP-AI block. > > > > Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same > > between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to > > take care of the DRP-AI clocks/resets. > > Ok, so this reuse is quite interesting. > > > > +++ b/drivers/clk/renesas/Makefile > > @@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg- > mssr.o > > obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o > > obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o > > obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o > > +obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o > > obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o > > They share the same source file, but the file will be different basen on > config options. > > If you enable CONFIG_CLK_R9A07G044, you get g044 support but not g054 > support. > > If you enable CONFIG_CLK_R9A07G054, you get both g044 and g054 support, > you can't disable g044. This is not true, we can disable g044 still. see rzg2l_cpg.c, there is a guard for CONFIG_CLK_R9A07G044. In this case,We will get unused variable warning for r9a07g044_cpg_info. > > This is quite strange, but probably not a problem. For symmetry, I'd not > mind conditional compilation of g044 parts; OK, will send patch for adding guard for r9a07g044_cpg_info. or perhaps even better get > rid of condtional compilation of g045 parts -- I don't believe space > savings are significant. Yes true, still it saves some bytes. Cheers, Biju > > > > index 46359afef0d4..bdfabb992a20 100644 > > --- a/drivers/clk/renesas/r9a07g044-cpg.c > > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > > + > > +#ifdef CONFIG_CLK_R9A07G054 > > +const struct rzg2l_cpg_info r9a07g054_cpg_info = { > > + /* Core Clocks */ > > + .core_clks = core_clks.common, > > + .num_core_clks = ARRAY_SIZE(core_clks.common) + > ARRAY_SIZE(core_clks.drp), > > + .last_dt_core_clk = LAST_DT_CORE_CLK, > > + .num_total_core_clks = MOD_CLK_BASE, > > + > > + /* Critical Module Clocks */ > > + .crit_mod_clks = r9a07g044_crit_mod_clks, > > + .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), > > + > > + /* Module Clocks */ > > + .mod_clks = mod_clks.common, > > + .num_mod_clks = ARRAY_SIZE(mod_clks.common) + > ARRAY_SIZE(mod_clks.drp), > > + .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1, > > + > > + /* Resets */ > > + .resets = r9a07g044_resets, > > + .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ > > }; > > +#endif > > diff --git a/drivers/clk/renesas/rzg2l-cpg.c > > b/drivers/clk/renesas/rzg2l-cpg.c index edd0abe34a37..486d0656c58a > > 100644 > > --- a/drivers/clk/renesas/rzg2l-cpg.c > > +++ b/drivers/clk/renesas/rzg2l-cpg.c > > @@ -952,6 +952,12 @@ static const struct of_device_id > rzg2l_cpg_match[] = { > > .compatible = "renesas,r9a07g044-cpg", > > .data = &r9a07g044_cpg_info, > > }, > > +#endif > > +#ifdef CONFIG_CLK_R9A07G054 > > + { > > + .compatible = "renesas,r9a07g054-cpg", > > + .data = &r9a07g054_cpg_info, > > + }, > > #endif > > { /* sentinel */ } > > }; > > diff --git a/drivers/clk/renesas/rzg2l-cpg.h > > b/drivers/clk/renesas/rzg2l-cpg.h index 5729d102034b..ce657beaf160 > > 100644 > > --- a/drivers/clk/renesas/rzg2l-cpg.h > > +++ b/drivers/clk/renesas/rzg2l-cpg.h > > @@ -203,5 +203,6 @@ struct rzg2l_cpg_info { }; > > > > extern const struct rzg2l_cpg_info r9a07g044_cpg_info; > > +extern const struct rzg2l_cpg_info r9a07g054_cpg_info; > > > > #endif > > -- > > 2.25.1 > > > > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC 2022-08-03 7:16 ` Biju Das @ 2022-08-03 13:50 ` Pavel Machek 0 siblings, 0 replies; 33+ messages in thread From: Pavel Machek @ 2022-08-03 13:50 UTC (permalink / raw) To: Biju Das Cc: Pavel Machek, nobuhiro1.iwamatsu@toshiba.co.jp, Prabhakar Mahadev Lad, cip-dev@lists.cip-project.org [-- Attachment #1: Type: text/plain, Size: 802 bytes --] Hi! > > If you enable CONFIG_CLK_R9A07G044, you get g044 support but not g054 > > support. > > > > If you enable CONFIG_CLK_R9A07G054, you get both g044 and g054 support, > > you can't disable g044. > > This is not true, we can disable g044 still. see rzg2l_cpg.c, there is a guard > for CONFIG_CLK_R9A07G044. > > In this case,We will get unused variable warning for r9a07g044_cpg_info. > > > > > This is quite strange, but probably not a problem. For symmetry, I'd not > > mind conditional compilation of g044 parts; > > OK, will send patch for adding guard for r9a07g044_cpg_info. Thank you. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 11/24] clk: renesas: rzg2l: Remove unused notifiers 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (9 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for " Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 12/24] clk: renesas: rzg2l: Simplify multiplication/shift logic Biju Das ` (13 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev From: Phil Edworthy <phil.edworthy@renesas.com> commit 53367bd28f3bf143355e66f20cb6cb83b70e9122 upstream. notifiers is not used. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220304143241.8523-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/rzg2l-cpg.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 486d0656c58a..b3a1533970e5 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -76,7 +76,6 @@ struct sd_hw_data { * @num_mod_clks: Number of Module Clocks in clks[] * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT - * @notifiers: Notifier chain to save/restore clock state for system resume * @info: Pointer to platform data */ struct rzg2l_cpg_priv { @@ -91,7 +90,6 @@ struct rzg2l_cpg_priv { unsigned int num_resets; unsigned int last_dt_core_clk; - struct raw_notifier_head notifiers; const struct rzg2l_cpg_info *info; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 12/24] clk: renesas: rzg2l: Simplify multiplication/shift logic 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (10 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 11/24] clk: renesas: rzg2l: Remove unused notifiers Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 13/24] dt-bindings: serial: renesas,scif: Document RZ/V2L SoC Biju Das ` (12 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev From: Geert Uytterhoeven <geert+renesas@glider.be> commit 29db30c45f07c929c86c40a5b85f18b69c89c638 upstream. "a * (1 << b)" == "a << b". No change in generated code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index b3a1533970e5..f626d2704477 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -289,7 +289,7 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); mult = MDIV(val1) + KDIV(val1) / 65536; - div = PDIV(val1) * (1 << SDIV(val2)); + div = PDIV(val1) << SDIV(val2); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); } -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 13/24] dt-bindings: serial: renesas,scif: Document RZ/V2L SoC 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (11 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 12/24] clk: renesas: rzg2l: Simplify multiplication/shift logic Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 14/24] dt-bindings: serial: renesas,sci: " Biju Das ` (11 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit b0c86a6083229db0518e2754b2b6298e40e8d637 upstream. Add SCIF binding documentation for Renesas RZ/V2L SoC. SCIF block on RZ/V2L is identical to one found on the RZ/G2L SoC. No driver changes are required as RZ/G2L compatible string "renesas,scif-r9a07g044" will be used as a fallback. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211221094717.16187-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 701cb4936f3c..d1fd82aac212 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -66,6 +66,12 @@ properties: - items: - enum: - renesas,scif-r9a07g044 # RZ/G2{L,LC} + - renesas,scif-r9a07g054 # RZ/V2L + + - items: + - enum: + - renesas,scif-r9a07g054 # RZ/V2L + - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback for RZ/V2L reg: maxItems: 1 @@ -151,6 +157,7 @@ if: - renesas,rcar-gen2-scif - renesas,rcar-gen3-scif - renesas,scif-r9a07g044 + - renesas,scif-r9a07g054 then: required: - resets -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 14/24] dt-bindings: serial: renesas,sci: Document RZ/V2L SoC 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (12 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 13/24] dt-bindings: serial: renesas,scif: Document RZ/V2L SoC Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 15/24] dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl Biju Das ` (10 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit a359101c7c6404d917a19d52133305ea284a0197 upstream. Add SCI binding documentation for Renesas RZ/V2L SoC. No driver changes are required as generic compatible string "renesas,sci" will be used as a fallback. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211221094717.16187-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- Documentation/devicetree/bindings/serial/renesas,sci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml index f00b1d38e9a5..8dda4e10e09d 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml @@ -18,6 +18,7 @@ properties: - items: - enum: - renesas,r9a07g044-sci # RZ/G2{L,LC} + - renesas,r9a07g054-sci # RZ/V2L - const: renesas,sci # generic SCI compatible UART - items: @@ -67,6 +68,7 @@ if: contains: enum: - renesas,r9a07g044-sci + - renesas,r9a07g054-sci then: properties: resets: -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 15/24] dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (13 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 14/24] dt-bindings: serial: renesas,sci: " Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 16/24] pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled Biju Das ` (9 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit c07b19de2f7ac91662aa99767815a258da6ef16f upstream. Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L SoC is package- and pin-compatible with RZ/G2L. No driver changes are required as the RZ/G2L compatible string "renesas,r9a07g044-pinctrl" will be used as a fallback. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220110134659.30424-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 83488cd8673d..e4849a3680e0 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G2L combined Pin and GPIO controller +title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function @@ -20,8 +20,15 @@ description: properties: compatible: - enum: - - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + oneOf: + - items: + - enum: + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + + - items: + - enum: + - renesas,r9a07g054-pinctrl # RZ/V2L + - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L reg: maxItems: 1 -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 16/24] pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (14 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 15/24] dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 17/24] pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register() Biju Das ` (8 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 0c8fce49f24e7c8ee2bdff4761f414ad59bfa29a upstream. RZ/V2L uses the RZ/G2L GPIO and pinctrl driver. Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled. Update the description for RZ/V2L pin control support. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220110134659.30424-8-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20220206194614.13209-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/pinctrl/renesas/Kconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 356a70739689..623d0c01e259 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -37,6 +37,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A77990 if ARCH_R8A77990 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_RZG2L if ARCH_R9A07G044 + select PINCTRL_RZG2L if ARCH_R9A07G054 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 @@ -173,14 +174,15 @@ config PINCTRL_RZA2 This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_RZG2L - bool "pin control support for RZ/G2L" if COMPILE_TEST + bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST depends on OF select GPIOLIB select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help - This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms. + This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L} + platforms. config PINCTRL_PFC_R8A77470 bool "pin control support for RZ/G1C" if COMPILE_TEST -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 17/24] pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register() 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (15 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 16/24] pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC Biju Das ` (7 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 2e08ab0427fe3e33a92a37cfe3b6db340ab7397f upstream. Update rzg2l_gpio_register() to use driver data for chip->names and check for gpio-range. This allows reusing the driver for SoC's with different port pin definitions(eg:- RZ/G2UL SoC has fewer ports compared to RZ/G2L and port pin definitions are different). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220206194614.13209-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index ccee9c9e2e22..cb805502fb0f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1090,12 +1090,12 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) } if (of_args.args[0] != 0 || of_args.args[1] != 0 || - of_args.args[2] != ARRAY_SIZE(rzg2l_gpio_names)) { + of_args.args[2] != pctrl->data->n_port_pins) { dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); return -EINVAL; } - chip->names = rzg2l_gpio_names; + chip->names = pctrl->data->port_pins; chip->request = rzg2l_gpio_request; chip->free = rzg2l_gpio_free; chip->get_direction = rzg2l_gpio_get_direction; -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (16 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 17/24] pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register() Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 19/24] arm64: dts: renesas: Add initial DTSI for " Biju Das ` (6 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 654f89f9496db716c4e9a79c3c6193d57cfaa963 upstream. Document Gigabit Ethernet IP found on RZ/V2L SoC. Gigabit Ethernet Interface is identical to one found on the RZ/G2L SoC. No driver changes are required as generic compatible string "renesas,rzg2l-gbeth" will be used as a fallback. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml index 5237949cfabe..80197259afa8 100644 --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml @@ -45,7 +45,8 @@ properties: - items: - enum: - renesas,r9a07g044-gbeth # RZ/G2{L,LC} - - const: renesas,rzg2l-gbeth # RZ/G2L + - renesas,r9a07g054-gbeth # RZ/V2L + - const: renesas,rzg2l-gbeth # RZ/{G2L,V2L} family reg: true -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 19/24] arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (17 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 20/24] arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK Biju Das ` (5 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 7c2b8198f4f321df03e285a931fab2a33668c88d upstream. The RZ/V2L SoC is package- and pin-compatible with RZ/G2L, the only difference being that the RZ/V2L SoC has additional DRP-AI IP (AI accelerator). Add initial DTSI for the RZ/V2L SoC with below SoC specific dtsi files for supporting single core and dual core devices: r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts Both the RZ/G2L and RZ/V2L SMARC EVK SoMs are identical apart from the SoCs used, hence the common dtsi files (rzg2l-smarc*.dtsi) are shared between the RZ/G2L and RZ/V2L SMARC EVKs. Place holders are added in device nodes to avoid compilation errors for devices which have not been enabled yet on the RZ/V2L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220110134659.30424-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 491 +++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 25 + arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi | 13 + 3 files changed, 529 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi new file mode 100644 index 000000000000..5d39e765c291 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L SoC + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a07g054-cpg.h> + +/ { + compatible = "renesas,r9a07g054"; + #address-cells = <2>; + #size-cells = <2>; + + audio_clk1: audio_clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + audio_clk2: audio_clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssi0: ssi@10049c00 { + reg = <0 0x10049c00 0 0x400>; + #sound-dai-cells = <0>; + /* place holder */ + }; + + spi1: spi@1004b000 { + reg = <0 0x1004b000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g054-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g054-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCI1_RST>; + status = "disabled"; + }; + + canfd: can@10050000 { + reg = <0 0x10050000 0 0x8000>; + /* place holder */ + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058000 0 0x400>; + /* place holder */ + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058400 0 0x400>; + /* place holder */ + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058c00 0 0x400>; + /* place holder */ + }; + + adc: adc@10059000 { + reg = <0 0x10059000 0 0x400>; + /* place holder */ + }; + + sbc: spi@10060000 { + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g054-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g054-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g054-pinctrl", + "renesas,r9a07g044-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 392>; + clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_GPIO_RSTN>, + <&cpg R9A07G054_GPIO_PORT_RESETN>, + <&cpg R9A07G054_GPIO_SPARE_RESETN>; + }; + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g054-dmac", + "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_DMAC_ARESETN>, + <&cpg R9A07G054_DMAC_RST_ASYNC>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + gpu: gpu@11840000 { + reg = <0x0 0x11840000 0x0 0x10000>; + /* place holder */ + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + sdhi0: mmc@11c00000 { + reg = <0x0 0x11c00000 0 0x10000>; + /* place holder */ + }; + + sdhi1: mmc@11c10000 { + reg = <0x0 0x11c10000 0 0x10000>; + /* place holder */ + }; + + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g054-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G054_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G054_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g054-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G054_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G054_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + phyrst: usbphy-ctrl@11c40000 { + reg = <0 0x11c40000 0 0x10000>; + /* place holder */ + }; + + ohci0: usb@11c50000 { + reg = <0 0x11c50000 0 0x100>; + /* place holder */ + }; + + ohci1: usb@11c70000 { + reg = <0 0x11c70000 0 0x100>; + /* place holder */ + }; + + ehci0: usb@11c50100 { + reg = <0 0x11c50100 0 0x100>; + /* place holder */ + }; + + ehci1: usb@11c70100 { + reg = <0 0x11c70100 0 0x100>; + /* place holder */ + }; + + usb2_phy0: usb-phy@11c50200 { + reg = <0 0x11c50200 0 0x700>; + /* place holder */ + }; + + usb2_phy1: usb-phy@11c70200 { + reg = <0 0x11c70200 0 0x700>; + /* place holder */ + }; + + hsusb: usb@11c60000 { + reg = <0 0x11c60000 0 0x10000>; + /* place holder */ + }; + + wdt0: watchdog@12800800 { + reg = <0 0x12800800 0 0x400>; + /* place holder */ + }; + + wdt1: watchdog@12800c00 { + reg = <0 0x12800C00 0 0x400>; + /* place holder */ + }; + + wdt2: watchdog@12800400 { + reg = <0 0x12800400 0 0x400>; + /* place holder */ + }; + + ostm0: timer@12801000 { + reg = <0x0 0x12801000 0x0 0x400>; + /* place holder */ + }; + + ostm1: timer@12801400 { + reg = <0x0 0x12801400 0x0 0x400>; + /* place holder */ + }; + + ostm2: timer@12801800 { + reg = <0x0 0x12801800 0x0 0x400>; + /* place holder */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi new file mode 100644 index 000000000000..c448cc6634c1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054.dtsi" + +/ { + compatible = "renesas,r9a07g054l1", "renesas,r9a07g054"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi new file mode 100644 index 000000000000..4d5914bc95d3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L R9A07G054L2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054.dtsi" + +/ { + compatible = "renesas,r9a07g054l2", "renesas,r9a07g054"; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 20/24] arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (18 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 19/24] arm64: dts: renesas: Add initial DTSI for " Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 21/24] arm64: defconfig: Enable ARCH_R9A07G054 Biju Das ` (4 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit f91c4c74796acca0a5a3bde747948a844eb2c30b upstream. Add basic support for the RZ/V2L SMARC EVK (based on R9A07G054L2): - memory - External input clock - CPG - Pin controller - SCIF - GbEthernet - Audio Clock It shares the same carrier board with RZ/G2L with the same pin mapping. Delete the gpio-hog nodes from pinctrl as they will be added later when the functionality has been tested. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220110134659.30424-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a07g054l2-smarc.dts | 25 +++++++++++++++++++ .../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 2 +- .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 2 +- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 2 +- 5 files changed, 30 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 962a66332236..8815c5eb4cfc 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -59,3 +59,5 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb + +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts new file mode 100644 index 000000000000..39ef55bfe0c3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054l2.dtsi" +#include "rzg2l-smarc-som.dtsi" +#include "rzg2l-smarc-pinfunction.dtsi" +#include "rzg2l-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g054l2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054"; +}; + +&pinctrl { + /delete-node/ can0-stb; + /delete-node/ can1-stb; + /delete-node/ gpio-sd0-pwr-en-hog; + /delete-node/ sd0-dev-sel-hog; + /delete-node/ sd1-pwr-en-hog; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index 71d83e447670..2ef217445f72 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC pincontrol parts + * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts * * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 41fdae7ba66b..879375c0395e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC SOM common parts + * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts * * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 46abb29718cc..78034f36156d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC EVK common parts + * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts * * Copyright (C) 2021 Renesas Electronics Corp. */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 21/24] arm64: defconfig: Enable ARCH_R9A07G054 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (19 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 20/24] arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 22/24] arm64: dts: renesas: rzg2l-smarc: Add common dtsi file Biju Das ` (3 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit ca9df4a75a208f3294a9a09b84ffa1bc89d3e0df upstream. Enable support for the Renesas RZ/V2L SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220308140033.10501-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58a79a3e1cd0..7975a4b6a84a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -963,6 +963,7 @@ CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y CONFIG_ARCH_R9A07G044=y +CONFIG_ARCH_R9A07G054=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 22/24] arm64: dts: renesas: rzg2l-smarc: Add common dtsi file 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (20 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 21/24] arm64: defconfig: Enable ARCH_R9A07G054 Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 23/24] arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings Biju Das ` (2 subsequent siblings) 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 726fd781195dc99cdcb60b2678694bfa5ccd1825 upstream. RZ/{G2L,V2L} and G2LC SoC use the same carrier board, but the SoM is different. Different pin mapping is possible on SoM. For eg:- RZ/G2L SMARC EVK uses SCIF2, whereas RZ/G2LC uses SCIF1 for the serial interface available on PMOD1. This patch adds support for handling the pin mapping differences by moving definitions common to RZ/G2L and RZ/G2LC to a common dtsi file. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220203170636.7747-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/r9a07g044c2-smarc.dts | 9 +- .../boot/dts/renesas/r9a07g044l2-smarc.dts | 1 + .../boot/dts/renesas/r9a07g054l2-smarc.dts | 1 + .../boot/dts/renesas/rz-smarc-common.dtsi | 207 ++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 193 ---------------- 5 files changed, 210 insertions(+), 201 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 8d671111d973..af84fd6c8a81 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -9,12 +9,11 @@ #include "r9a07g044c2.dtsi" #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc-pinfunction.dtsi" -#include "rzg2l-smarc.dtsi" +#include "rz-smarc-common.dtsi" / { model = "Renesas SMARC EVK based on r9a07g044c2"; compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; - }; &canfd { @@ -75,12 +74,6 @@ &phyrst { status = "disabled"; }; -&scif2 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index 886d38886d05..bc2af6c92ccd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -9,6 +9,7 @@ #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" #include "rzg2l-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 39ef55bfe0c3..49d141db53f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -9,6 +9,7 @@ #include "r9a07g054l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" #include "rzg2l-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi new file mode 100644 index 000000000000..588117aafaca --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/* + * SSI-WM8978 + * + * This command is required when Playback/Capture + * + * amixer cset name='Left Input Mixer L2 Switch' on + * amixer cset name='Right Input Mixer R2 Switch' on + * amixer cset name='Headphone Playback Volume' 100 + * amixer cset name='PCM Volume' 100% + * amixer cset name='Input PGA Volume' 25 + * + */ + +/ { + aliases { + serial0 = &scif0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c3 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + audio_mclock: audio_mclock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + snd_rzg2l: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "L2", "Mic Bias", + "R2", "Mic Bias", + "Mic Bias", "Microphone Jack"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi0>; + }; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_mclock>; + sound-dai = <&wm8978>; + }; + }; + + usb0_vbus_otg: regulator-usb0-vbus-otg { + compatible = "regulator-fixed"; + + regulator-name = "USB0_VBUS_OTG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +}; + +&audio_clk1{ + clock-frequency = <11289600>; +}; + +&audio_clk2{ + clock-frequency = <12288000>; +}; + +&canfd { + pinctrl-0 = <&can0_pins &can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&phyrst { + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&usb0_vbus_otg>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 78034f36156d..33ddfd18bd56 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -8,164 +8,13 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> -/* - * SSI-WM8978 - * - * This command is required when Playback/Capture - * - * amixer cset name='Left Input Mixer L2 Switch' on - * amixer cset name='Right Input Mixer R2 Switch' on - * amixer cset name='Headphone Playback Volume' 100 - * amixer cset name='PCM Volume' 100% - * amixer cset name='Input PGA Volume' 25 - * - */ - /* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ #define PMOD1_SER0 1 / { aliases { - serial0 = &scif0; serial1 = &scif2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c3 = &i2c3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - audio_mclock: audio_mclock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - snd_rzg2l: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&cpu_dai>; - simple-audio-card,frame-master = <&cpu_dai>; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,widgets = "Microphone", "Microphone Jack"; - simple-audio-card,routing = - "L2", "Mic Bias", - "R2", "Mic Bias", - "Mic Bias", "Microphone Jack"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi0>; - }; - - codec_dai: simple-audio-card,codec { - clocks = <&audio_mclock>; - sound-dai = <&wm8978>; - }; - }; - - usb0_vbus_otg: regulator-usb0-vbus-otg { - compatible = "regulator-fixed"; - - regulator-name = "USB0_VBUS_OTG"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&audio_clk1{ - clock-frequency = <11289600>; -}; - -&audio_clk2{ - clock-frequency = <12288000>; -}; - -&canfd { - pinctrl-0 = <&can0_pins &can1_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; }; - - channel1 { - status = "okay"; - }; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&phyrst { - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - status = "okay"; }; /* @@ -184,45 +33,3 @@ &scif2 { status = "okay"; }; #endif - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi1>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&spi1 { - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&ssi0 { - pinctrl-0 = <&ssi0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&usb0_vbus_otg>; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 23/24] arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (21 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 22/24] arm64: dts: renesas: rzg2l-smarc: Add common dtsi file Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 11:08 ` [PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board Biju Das 2022-08-02 16:56 ` [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Pavel Machek 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit 2ed3b5d9540b246d7a1ec98971914ee810b40086 upstream. RZ/G2LC SoM uses DIP-SWitch SW1 for various pin multiplexing functions. This patch describes DIP-SWitch SW1 settings on SoM and adds the corresponding macros for enabling pinmux functionality on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220203170636.7747-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../boot/dts/renesas/r9a07g044c2-smarc.dts | 4 +-- arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index af84fd6c8a81..50abdabc374a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -7,9 +7,7 @@ /dts-v1/; #include "r9a07g044c2.dtsi" -#include "rzg2lc-smarc-som.dtsi" -#include "rzg2lc-smarc-pinfunction.dtsi" -#include "rz-smarc-common.dtsi" +#include "rzg2lc-smarc.dtsi" / { model = "Renesas SMARC EVK based on r9a07g044c2"; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi new file mode 100644 index 000000000000..ca5ca7ce6692 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC EVK parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/* + * DIP-Switch SW1 setting on SoM + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) + * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) + * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) + * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) + * Please change below macros according to SW1 setting + */ + +#define SW_SCIF_CAN 0 +#if (SW_SCIF_CAN) +/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ +#define SW_RSPI_CAN 0 +#else +/* Please set SW_RSPI_CAN. Default value is 1 */ +#define SW_RSPI_CAN 1 +#endif + +#if (SW_SCIF_CAN & SW_RSPI_CAN) +#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" +#endif + +#include "rzg2lc-smarc-som.dtsi" +#include "rzg2lc-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (22 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 23/24] arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings Biju Das @ 2022-08-02 11:08 ` Biju Das 2022-08-02 16:56 ` [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Pavel Machek 24 siblings, 0 replies; 33+ messages in thread From: Biju Das @ 2022-08-02 11:08 UTC (permalink / raw) To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, Lad Prabhakar, Biju Das, cip-dev commit fa00d6dc19283bee13f0390546f741293f6d2d9a upstream. SCIF1 interface is available on PMOD1 connector (CN7) on carrier board. This patch adds pinmux and scif1 node to carrier board dtsi file for RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220203170636.7747-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 26 +++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 1032f6563515..ec9e08ec0822 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -17,6 +17,13 @@ scif0_pins: scif0 { <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ }; + scif1_pins: scif1 { + pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ + <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ + <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index ca5ca7ce6692..1b59ef376296 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -34,3 +34,29 @@ #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" + +/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/ { + aliases { + serial1 = &scif1; + }; +}; + +/* + * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board + * SW1 should be at position 2->3 so that SER0_CTS# line is activated + * SW2 should be at position 2->3 so that SER0_TX line is activated + * SW3 should be at position 2->3 so that SER0_RX line is activated + * SW4 should be at position 2->3 so that SER0_RTS# line is activated + */ +#if (!SW_SCIF_CAN && PMOD1_SER0) +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; +#endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support 2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das ` (23 preceding siblings ...) 2022-08-02 11:08 ` [PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board Biju Das @ 2022-08-02 16:56 ` Pavel Machek 2022-08-03 8:07 ` nobuhiro1.iwamatsu 24 siblings, 1 reply; 33+ messages in thread From: Pavel Machek @ 2022-08-02 16:56 UTC (permalink / raw) To: Biju Das; +Cc: Pavel Machek, nobuhiro1.iwamatsu, Lad Prabhakar, cip-dev [-- Attachment #1: Type: text/plain, Size: 577 bytes --] Hi! > This patch series aims to add Basic board support for SMARC EVK > based on RZ/G2LC and RZ/V2L SoC. RZ/{G2L, G2LC, V2L} share the same > SMARC EVK board, but SoM is different and pin mapping of SoM > module is different. > > All these patches are cherry-picked from the mainline. Series looks okay to me. I can apply it if there are no other commands (and if it passes testing). Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support 2022-08-02 16:56 ` [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Pavel Machek @ 2022-08-03 8:07 ` nobuhiro1.iwamatsu 2022-08-03 13:50 ` Pavel Machek 0 siblings, 1 reply; 33+ messages in thread From: nobuhiro1.iwamatsu @ 2022-08-03 8:07 UTC (permalink / raw) To: pavel, biju.das.jz; +Cc: prabhakar.mahadev-lad.rj, cip-dev Hi all, > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: Wednesday, August 3, 2022 1:57 AM > To: Biju Das <biju.das.jz@bp.renesas.com> > Cc: Pavel Machek <pavel@denx.de>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ > ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org > Subject: Re: [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support > > Hi! > > > This patch series aims to add Basic board support for SMARC EVK based > > on RZ/G2LC and RZ/V2L SoC. RZ/{G2L, G2LC, V2L} share the same SMARC > > EVK board, but SoM is different and pin mapping of SoM module is > > different. > > > > All these patches are cherry-picked from the mainline. > > Series looks okay to me. I can apply it if there are no other commands (and if it > passes testing). > I reviewed this series, LGTM. Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Pavel, please push to git.kernel.org. Best regards, Nobuhiro ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support 2022-08-03 8:07 ` nobuhiro1.iwamatsu @ 2022-08-03 13:50 ` Pavel Machek 0 siblings, 0 replies; 33+ messages in thread From: Pavel Machek @ 2022-08-03 13:50 UTC (permalink / raw) To: nobuhiro1.iwamatsu; +Cc: pavel, biju.das.jz, prabhakar.mahadev-lad.rj, cip-dev [-- Attachment #1: Type: text/plain, Size: 1260 bytes --] Hi! > > From: Pavel Machek <pavel@denx.de> > > Sent: Wednesday, August 3, 2022 1:57 AM > > To: Biju Das <biju.das.jz@bp.renesas.com> > > Cc: Pavel Machek <pavel@denx.de>; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ > > ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com>; cip-dev@lists.cip-project.org > > Subject: Re: [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support > > > > Hi! > > > > > This patch series aims to add Basic board support for SMARC EVK based > > > on RZ/G2LC and RZ/V2L SoC. RZ/{G2L, G2LC, V2L} share the same SMARC > > > EVK board, but SoM is different and pin mapping of SoM module is > > > different. > > > > > > All these patches are cherry-picked from the mainline. > > > > Series looks okay to me. I can apply it if there are no other commands (and if it > > passes testing). > > > > I reviewed this series, LGTM. > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> > > Pavel, please push to git.kernel.org. Done, thank you for the review. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2022-08-03 13:51 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz follow: Atom feed
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2022-08-02 11:08 [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 01/24] arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 02/24] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK Biju Das
2022-08-02 16:46 ` Pavel Machek
2022-08-03 7:19 ` Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 03/24] arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 04/24] arm64: dts: renesas: rzg2lc-smarc: Enable microSD " Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 05/24] clk: renesas: r9a07g044: Add mux and divider for G clock Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 06/24] clk: renesas: r9a07g044: Add GPU clock and reset entries Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 07/24] clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 08/24] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 09/24] dt-bindings: clock: renesas: Document RZ/V2L SoC Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 10/24] clk: renesas: rzg2l-cpg: Add support for " Biju Das
2022-08-02 16:54 ` Pavel Machek
2022-08-03 7:16 ` Biju Das
2022-08-03 13:50 ` Pavel Machek
2022-08-02 11:08 ` [PATCH 5.10.y-cip 11/24] clk: renesas: rzg2l: Remove unused notifiers Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 12/24] clk: renesas: rzg2l: Simplify multiplication/shift logic Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 13/24] dt-bindings: serial: renesas,scif: Document RZ/V2L SoC Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 14/24] dt-bindings: serial: renesas,sci: " Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 15/24] dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 16/24] pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabled Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 17/24] pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register() Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 18/24] dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 19/24] arm64: dts: renesas: Add initial DTSI for " Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 20/24] arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 21/24] arm64: defconfig: Enable ARCH_R9A07G054 Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 22/24] arm64: dts: renesas: rzg2l-smarc: Add common dtsi file Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 23/24] arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings Biju Das
2022-08-02 11:08 ` [PATCH 5.10.y-cip 24/24] arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board Biju Das
2022-08-02 16:56 ` [PATCH 5.10.y-cip 00/24] Add RZ/{G2LC, V2L} support Pavel Machek
2022-08-03 8:07 ` nobuhiro1.iwamatsu
2022-08-03 13:50 ` Pavel Machek
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