Re: Preparing isar-cip-core for RZ/Five

[Pavel Machek <pavel@denx.de>]

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Hi!

> > Can you check if ldconfig and gcc work for you? That were the
> > roadblocks I was hitting. If they do, I'll be interested in details of
> > your setup.
> 
> Hmm, seems the issue persists:

:-(. Do you get gcc faulting, too?

> root@demo:~# ldconfig                                                                                                                                                                                                                        
> Illegal instruction
> 
> [  297.146728] ldconfig[497]: unhandled signal 4 code 0x1 at 0x00000000000380c8 in ldconfig[10000+83000]
...
> (gdb) disassemble $pc,+0x10
> Dump of assembler code from 0x380c8 to 0x380d8:
> => 0x00000000000380c8:  auipc   a2,0x66
>    0x00000000000380cc:  addi    a2,a2,2000 # 0x9e898
>    0x00000000000380d0:  sd      a0,0(a2)

auipc is something rather simple. a2 = pc + 0x66 << something. Not
sure how it could fault. Plus we get "illegal instruction", suggesting
it is not some other fault.

Could some kind of self-modifying code be involved? I guess some kind
of debugging/watchpoint is not probable.

> Do we have any instruction set restrictions that prevents the usage of 
> distros on this CPU? Under QEMU, we come along here as well and execute 
> this without problems. Some infamous Intel CPU comes to my mind at this 
> point - hope, history does not repeat here....

Which Intel CPU comes to mind? Pentium with its fdiv bug? I'd say
recent ones outdid it :-).

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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