Re: [cip-dev] ldconfig segfault on RZ/Five was Re: Preparing isar-cip-core for RZ/Five

[Pavel Machek <pavel@denx.de>]

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Hi!

(Can I get you to wrap emails at ~72 columns or so?)

> > I did a quick test with the patches pointed by Florian but unfortunately ldconfig still fails.
> 
> I did some experiments on RZ/Five with this issue, and I'm almost positive that there is something wrong (or doesn't work as documented) with the icache handling on this SoC.

>  1. The issue only affects non-PIE executables (there are very few
> of those, basically just ldconfig, gcc, cpp and gcov* on the Debian
> system), and it occurs very early during the execution of the
> program. According to the datasheet, the cache on the ax45mp-1c core
> is virtually indexed, so it is unlikely that a PIE executable will
> ever hit anything in the cache when newly loaded, but it is much
> more likely with non-PIE executables.

Ah, I was wondering what does gcc and ldconfig have in common...

> 2. Setting a breakpoint before the illegal/segfaulting instruction
>doesn't work, and what is executed is clearly not what we're seeing
>through the dcache (the offending instructions are neither illegal,
>nor are they able to cause segfaults), so instruction fetches must
>see something different.

In my testing, I was able to stepi from the start, and then I was able
to put breakpoint at preceding instruction (which was a jump). It
looked like we jumped into the middle of instruction, which would
explain the fault.

Best regards,
								Pavel

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DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
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