From: Pavel Machek <pavel@denx.de>
To: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
tomm.merciai@gmail.com
Subject: Re: [PATCH 6.1.y-cip 13/21] clk: renesas: rzv2h: Add MSTOP support
Date: Fri, 21 Mar 2025 21:10:58 +0100 [thread overview]
Message-ID: <Z93H0jNRuKYCShoZ@duo.ucw.cz> (raw)
In-Reply-To: <20250321110021.3612805-14-tommaso.merciai.xr@bp.renesas.com>
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Hi!
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> commit 9b6e63a777ea5fb85bf24f9cb5ba902eed4f1f2f upstream.
>
> Add MSTOP support to control buses for the individual units on RZ/V2H.
> Use per-bit (instead of group-based) configuration and atomic counters,
> to ensure precise control over individual MSTOP bits, and to prevent
> issues with shared dependencies between module clocks.
>
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -64,6 +68,7 @@
> * @resets: Array of resets
> * @num_resets: Number of Module Resets in info->resets[]
> * @last_dt_core_clk: ID of the last Core Clock exported to DT
> + * @mstop_count: Array of mstop values
> * @rcdev: Reset controller entity
> */
> struct rzv2h_cpg_priv {
> @@ -78,6 +83,8 @@ struct rzv2h_cpg_priv {
> unsigned int num_resets;
> unsigned int last_dt_core_clk;
>
> + atomic_t *mstop_count;
> +
So this one is interesting. There's atomic_t,
> +static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv,
> + u32 mstop_data)
> +{
> + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
> + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
> + unsigned int index = (mstop_index - 1) * 16;
> + atomic_t *mstop = &priv->mstop_count[index];
> + unsigned long flags;
> + unsigned int i;
> + u32 val = 0;
> +
> + spin_lock_irqsave(&priv->rmw_lock, flags);
> + for_each_set_bit(i, &mstop_mask, 16) {
> + if (!atomic_read(&mstop[i]))
> + val |= BIT(i) << 16;
> + atomic_inc(&mstop[i]);
> + }
but then it seems to be accessed under spinlock in all cases. Is
atomic_t needed? If so, comment why we still need the atomic would be
nice.
Best regards,
Pavel
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DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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next prev parent reply other threads:[~2025-03-21 20:11 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-21 11:00 [PATCH 6.1.y-cip 00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 01/21] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 02/21] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 03/21] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 04/21] dt-bindings: clock: renesas: Document RZ/G3E " Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 05/21] clk: renesas: Add family-specific clock driver for RZ/V2H(P) Tommaso Merciai
2025-03-21 20:08 ` Pavel Machek
2025-03-21 11:00 ` [PATCH 6.1.y-cip 06/21] clk: renesas: Add RZ/V2H(P) CPG driver Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 07/21] clk: renesas: rzv2h: Add support for dynamic switching divider clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 08/21] clk: renesas: rzv2h: Add selective Runtime PM support for clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 09/21] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 10/21] clk: renesas: r9a09g057: Add CA55 core clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 11/21] clk: renesas: r9a09g057: Add clock and reset entries for ICU Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 12/21] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 13/21] clk: renesas: rzv2h: Add MSTOP support Tommaso Merciai
2025-03-21 20:10 ` Pavel Machek [this message]
2025-03-21 11:00 ` [PATCH 6.1.y-cip 14/21] clk: renesas: rzv2h: Add support for RZ/G3E SoC Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 15/21] clk: renesas: r9a09g047: Add CA55 core clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 16/21] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 17/21] arm64: dts: renesas: r9a09g047: Add OPP table Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 18/21] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 19/21] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 20/21] soc: renesas: Add RZ/G3E (R9A09G047) config option Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 21/21] arm64: defconfig: Enable R9A09G047 SoC Tommaso Merciai
2025-03-21 20:12 ` [PATCH 6.1.y-cip 00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform Pavel Machek
2025-03-24 9:03 ` Tommaso Merciai
2025-03-24 9:15 ` Pavel Machek
2025-03-26 12:54 ` Pavel Machek
2025-03-26 13:43 ` Tommaso Merciai
2025-03-31 9:07 ` Pavel Machek
2025-03-31 9:54 ` Tommaso Merciai
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