From: Pavel Machek <pavel@denx.de>
To: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
tomm.merciai@gmail.com
Subject: Re: [PATCH 6.1.y-cip 05/21] clk: renesas: Add family-specific clock driver for RZ/V2H(P)
Date: Fri, 21 Mar 2025 21:08:28 +0100 [thread overview]
Message-ID: <Z93HPMEut+5uQsjS@duo.ucw.cz> (raw)
In-Reply-To: <20250321110021.3612805-6-tommaso.merciai.xr@bp.renesas.com>
[-- Attachment #1: Type: text/plain, Size: 1975 bytes --]
Hi!
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> commit dd22e56217495e2d392ded86a1e11a908e424e64 upstream.
>
> Add family-specific clock driver for RZ/V2H(P) SoCs.
> +#include "rzv2h-cpg.h"
> +
> +#ifdef DEBUG
> +#define WARN_DEBUG(x) WARN_ON(x)
> +#else
> +#define WARN_DEBUG(x) do { } while (0)
> +#endif
Normally, we use DEBUG for enabling debug prints, they should not
modify behaviour.
> +static void __init
> +rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
> + struct rzv2h_cpg_priv *priv)
> +{
> + struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
> + unsigned int id = core->id, div = core->div;
> + struct device *dev = priv->dev;
> + const char *parent_name;
> + struct clk_hw *clk_hw;
> +
> + WARN_DEBUG(id >= priv->num_core_clks);
> + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
Are you sure this is safe to do? if id is more than num_core_clock,
we'll still proceed and do out-of-array read/write.
If this truly can not happen, that's okay, but...
...
> + dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
> + priv->clks[id] = clk;
> + return;
> +static void __init
> +rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
> + struct rzv2h_cpg_priv *priv)
> +{
> + struct mod_clock *clock = NULL;
> + struct device *dev = priv->dev;
> + struct clk_init_data init;
> + struct clk *parent, *clk;
> + const char *parent_name;
> + unsigned int id;
> + int ret;
> +
> + id = GET_MOD_CLK_ID(priv->num_core_clks, mod->on_index, mod->on_bit);
> + WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
> + WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
> + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
Same here.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
next prev parent reply other threads:[~2025-03-21 20:08 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-21 11:00 [PATCH 6.1.y-cip 00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 01/21] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 02/21] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 03/21] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 04/21] dt-bindings: clock: renesas: Document RZ/G3E " Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 05/21] clk: renesas: Add family-specific clock driver for RZ/V2H(P) Tommaso Merciai
2025-03-21 20:08 ` Pavel Machek [this message]
2025-03-21 11:00 ` [PATCH 6.1.y-cip 06/21] clk: renesas: Add RZ/V2H(P) CPG driver Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 07/21] clk: renesas: rzv2h: Add support for dynamic switching divider clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 08/21] clk: renesas: rzv2h: Add selective Runtime PM support for clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 09/21] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 10/21] clk: renesas: r9a09g057: Add CA55 core clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 11/21] clk: renesas: r9a09g057: Add clock and reset entries for ICU Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 12/21] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 13/21] clk: renesas: rzv2h: Add MSTOP support Tommaso Merciai
2025-03-21 20:10 ` Pavel Machek
2025-03-21 11:00 ` [PATCH 6.1.y-cip 14/21] clk: renesas: rzv2h: Add support for RZ/G3E SoC Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 15/21] clk: renesas: r9a09g047: Add CA55 core clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 16/21] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 17/21] arm64: dts: renesas: r9a09g047: Add OPP table Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 18/21] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 19/21] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 20/21] soc: renesas: Add RZ/G3E (R9A09G047) config option Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 21/21] arm64: defconfig: Enable R9A09G047 SoC Tommaso Merciai
2025-03-21 20:12 ` [PATCH 6.1.y-cip 00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform Pavel Machek
2025-03-24 9:03 ` Tommaso Merciai
2025-03-24 9:15 ` Pavel Machek
2025-03-26 12:54 ` Pavel Machek
2025-03-26 13:43 ` Tommaso Merciai
2025-03-31 9:07 ` Pavel Machek
2025-03-31 9:54 ` Tommaso Merciai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Z93HPMEut+5uQsjS@duo.ucw.cz \
--to=pavel@denx.de \
--cc=biju.das.jz@bp.renesas.com \
--cc=cip-dev@lists.cip-project.org \
--cc=nobuhiro1.iwamatsu@toshiba.co.jp \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=tomm.merciai@gmail.com \
--cc=tommaso.merciai.xr@bp.renesas.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox