Re: [PATCH 6.1.y-cip 04/85] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG

Pavel Machek
2025-03-14T10:08:44Z

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Hi!

> Document the device tree bindings for the Renesas RZ/G3E SoC
> Clock Pulse Generator (CPG).
>
> Also define constants for the core clocks of the RZ/G3E SoC.
>

> --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> @@ -4,19 +4,22 @@
> $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
> +title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
>
> maintainers:
> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> description:
> - On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
> - and control of clock signals for the IP modules, generation and control of resets,
> - and control over booting, low power consumption and power supply domains.
> + On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
> + generation and control of clock signals for the IP modules, generation and
> + control of resets, and control over booting, low power consumption and power

", and" -> ",".

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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