Re: [PATCH 6.1.y-cip 03/85] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG

Pavel Machek
2025-03-14T10:07:54Z

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Hi!

> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> commit afec1aba08607b18cfd00fdcd6525aeca0e187bf upstream.
>
> Document the device tree bindings for the Renesas RZ/V2H(P) SoC
> Clock Pulse Generator (CPG).
>
> CPG block handles the below operations:
> - Generation and control of clock signals for the IP modules
> - Generation and control of resets
> - Control over booting
> - Low power consumption and power supply domains
>
> Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the
> core clocks are a subset of the ones which are listed as part of section
> 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register.
>
> Signed-off-by: Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com>

> +description:
> + On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
> + and control of clock signals for the IP modules, generation and control of resets,
> + and control over booting, low power consumption and power supply domains.

", and" -- probably delete and.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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