Re: [PATCH 6.1.y-cip 07/85] clk: renesas: rzv2h: Add support for dynamic switching divider clocks

Pavel Machek
2025-03-14T10:14:14Z

[-- Attachment #1: Type: text/plain, Size: 1648 bytes --]

Hi!

> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> commit bc4d25fdfadfa80dc3ba690792b5220d50ea7b52 upstream.
>
> Add support for dynamic switching divider clocks.

> +++ b/drivers/clk/renesas/rzv2h-cpg.c

> +static int rzv2h_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + struct ddiv_clk *ddiv = to_ddiv_clock(divider);
> + struct rzv2h_cpg_priv *priv = ddiv->priv;
> + unsigned long flags = 0;
> + int value;
> + u32 val;
> + int ret;
> +
> + value = divider_get_val(rate, parent_rate, divider->table,
> + divider->width, divider->flags);
> + if (value < 0)
> + return value;
> +
> + spin_lock_irqsave(divider->lock, flags);
> +
> + ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
> + if (ret)
> + goto ddiv_timeout;
> +
> + val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift);
> + val &= ~(clk_div_mask(divider->width) << divider->shift);
> + val |= (u32)value << divider->shift;
> + writel(val, divider->reg);
> +
> + ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
v-- from here
> + if (ret)
> + goto ddiv_timeout;
> +
> + spin_unlock_irqrestore(divider->lock, flags);
> +
> + return 0;
> +
^-- to here
> +ddiv_timeout:
> + spin_unlock_irqrestore(divider->lock, flags);
> + return ret;
> +}

Marked code can be simply deleted.

Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]