* [PATCH 6.1.y-cip 01/85] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 02/85] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK Tommaso Merciai
` (84 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit ceaa1428e197d9d273ceaf60b8a7bbb3a60565b3 upstream.
Document Renesas RZ/G3E (R9A09G047) SoC variants.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/arm/renesas.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index 4eee12b5d67c..8de30b478d18 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -485,6 +485,19 @@ properties:
- const: renesas,r9a08g045s33 # PCIe support
- const: renesas,r9a08g045
+ - description: RZ/G3E (R9A09G047)
+ items:
+ - enum:
+ - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
+ - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
+ - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
+ - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
+ - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
+ - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
+ - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
+ - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
+ - const: renesas,r9a09g047
+
additionalProperties: true
...
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 02/85] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 01/85] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 03/85] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Tommaso Merciai
` (83 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 2bf1a3ca1df7ed93e5ac82ff672753a4edbb6e80 upstream.
Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is based
on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II EVK
consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board.
The SoM module sits on top of the carrier board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index 8de30b478d18..05a96ac138b8 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -487,6 +487,10 @@ properties:
- description: RZ/G3E (R9A09G047)
items:
+ - enum:
+ - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
+ - enum:
+ - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
- enum:
- renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
- renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 03/85] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 01/85] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 02/85] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-14 10:07 ` Pavel Machek
2025-03-12 11:21 ` [PATCH 6.1.y-cip 04/85] dt-bindings: clock: renesas: Document RZ/G3E " Tommaso Merciai
` (82 subsequent siblings)
85 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit afec1aba08607b18cfd00fdcd6525aeca0e187bf upstream.
Document the device tree bindings for the Renesas RZ/V2H(P) SoC
Clock Pulse Generator (CPG).
CPG block handles the below operations:
- Generation and control of clock signals for the IP modules
- Generation and control of resets
- Control over booting
- Low power consumption and power supply domains
Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the
core clocks are a subset of the ones which are listed as part of section
4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../bindings/clock/renesas,rzv2h-cpg.yaml | 80 +++++++++++++++++++
.../dt-bindings/clock/renesas,r9a09g057-cpg.h | 21 +++++
2 files changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
create mode 100644 include/dt-bindings/clock/renesas,r9a09g057-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
new file mode 100644
index 000000000000..926c503bed1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description:
+ On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
+ and control of clock signals for the IP modules, generation and control of resets,
+ and control over booting, low power consumption and power supply domains.
+
+properties:
+ compatible:
+ const: renesas,r9a09g057-cpg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AUDIO_EXTAL clock input
+ - description: RTXIN clock input
+ - description: QEXTAL clock input
+
+ clock-names:
+ items:
+ - const: audio_extal
+ - const: rtxin
+ - const: qextal
+
+ '#clock-cells':
+ description: |
+ - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+ and a core clock reference, as defined in
+ <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
+ - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+ a module number. The module number is calculated as the CLKON register
+ offset index multiplied by 16, plus the actual bit in the register
+ used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
+ calculation is (1 * 16 + 3) = 0x13.
+ const: 2
+
+ '#power-domain-cells':
+ const: 0
+
+ '#reset-cells':
+ description:
+ The single reset specifier cell must be the reset number. The reset number
+ is calculated as the reset register offset index multiplied by 16, plus the
+ actual bit in the register used to reset the specific IP block. For example,
+ for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#power-domain-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@10420000 {
+ compatible = "renesas,r9a09g057-cpg";
+ reg = <0x10420000 0x10000>;
+ clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+ clock-names = "audio_extal", "rtxin", "qextal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
new file mode 100644
index 000000000000..541e6d719bd6
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Core Clock list */
+#define R9A09G057_SYS_0_PCLK 0
+#define R9A09G057_CA55_0_CORE_CLK0 1
+#define R9A09G057_CA55_0_CORE_CLK1 2
+#define R9A09G057_CA55_0_CORE_CLK2 3
+#define R9A09G057_CA55_0_CORE_CLK3 4
+#define R9A09G057_CA55_0_PERIPHCLK 5
+#define R9A09G057_CM33_CLK0 6
+#define R9A09G057_CST_0_SWCLKTCK 7
+#define R9A09G057_IOTOP_0_SHCLK 8
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 03/85] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
2025-03-12 11:21 ` [PATCH 6.1.y-cip 03/85] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Tommaso Merciai
@ 2025-03-14 10:07 ` Pavel Machek
0 siblings, 0 replies; 104+ messages in thread
From: Pavel Machek @ 2025-03-14 10:07 UTC (permalink / raw)
To: Tommaso Merciai
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 1267 bytes --]
Hi!
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> commit afec1aba08607b18cfd00fdcd6525aeca0e187bf upstream.
>
> Document the device tree bindings for the Renesas RZ/V2H(P) SoC
> Clock Pulse Generator (CPG).
>
> CPG block handles the below operations:
> - Generation and control of clock signals for the IP modules
> - Generation and control of resets
> - Control over booting
> - Low power consumption and power supply domains
>
> Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the
> core clocks are a subset of the ones which are listed as part of section
> 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register.
>
> Signed-off-by: Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +description:
> + On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
> + and control of clock signals for the IP modules, generation and control of resets,
> + and control over booting, low power consumption and power supply domains.
", and" -- probably delete and.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread
* [PATCH 6.1.y-cip 04/85] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (2 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 03/85] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-14 10:08 ` Pavel Machek
2025-03-12 11:21 ` [PATCH 6.1.y-cip 05/85] clk: renesas: Add family-specific clock driver for RZ/V2H(P) Tommaso Merciai
` (81 subsequent siblings)
85 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 25458fdd39a18a5ce00c36f38992da54bb7453f3 upstream.
Document the device tree bindings for the Renesas RZ/G3E SoC
Clock Pulse Generator (CPG).
Also define constants for the core clocks of the RZ/G3E SoC.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../bindings/clock/renesas,rzv2h-cpg.yaml | 15 +++++++------
.../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 +++++++++++++++++++
2 files changed, 30 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
index 926c503bed1f..c3fe76abd549 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -4,19 +4,22 @@
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
+title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
- On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
- and control of clock signals for the IP modules, generation and control of resets,
- and control over booting, low power consumption and power supply domains.
+ On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
+ generation and control of clock signals for the IP modules, generation and
+ control of resets, and control over booting, low power consumption and power
+ supply domains.
properties:
compatible:
- const: renesas,r9a09g057-cpg
+ enum:
+ - renesas,r9a09g047-cpg # RZ/G3E
+ - renesas,r9a09g057-cpg # RZ/V2H
reg:
maxItems: 1
@@ -37,7 +40,7 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
- <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
+ <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number. The module number is calculated as the CLKON register
offset index multiplied by 16, plus the actual bit in the register
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
new file mode 100644
index 000000000000..1d031bf6bf03
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Core Clock list */
+#define R9A09G047_SYS_0_PCLK 0
+#define R9A09G047_CA55_0_CORECLK0 1
+#define R9A09G047_CA55_0_CORECLK1 2
+#define R9A09G047_CA55_0_CORECLK2 3
+#define R9A09G047_CA55_0_CORECLK3 4
+#define R9A09G047_CA55_0_PERIPHCLK 5
+#define R9A09G047_CM33_CLK0 6
+#define R9A09G047_CST_0_SWCLKTCK 7
+#define R9A09G047_IOTOP_0_SHCLK 8
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 04/85] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
2025-03-12 11:21 ` [PATCH 6.1.y-cip 04/85] dt-bindings: clock: renesas: Document RZ/G3E " Tommaso Merciai
@ 2025-03-14 10:08 ` Pavel Machek
0 siblings, 0 replies; 104+ messages in thread
From: Pavel Machek @ 2025-03-14 10:08 UTC (permalink / raw)
To: Tommaso Merciai
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 1397 bytes --]
Hi!
> Document the device tree bindings for the Renesas RZ/G3E SoC
> Clock Pulse Generator (CPG).
>
> Also define constants for the core clocks of the RZ/G3E SoC.
>
> --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> @@ -4,19 +4,22 @@
> $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
> +title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
>
> maintainers:
> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> description:
> - On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
> - and control of clock signals for the IP modules, generation and control of resets,
> - and control over booting, low power consumption and power supply domains.
> + On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
> + generation and control of clock signals for the IP modules, generation and
> + control of resets, and control over booting, low power consumption and power
", and" -> ",".
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread
* [PATCH 6.1.y-cip 05/85] clk: renesas: Add family-specific clock driver for RZ/V2H(P)
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (3 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 04/85] dt-bindings: clock: renesas: Document RZ/G3E " Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-14 10:12 ` Pavel Machek
2025-03-12 11:21 ` [PATCH 6.1.y-cip 06/85] clk: renesas: Add RZ/V2H(P) CPG driver Tommaso Merciai
` (80 subsequent siblings)
85 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit dd22e56217495e2d392ded86a1e11a908e424e64 upstream.
Add family-specific clock driver for RZ/V2H(P) SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240729202645.263525-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/Kconfig | 4 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/rzv2h-cpg.c | 684 ++++++++++++++++++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.h | 149 +++++++
4 files changed, 838 insertions(+)
create mode 100644 drivers/clk/renesas/rzv2h-cpg.c
create mode 100644 drivers/clk/renesas/rzv2h-cpg.h
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 04593172392e..5bb7ce115d74 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -228,6 +228,10 @@ config CLK_RENESAS_VBATTB
depends on ARCH_RZG2L || COMPILE_TEST
select RESET_CONTROLLER
+config CLK_RZV2H
+ bool "RZ/V2H(P) family clock support" if COMPILE_TEST
+ select RESET_CONTROLLER
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 46bdcbcbf183..20fee1e834dc 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
obj-$(CONFIG_CLK_RCAR_GEN4_CPG) += rcar-gen4-cpg.o
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
+obj-$(CONFIG_CLK_RZV2H) += rzv2h-cpg.o
# Generic
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
new file mode 100644
index 000000000000..9a568020f61f
--- /dev/null
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -0,0 +1,684 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/V2H(P) Clock Pulse Generator
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ * Based on rzg2l-cpg.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2013 Ideas On Board SPRL
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/iopoll.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+#include "rzv2h-cpg.h"
+
+#ifdef DEBUG
+#define WARN_DEBUG(x) WARN_ON(x)
+#else
+#define WARN_DEBUG(x) do { } while (0)
+#endif
+
+#define GET_CLK_ON_OFFSET(x) (0x600 + ((x) * 4))
+#define GET_CLK_MON_OFFSET(x) (0x800 + ((x) * 4))
+#define GET_RST_OFFSET(x) (0x900 + ((x) * 4))
+#define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4))
+
+#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val)))
+#define MDIV(val) FIELD_GET(GENMASK(15, 6), (val))
+#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
+#define SDIV(val) FIELD_GET(GENMASK(2, 0), (val))
+
+#define GET_MOD_CLK_ID(base, index, bit) \
+ ((base) + ((((index) * (16))) + (bit)))
+
+/**
+ * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
+ *
+ * @dev: CPG device
+ * @base: CPG register block base address
+ * @clks: Array containing all Core and Module Clocks
+ * @num_core_clks: Number of Core Clocks in clks[]
+ * @num_mod_clks: Number of Module Clocks in clks[]
+ * @resets: Array of resets
+ * @num_resets: Number of Module Resets in info->resets[]
+ * @last_dt_core_clk: ID of the last Core Clock exported to DT
+ * @rcdev: Reset controller entity
+ */
+struct rzv2h_cpg_priv {
+ struct device *dev;
+ void __iomem *base;
+
+ struct clk **clks;
+ unsigned int num_core_clks;
+ unsigned int num_mod_clks;
+ struct rzv2h_reset *resets;
+ unsigned int num_resets;
+ unsigned int last_dt_core_clk;
+
+ struct reset_controller_dev rcdev;
+};
+
+#define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev)
+
+struct pll_clk {
+ struct rzv2h_cpg_priv *priv;
+ void __iomem *base;
+ struct clk_hw hw;
+ unsigned int conf;
+ unsigned int type;
+};
+
+#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
+
+/**
+ * struct mod_clock - Module clock
+ *
+ * @priv: CPG private data
+ * @hw: handle between common and hardware-specific interfaces
+ * @on_index: register offset
+ * @on_bit: ON/MON bit
+ * @mon_index: monitor register offset
+ * @mon_bit: montor bit
+ */
+struct mod_clock {
+ struct rzv2h_cpg_priv *priv;
+ struct clk_hw hw;
+ u8 on_index;
+ u8 on_bit;
+ s8 mon_index;
+ u8 mon_bit;
+};
+
+#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
+
+static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct pll_clk *pll_clk = to_pll(hw);
+ struct rzv2h_cpg_priv *priv = pll_clk->priv;
+ unsigned int clk1, clk2;
+ u64 rate;
+
+ if (!PLL_CLK_ACCESS(pll_clk->conf))
+ return 0;
+
+ clk1 = readl(priv->base + PLL_CLK1_OFFSET(pll_clk->conf));
+ clk2 = readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf));
+
+ rate = mul_u64_u32_shr(parent_rate, (MDIV(clk1) << 16) + KDIV(clk1),
+ 16 + SDIV(clk2));
+
+ return DIV_ROUND_CLOSEST_ULL(rate, PDIV(clk1));
+}
+
+static const struct clk_ops rzv2h_cpg_pll_ops = {
+ .recalc_rate = rzv2h_cpg_pll_clk_recalc_rate,
+};
+
+static struct clk * __init
+rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
+ struct rzv2h_cpg_priv *priv,
+ const struct clk_ops *ops)
+{
+ void __iomem *base = priv->base;
+ struct device *dev = priv->dev;
+ struct clk_init_data init;
+ const struct clk *parent;
+ const char *parent_name;
+ struct pll_clk *pll_clk;
+ int ret;
+
+ parent = priv->clks[core->parent];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+
+ pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
+ if (!pll_clk)
+ return ERR_PTR(-ENOMEM);
+
+ parent_name = __clk_get_name(parent);
+ init.name = core->name;
+ init.ops = ops;
+ init.flags = 0;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ pll_clk->hw.init = &init;
+ pll_clk->conf = core->conf;
+ pll_clk->base = base;
+ pll_clk->priv = priv;
+ pll_clk->type = core->type;
+
+ ret = devm_clk_hw_register(dev, &pll_clk->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return pll_clk->hw.clk;
+}
+
+static struct clk
+*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ unsigned int clkidx = clkspec->args[1];
+ struct rzv2h_cpg_priv *priv = data;
+ struct device *dev = priv->dev;
+ const char *type;
+ struct clk *clk;
+
+ switch (clkspec->args[0]) {
+ case CPG_CORE:
+ type = "core";
+ if (clkidx > priv->last_dt_core_clk) {
+ dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
+ return ERR_PTR(-EINVAL);
+ }
+ clk = priv->clks[clkidx];
+ break;
+
+ case CPG_MOD:
+ type = "module";
+ if (clkidx >= priv->num_mod_clks) {
+ dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
+ return ERR_PTR(-EINVAL);
+ }
+ clk = priv->clks[priv->num_core_clks + clkidx];
+ break;
+
+ default:
+ dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (IS_ERR(clk))
+ dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
+ PTR_ERR(clk));
+ else
+ dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
+ clkspec->args[0], clkspec->args[1], clk,
+ clk_get_rate(clk));
+ return clk;
+}
+
+static void __init
+rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
+ struct rzv2h_cpg_priv *priv)
+{
+ struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
+ unsigned int id = core->id, div = core->div;
+ struct device *dev = priv->dev;
+ const char *parent_name;
+ struct clk_hw *clk_hw;
+
+ WARN_DEBUG(id >= priv->num_core_clks);
+ WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
+
+ switch (core->type) {
+ case CLK_TYPE_IN:
+ clk = of_clk_get_by_name(priv->dev->of_node, core->name);
+ break;
+ case CLK_TYPE_FF:
+ WARN_DEBUG(core->parent >= priv->num_core_clks);
+ parent = priv->clks[core->parent];
+ if (IS_ERR(parent)) {
+ clk = parent;
+ goto fail;
+ }
+
+ parent_name = __clk_get_name(parent);
+ clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name,
+ parent_name, CLK_SET_RATE_PARENT,
+ core->mult, div);
+ if (IS_ERR(clk_hw))
+ clk = ERR_CAST(clk_hw);
+ else
+ clk = clk_hw->clk;
+ break;
+ case CLK_TYPE_PLL:
+ clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops);
+ break;
+ default:
+ goto fail;
+ }
+
+ if (IS_ERR_OR_NULL(clk))
+ goto fail;
+
+ dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
+ priv->clks[id] = clk;
+ return;
+
+fail:
+ dev_err(dev, "Failed to register core clock %s: %ld\n",
+ core->name, PTR_ERR(clk));
+}
+
+static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
+{
+ struct mod_clock *clock = to_mod_clock(hw);
+ unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);
+ struct rzv2h_cpg_priv *priv = clock->priv;
+ u32 bitmask = BIT(clock->on_bit);
+ struct device *dev = priv->dev;
+ u32 value;
+ int error;
+
+ dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
+ enable ? "ON" : "OFF");
+
+ value = bitmask << 16;
+ if (enable)
+ value |= bitmask;
+
+ writel(value, priv->base + reg);
+
+ if (!enable || clock->mon_index < 0)
+ return 0;
+
+ reg = GET_CLK_MON_OFFSET(clock->mon_index);
+ bitmask = BIT(clock->mon_bit);
+ error = readl_poll_timeout_atomic(priv->base + reg, value,
+ value & bitmask, 0, 10);
+ if (error)
+ dev_err(dev, "Failed to enable CLK_ON %p\n",
+ priv->base + reg);
+
+ return error;
+}
+
+static int rzv2h_mod_clock_enable(struct clk_hw *hw)
+{
+ return rzv2h_mod_clock_endisable(hw, true);
+}
+
+static void rzv2h_mod_clock_disable(struct clk_hw *hw)
+{
+ rzv2h_mod_clock_endisable(hw, false);
+}
+
+static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
+{
+ struct mod_clock *clock = to_mod_clock(hw);
+ struct rzv2h_cpg_priv *priv = clock->priv;
+ u32 bitmask;
+ u32 offset;
+
+ if (clock->mon_index >= 0) {
+ offset = GET_CLK_MON_OFFSET(clock->mon_index);
+ bitmask = BIT(clock->mon_bit);
+ } else {
+ offset = GET_CLK_ON_OFFSET(clock->on_index);
+ bitmask = BIT(clock->on_bit);
+ }
+
+ return readl(priv->base + offset) & bitmask;
+}
+
+static const struct clk_ops rzv2h_mod_clock_ops = {
+ .enable = rzv2h_mod_clock_enable,
+ .disable = rzv2h_mod_clock_disable,
+ .is_enabled = rzv2h_mod_clock_is_enabled,
+};
+
+static void __init
+rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
+ struct rzv2h_cpg_priv *priv)
+{
+ struct mod_clock *clock = NULL;
+ struct device *dev = priv->dev;
+ struct clk_init_data init;
+ struct clk *parent, *clk;
+ const char *parent_name;
+ unsigned int id;
+ int ret;
+
+ id = GET_MOD_CLK_ID(priv->num_core_clks, mod->on_index, mod->on_bit);
+ WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
+ WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
+ WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
+
+ parent = priv->clks[mod->parent];
+ if (IS_ERR(parent)) {
+ clk = parent;
+ goto fail;
+ }
+
+ clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
+ if (!clock) {
+ clk = ERR_PTR(-ENOMEM);
+ goto fail;
+ }
+
+ init.name = mod->name;
+ init.ops = &rzv2h_mod_clock_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ if (mod->critical)
+ init.flags |= CLK_IS_CRITICAL;
+
+ parent_name = __clk_get_name(parent);
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ clock->on_index = mod->on_index;
+ clock->on_bit = mod->on_bit;
+ clock->mon_index = mod->mon_index;
+ clock->mon_bit = mod->mon_bit;
+ clock->priv = priv;
+ clock->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &clock->hw);
+ if (ret) {
+ clk = ERR_PTR(ret);
+ goto fail;
+ }
+
+ priv->clks[id] = clock->hw.clk;
+
+ return;
+
+fail:
+ dev_err(dev, "Failed to register module clock %s: %ld\n",
+ mod->name, PTR_ERR(clk));
+}
+
+static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
+ unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
+ u32 mask = BIT(priv->resets[id].reset_bit);
+ u8 monbit = priv->resets[id].mon_bit;
+ u32 value = mask << 16;
+
+ dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);
+
+ writel(value, priv->base + reg);
+
+ reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
+ mask = BIT(monbit);
+
+ return readl_poll_timeout_atomic(priv->base + reg, value,
+ value & mask, 10, 200);
+}
+
+static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
+ unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
+ u32 mask = BIT(priv->resets[id].reset_bit);
+ u8 monbit = priv->resets[id].mon_bit;
+ u32 value = (mask << 16) | mask;
+
+ dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);
+
+ writel(value, priv->base + reg);
+
+ reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
+ mask = BIT(monbit);
+
+ return readl_poll_timeout_atomic(priv->base + reg, value,
+ !(value & mask), 10, 200);
+}
+
+static int rzv2h_cpg_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = rzv2h_cpg_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ return rzv2h_cpg_deassert(rcdev, id);
+}
+
+static int rzv2h_cpg_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
+ unsigned int reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
+ u8 monbit = priv->resets[id].mon_bit;
+
+ return !!(readl(priv->base + reg) & BIT(monbit));
+}
+
+static const struct reset_control_ops rzv2h_cpg_reset_ops = {
+ .reset = rzv2h_cpg_reset,
+ .assert = rzv2h_cpg_assert,
+ .deassert = rzv2h_cpg_deassert,
+ .status = rzv2h_cpg_status,
+};
+
+static int rzv2h_cpg_reset_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *reset_spec)
+{
+ struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
+ unsigned int id = reset_spec->args[0];
+ u8 rst_index = id / 16;
+ u8 rst_bit = id % 16;
+ unsigned int i;
+
+ for (i = 0; i < rcdev->nr_resets; i++) {
+ if (rst_index == priv->resets[i].reset_index &&
+ rst_bit == priv->resets[i].reset_bit)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static int rzv2h_cpg_reset_controller_register(struct rzv2h_cpg_priv *priv)
+{
+ priv->rcdev.ops = &rzv2h_cpg_reset_ops;
+ priv->rcdev.of_node = priv->dev->of_node;
+ priv->rcdev.dev = priv->dev;
+ priv->rcdev.of_reset_n_cells = 1;
+ priv->rcdev.of_xlate = rzv2h_cpg_reset_xlate;
+ priv->rcdev.nr_resets = priv->num_resets;
+
+ return devm_reset_controller_register(priv->dev, &priv->rcdev);
+}
+
+/**
+ * struct rzv2h_cpg_pd - RZ/V2H power domain data structure
+ * @priv: pointer to CPG private data structure
+ * @genpd: generic PM domain
+ */
+struct rzv2h_cpg_pd {
+ struct rzv2h_cpg_priv *priv;
+ struct generic_pm_domain genpd;
+};
+
+static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct of_phandle_args clkspec;
+ bool once = true;
+ struct clk *clk;
+ int error;
+ int i = 0;
+
+ while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
+ &clkspec)) {
+ if (once) {
+ once = false;
+ error = pm_clk_create(dev);
+ if (error) {
+ of_node_put(clkspec.np);
+ goto err;
+ }
+ }
+ clk = of_clk_get_from_provider(&clkspec);
+ of_node_put(clkspec.np);
+ if (IS_ERR(clk)) {
+ error = PTR_ERR(clk);
+ goto fail_destroy;
+ }
+
+ error = pm_clk_add_clk(dev, clk);
+ if (error) {
+ dev_err(dev, "pm_clk_add_clk failed %d\n",
+ error);
+ goto fail_put;
+ }
+ i++;
+ }
+
+ return 0;
+
+fail_put:
+ clk_put(clk);
+
+fail_destroy:
+ pm_clk_destroy(dev);
+err:
+ return error;
+}
+
+static void rzv2h_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
+{
+ if (!pm_clk_no_clocks(dev))
+ pm_clk_destroy(dev);
+}
+
+static void rzv2h_cpg_genpd_remove_simple(void *data)
+{
+ pm_genpd_remove(data);
+}
+
+static int __init rzv2h_cpg_add_pm_domains(struct rzv2h_cpg_priv *priv)
+{
+ struct device *dev = priv->dev;
+ struct device_node *np = dev->of_node;
+ struct rzv2h_cpg_pd *pd;
+ int ret;
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->genpd.name = np->name;
+ pd->priv = priv;
+ pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+ pd->genpd.attach_dev = rzv2h_cpg_attach_dev;
+ pd->genpd.detach_dev = rzv2h_cpg_detach_dev;
+ ret = pm_genpd_init(&pd->genpd, &pm_domain_always_on_gov, false);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(dev, rzv2h_cpg_genpd_remove_simple, &pd->genpd);
+ if (ret)
+ return ret;
+
+ return of_genpd_add_provider_simple(np, &pd->genpd);
+}
+
+static void rzv2h_cpg_del_clk_provider(void *data)
+{
+ of_clk_del_provider(data);
+}
+
+static int __init rzv2h_cpg_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const struct rzv2h_cpg_info *info;
+ struct rzv2h_cpg_priv *priv;
+ unsigned int nclks, i;
+ struct clk **clks;
+ int error;
+
+ info = of_device_get_match_data(dev);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ nclks = info->num_total_core_clks + info->num_hw_mod_clks;
+ clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ return -ENOMEM;
+
+ priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
+ info->num_resets, GFP_KERNEL);
+ if (!priv->resets)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, priv);
+ priv->clks = clks;
+ priv->num_core_clks = info->num_total_core_clks;
+ priv->num_mod_clks = info->num_hw_mod_clks;
+ priv->last_dt_core_clk = info->last_dt_core_clk;
+ priv->num_resets = info->num_resets;
+
+ for (i = 0; i < nclks; i++)
+ clks[i] = ERR_PTR(-ENOENT);
+
+ for (i = 0; i < info->num_core_clks; i++)
+ rzv2h_cpg_register_core_clk(&info->core_clks[i], priv);
+
+ for (i = 0; i < info->num_mod_clks; i++)
+ rzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv);
+
+ error = of_clk_add_provider(np, rzv2h_cpg_clk_src_twocell_get, priv);
+ if (error)
+ return error;
+
+ error = devm_add_action_or_reset(dev, rzv2h_cpg_del_clk_provider, np);
+ if (error)
+ return error;
+
+ error = rzv2h_cpg_add_pm_domains(priv);
+ if (error)
+ return error;
+
+ error = rzv2h_cpg_reset_controller_register(priv);
+ if (error)
+ return error;
+
+ return 0;
+}
+
+static const struct of_device_id rzv2h_cpg_match[] = {
+ { /* sentinel */ }
+};
+
+static struct platform_driver rzv2h_cpg_driver = {
+ .driver = {
+ .name = "rzv2h-cpg",
+ .of_match_table = rzv2h_cpg_match,
+ },
+};
+
+static int __init rzv2h_cpg_init(void)
+{
+ return platform_driver_probe(&rzv2h_cpg_driver, rzv2h_cpg_probe);
+}
+
+subsys_initcall(rzv2h_cpg_init);
+
+MODULE_DESCRIPTION("Renesas RZ/V2H CPG Driver");
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
new file mode 100644
index 000000000000..ab6beaa50296
--- /dev/null
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Renesas RZ/V2H(P) Clock Pulse Generator
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#ifndef __RENESAS_RZV2H_CPG_H__
+#define __RENESAS_RZV2H_CPG_H__
+
+/**
+ * Definitions of CPG Core Clocks
+ *
+ * These include:
+ * - Clock outputs exported to DT
+ * - External input clocks
+ * - Internal CPG clocks
+ */
+struct cpg_core_clk {
+ const char *name;
+ unsigned int id;
+ unsigned int parent;
+ unsigned int div;
+ unsigned int mult;
+ unsigned int type;
+ unsigned int conf;
+};
+
+enum clk_types {
+ /* Generic */
+ CLK_TYPE_IN, /* External Clock Input */
+ CLK_TYPE_FF, /* Fixed Factor Clock */
+ CLK_TYPE_PLL,
+};
+
+/* BIT(31) indicates if CLK1/2 are accessible or not */
+#define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16)))
+#define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0)
+#define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16))
+#define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4))
+
+#define DEF_TYPE(_name, _id, _type...) \
+ { .name = _name, .id = _id, .type = _type }
+#define DEF_BASE(_name, _id, _type, _parent...) \
+ DEF_TYPE(_name, _id, _type, .parent = _parent)
+#define DEF_PLL(_name, _id, _parent, _conf) \
+ DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .conf = _conf)
+#define DEF_INPUT(_name, _id) \
+ DEF_TYPE(_name, _id, CLK_TYPE_IN)
+#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
+
+/**
+ * struct rzv2h_mod_clk - Module Clocks definitions
+ *
+ * @name: handle between common and hardware-specific interfaces
+ * @parent: id of parent clock
+ * @critical: flag to indicate the clock is critical
+ * @on_index: control register index
+ * @on_bit: ON bit
+ * @mon_index: monitor register index
+ * @mon_bit: monitor bit
+ */
+struct rzv2h_mod_clk {
+ const char *name;
+ u16 parent;
+ bool critical;
+ u8 on_index;
+ u8 on_bit;
+ s8 mon_index;
+ u8 mon_bit;
+};
+
+#define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _monindex, _monbit) \
+ { \
+ .name = (_name), \
+ .parent = (_parent), \
+ .critical = (_critical), \
+ .on_index = (_onindex), \
+ .on_bit = (_onbit), \
+ .mon_index = (_monindex), \
+ .mon_bit = (_monbit), \
+ }
+
+#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
+ DEF_MOD_BASE(_name, _parent, false, _onindex, _onbit, _monindex, _monbit)
+
+#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
+ DEF_MOD_BASE(_name, _parent, true, _onindex, _onbit, _monindex, _monbit)
+
+/**
+ * struct rzv2h_reset - Reset definitions
+ *
+ * @reset_index: reset register index
+ * @reset_bit: reset bit
+ * @mon_index: monitor register index
+ * @mon_bit: monitor bit
+ */
+struct rzv2h_reset {
+ u8 reset_index;
+ u8 reset_bit;
+ u8 mon_index;
+ u8 mon_bit;
+};
+
+#define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) \
+ { \
+ .reset_index = (_resindex), \
+ .reset_bit = (_resbit), \
+ .mon_index = (_monindex), \
+ .mon_bit = (_monbit), \
+ }
+
+#define DEF_RST(_resindex, _resbit, _monindex, _monbit) \
+ DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)
+
+/**
+ * struct rzv2h_cpg_info - SoC-specific CPG Description
+ *
+ * @core_clks: Array of Core Clock definitions
+ * @num_core_clks: Number of entries in core_clks[]
+ * @last_dt_core_clk: ID of the last Core Clock exported to DT
+ * @num_total_core_clks: Total number of Core Clocks (exported + internal)
+ *
+ * @mod_clks: Array of Module Clock definitions
+ * @num_mod_clks: Number of entries in mod_clks[]
+ * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
+ *
+ * @resets: Array of Module Reset definitions
+ * @num_resets: Number of entries in resets[]
+ */
+struct rzv2h_cpg_info {
+ /* Core Clocks */
+ const struct cpg_core_clk *core_clks;
+ unsigned int num_core_clks;
+ unsigned int last_dt_core_clk;
+ unsigned int num_total_core_clks;
+
+ /* Module Clocks */
+ const struct rzv2h_mod_clk *mod_clks;
+ unsigned int num_mod_clks;
+ unsigned int num_hw_mod_clks;
+
+ /* Resets */
+ const struct rzv2h_reset *resets;
+ unsigned int num_resets;
+};
+
+#endif /* __RENESAS_RZV2H_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 05/85] clk: renesas: Add family-specific clock driver for RZ/V2H(P)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 05/85] clk: renesas: Add family-specific clock driver for RZ/V2H(P) Tommaso Merciai
@ 2025-03-14 10:12 ` Pavel Machek
2025-03-14 11:09 ` Tommaso Merciai
0 siblings, 1 reply; 104+ messages in thread
From: Pavel Machek @ 2025-03-14 10:12 UTC (permalink / raw)
To: Tommaso Merciai
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 2057 bytes --]
Hi!
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> commit dd22e56217495e2d392ded86a1e11a908e424e64 upstream.
>
> Add family-specific clock driver for RZ/V2H(P) SoCs.
So RZ/V2H... seems to be something different than "RZ/G3E" SoC. Good
place to split the series?
> --- /dev/null
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> +static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
> + unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
> + u32 mask = BIT(priv->resets[id].reset_bit);
> + u8 monbit = priv->resets[id].mon_bit;
> + u32 value = mask << 16;
> +
> + dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);
> +
> + writel(value, priv->base + reg);
> +
> + reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
> + mask = BIT(monbit);
> +
> + return readl_poll_timeout_atomic(priv->base + reg, value,
> + value & mask, 10, 200);
> +}
> +
> +static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
> + unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
> + u32 mask = BIT(priv->resets[id].reset_bit);
> + u8 monbit = priv->resets[id].mon_bit;
> + u32 value = (mask << 16) | mask;
> +
> + dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);
> +
> + writel(value, priv->base + reg);
> +
> + reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
> + mask = BIT(monbit);
> +
> + return readl_poll_timeout_atomic(priv->base + reg, value,
> + !(value & mask), 10, 200);
> +}
Assert&deassert are fairly similar, can you share the code.
(This and the other cleanups are not critical, will not block merge,
but may be worth fixing in mainline).
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 05/85] clk: renesas: Add family-specific clock driver for RZ/V2H(P)
2025-03-14 10:12 ` Pavel Machek
@ 2025-03-14 11:09 ` Tommaso Merciai
0 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-14 11:09 UTC (permalink / raw)
To: Pavel Machek
Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar, tomm.merciai
Hi Pavel,
Thanks for your review.
On Fri, Mar 14, 2025 at 11:12:06AM +0100, Pavel Machek wrote:
> Hi!
>
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > commit dd22e56217495e2d392ded86a1e11a908e424e64 upstream.
> >
> > Add family-specific clock driver for RZ/V2H(P) SoCs.
>
> So RZ/V2H... seems to be something different than "RZ/G3E" SoC. Good
> place to split the series?
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/rzv2h-cpg.c
> > +static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > + struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
> > + unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
> > + u32 mask = BIT(priv->resets[id].reset_bit);
> > + u8 monbit = priv->resets[id].mon_bit;
> > + u32 value = mask << 16;
> > +
> > + dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);
> > +
> > + writel(value, priv->base + reg);
> > +
> > + reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
> > + mask = BIT(monbit);
> > +
> > + return readl_poll_timeout_atomic(priv->base + reg, value,
> > + value & mask, 10, 200);
> > +}
> > +
> > +static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev,
> > + unsigned long id)
> > +{
> > + struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
> > + unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
> > + u32 mask = BIT(priv->resets[id].reset_bit);
> > + u8 monbit = priv->resets[id].mon_bit;
> > + u32 value = (mask << 16) | mask;
> > +
> > + dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);
> > +
> > + writel(value, priv->base + reg);
> > +
> > + reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
> > + mask = BIT(monbit);
> > +
> > + return readl_poll_timeout_atomic(priv->base + reg, value,
> > + !(value & mask), 10, 200);
> > +}
>
> Assert&deassert are fairly similar, can you share the code.
>
> (This and the other cleanups are not critical, will not block merge,
> but may be worth fixing in mainline).
Fully agree I will fix this into mainline first, thanks.
>
> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Regards,
Tommaso
^ permalink raw reply [flat|nested] 104+ messages in thread
* [PATCH 6.1.y-cip 06/85] clk: renesas: Add RZ/V2H(P) CPG driver
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (4 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 05/85] clk: renesas: Add family-specific clock driver for RZ/V2H(P) Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 07/85] clk: renesas: rzv2h: Add support for dynamic switching divider clocks Tommaso Merciai
` (79 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 36932cbc3e6cc95a681568c28bfadd72d7c2e7ce upstream.
Add RZ/V2H(P) CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240729202645.263525-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/Kconfig | 5 ++
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a09g057-cpg.c | 80 +++++++++++++++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.c | 6 +++
drivers/clk/renesas/rzv2h-cpg.h | 2 +
5 files changed, 94 insertions(+)
create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 5bb7ce115d74..688c088a68d9 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -39,6 +39,7 @@ config CLK_RENESAS
select CLK_R9A07G054 if ARCH_R9A07G054
select CLK_R9A08G045 if ARCH_R9A08G045
select CLK_R9A09G011 if ARCH_R9A09G011
+ select CLK_R9A09G057 if ARCH_R9A09G057
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
@@ -188,6 +189,10 @@ config CLK_R9A09G011
bool "RZ/V2M clock support" if COMPILE_TEST
select CLK_RZG2L
+config CLK_R9A09G057
+ bool "RZ/V2H(P) clock support" if COMPILE_TEST
+ select CLK_RZV2H
+
config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 20fee1e834dc..e7ff58c0a480 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
+obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
# Family
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
new file mode 100644
index 000000000000..9722b810e027
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/V2H(P) CPG driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
+
+#include "rzv2h-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK,
+
+ /* External Input Clocks */
+ CLK_AUDIO_EXTAL,
+ CLK_RTXIN,
+ CLK_QEXTAL,
+
+ /* PLL Clocks */
+ CLK_PLLCM33,
+ CLK_PLLDTY,
+ CLK_PLLCA55,
+
+ /* Internal Core Clocks */
+ CLK_PLLCM33_DIV16,
+
+ /* Module Clocks */
+ MOD_CLK_BASE,
+};
+
+static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
+ DEF_INPUT("rtxin", CLK_RTXIN),
+ DEF_INPUT("qextal", CLK_QEXTAL),
+
+ /* PLL Clocks */
+ DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+ DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
+ DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
+
+ /* Internal Core Clocks */
+ DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+
+ /* Core Clocks */
+ DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
+ DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+};
+
+static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
+ DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
+};
+
+static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
+ DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
+};
+
+const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r9a09g057_core_clks,
+ .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r9a09g057_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks),
+ .num_hw_mod_clks = 25 * 16,
+
+ /* Resets */
+ .resets = r9a09g057_resets,
+ .num_resets = ARRAY_SIZE(r9a09g057_resets),
+};
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 9a568020f61f..4e10cc835c63 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -664,6 +664,12 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
}
static const struct of_device_id rzv2h_cpg_match[] = {
+#ifdef CONFIG_CLK_R9A09G057
+ {
+ .compatible = "renesas,r9a09g057-cpg",
+ .data = &r9a09g057_cpg_info,
+ },
+#endif
{ /* sentinel */ }
};
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index ab6beaa50296..6df59e041701 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -146,4 +146,6 @@ struct rzv2h_cpg_info {
unsigned int num_resets;
};
+extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
+
#endif /* __RENESAS_RZV2H_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 07/85] clk: renesas: rzv2h: Add support for dynamic switching divider clocks
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (5 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 06/85] clk: renesas: Add RZ/V2H(P) CPG driver Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-14 10:13 ` Pavel Machek
2025-03-12 11:21 ` [PATCH 6.1.y-cip 08/85] clk: renesas: rzv2h: Add selective Runtime PM support for clocks Tommaso Merciai
` (78 subsequent siblings)
85 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit bc4d25fdfadfa80dc3ba690792b5220d50ea7b52 upstream.
Add support for dynamic switching divider clocks.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828093822.162855-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/rzv2h-cpg.c | 165 +++++++++++++++++++++++++++++++-
drivers/clk/renesas/rzv2h-cpg.h | 39 +++++++-
2 files changed, 201 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 4e10cc835c63..9fa00f5c1237 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -45,14 +45,19 @@
#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
#define SDIV(val) FIELD_GET(GENMASK(2, 0), (val))
+#define DDIV_DIVCTL_WEN(shift) BIT((shift) + 16)
+
#define GET_MOD_CLK_ID(base, index, bit) \
((base) + ((((index) * (16))) + (bit)))
+#define CPG_CLKSTATUS0 (0x700)
+
/**
* struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
*
* @dev: CPG device
* @base: CPG register block base address
+ * @rmw_lock: protects register accesses
* @clks: Array containing all Core and Module Clocks
* @num_core_clks: Number of Core Clocks in clks[]
* @num_mod_clks: Number of Module Clocks in clks[]
@@ -64,6 +69,7 @@
struct rzv2h_cpg_priv {
struct device *dev;
void __iomem *base;
+ spinlock_t rmw_lock;
struct clk **clks;
unsigned int num_core_clks;
@@ -108,6 +114,21 @@ struct mod_clock {
#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
+/**
+ * struct ddiv_clk - DDIV clock
+ *
+ * @priv: CPG private data
+ * @div: divider clk
+ * @mon: monitor bit in CPG_CLKSTATUS0 register
+ */
+struct ddiv_clk {
+ struct rzv2h_cpg_priv *priv;
+ struct clk_divider div;
+ u8 mon;
+};
+
+#define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div)
+
static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -161,7 +182,7 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
init.num_parents = 1;
pll_clk->hw.init = &init;
- pll_clk->conf = core->conf;
+ pll_clk->conf = core->cfg.conf;
pll_clk->base = base;
pll_clk->priv = priv;
pll_clk->type = core->type;
@@ -173,6 +194,143 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
return pll_clk->hw.clk;
}
+static unsigned long rzv2h_ddiv_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int val;
+
+ val = readl(divider->reg) >> divider->shift;
+ val &= clk_div_mask(divider->width);
+
+ return divider_recalc_rate(hw, parent_rate, val, divider->table,
+ divider->flags, divider->width);
+}
+
+static long rzv2h_ddiv_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+
+ return divider_round_rate(hw, rate, prate, divider->table,
+ divider->width, divider->flags);
+}
+
+static int rzv2h_ddiv_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+
+ return divider_determine_rate(hw, req, divider->table, divider->width,
+ divider->flags);
+}
+
+static inline int rzv2h_cpg_wait_ddiv_clk_update_done(void __iomem *base, u8 mon)
+{
+ u32 bitmask = BIT(mon);
+ u32 val;
+
+ return readl_poll_timeout_atomic(base + CPG_CLKSTATUS0, val, !(val & bitmask), 10, 200);
+}
+
+static int rzv2h_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ struct ddiv_clk *ddiv = to_ddiv_clock(divider);
+ struct rzv2h_cpg_priv *priv = ddiv->priv;
+ unsigned long flags = 0;
+ int value;
+ u32 val;
+ int ret;
+
+ value = divider_get_val(rate, parent_rate, divider->table,
+ divider->width, divider->flags);
+ if (value < 0)
+ return value;
+
+ spin_lock_irqsave(divider->lock, flags);
+
+ ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
+ if (ret)
+ goto ddiv_timeout;
+
+ val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift);
+ val &= ~(clk_div_mask(divider->width) << divider->shift);
+ val |= (u32)value << divider->shift;
+ writel(val, divider->reg);
+
+ ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
+ if (ret)
+ goto ddiv_timeout;
+
+ spin_unlock_irqrestore(divider->lock, flags);
+
+ return 0;
+
+ddiv_timeout:
+ spin_unlock_irqrestore(divider->lock, flags);
+ return ret;
+}
+
+static const struct clk_ops rzv2h_ddiv_clk_divider_ops = {
+ .recalc_rate = rzv2h_ddiv_recalc_rate,
+ .round_rate = rzv2h_ddiv_round_rate,
+ .determine_rate = rzv2h_ddiv_determine_rate,
+ .set_rate = rzv2h_ddiv_set_rate,
+};
+
+static struct clk * __init
+rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
+ struct rzv2h_cpg_priv *priv)
+{
+ struct ddiv cfg_ddiv = core->cfg.ddiv;
+ struct clk_init_data init = {};
+ struct device *dev = priv->dev;
+ u8 shift = cfg_ddiv.shift;
+ u8 width = cfg_ddiv.width;
+ const struct clk *parent;
+ const char *parent_name;
+ struct clk_divider *div;
+ struct ddiv_clk *ddiv;
+ int ret;
+
+ parent = priv->clks[core->parent];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+
+ parent_name = __clk_get_name(parent);
+
+ if ((shift + width) > 16)
+ return ERR_PTR(-EINVAL);
+
+ ddiv = devm_kzalloc(priv->dev, sizeof(*ddiv), GFP_KERNEL);
+ if (!ddiv)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = core->name;
+ init.ops = &rzv2h_ddiv_clk_divider_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ ddiv->priv = priv;
+ ddiv->mon = cfg_ddiv.monbit;
+ div = &ddiv->div;
+ div->reg = priv->base + cfg_ddiv.offset;
+ div->shift = shift;
+ div->width = width;
+ div->flags = core->flag;
+ div->lock = &priv->rmw_lock;
+ div->hw.init = &init;
+ div->table = core->dtable;
+
+ ret = devm_clk_hw_register(dev, &div->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return div->hw.clk;
+}
+
static struct clk
*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
void *data)
@@ -254,6 +412,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
case CLK_TYPE_PLL:
clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops);
break;
+ case CLK_TYPE_DDIV:
+ clk = rzv2h_cpg_ddiv_clk_register(core, priv);
+ break;
default:
goto fail;
}
@@ -612,6 +773,8 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
+ spin_lock_init(&priv->rmw_lock);
+
priv->dev = dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 6df59e041701..1c7a979ab790 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -8,6 +8,29 @@
#ifndef __RENESAS_RZV2H_CPG_H__
#define __RENESAS_RZV2H_CPG_H__
+/**
+ * struct ddiv - Structure for dynamic switching divider
+ *
+ * @offset: register offset
+ * @shift: position of the divider bit
+ * @width: width of the divider
+ * @monbit: monitor bit in CPG_CLKSTATUS0 register
+ */
+struct ddiv {
+ unsigned int offset:11;
+ unsigned int shift:4;
+ unsigned int width:4;
+ unsigned int monbit:5;
+};
+
+#define DDIV_PACK(_offset, _shift, _width, _monbit) \
+ ((struct ddiv){ \
+ .offset = _offset, \
+ .shift = _shift, \
+ .width = _width, \
+ .monbit = _monbit \
+ })
+
/**
* Definitions of CPG Core Clocks
*
@@ -23,7 +46,12 @@ struct cpg_core_clk {
unsigned int div;
unsigned int mult;
unsigned int type;
- unsigned int conf;
+ union {
+ unsigned int conf;
+ struct ddiv ddiv;
+ } cfg;
+ const struct clk_div_table *dtable;
+ u32 flag;
};
enum clk_types {
@@ -31,6 +59,7 @@ enum clk_types {
CLK_TYPE_IN, /* External Clock Input */
CLK_TYPE_FF, /* Fixed Factor Clock */
CLK_TYPE_PLL,
+ CLK_TYPE_DDIV, /* Dynamic Switching Divider */
};
/* BIT(31) indicates if CLK1/2 are accessible or not */
@@ -44,11 +73,17 @@ enum clk_types {
#define DEF_BASE(_name, _id, _type, _parent...) \
DEF_TYPE(_name, _id, _type, .parent = _parent)
#define DEF_PLL(_name, _id, _parent, _conf) \
- DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .conf = _conf)
+ DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.conf = _conf)
#define DEF_INPUT(_name, _id) \
DEF_TYPE(_name, _id, CLK_TYPE_IN)
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
+#define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
+ DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
+ .cfg.ddiv = _ddiv_packed, \
+ .parent = _parent, \
+ .dtable = _dtable, \
+ .flag = CLK_DIVIDER_HIWORD_MASK)
/**
* struct rzv2h_mod_clk - Module Clocks definitions
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 07/85] clk: renesas: rzv2h: Add support for dynamic switching divider clocks
2025-03-12 11:21 ` [PATCH 6.1.y-cip 07/85] clk: renesas: rzv2h: Add support for dynamic switching divider clocks Tommaso Merciai
@ 2025-03-14 10:13 ` Pavel Machek
0 siblings, 0 replies; 104+ messages in thread
From: Pavel Machek @ 2025-03-14 10:13 UTC (permalink / raw)
To: Tommaso Merciai
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 1648 bytes --]
Hi!
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> commit bc4d25fdfadfa80dc3ba690792b5220d50ea7b52 upstream.
>
> Add support for dynamic switching divider clocks.
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> +static int rzv2h_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + struct ddiv_clk *ddiv = to_ddiv_clock(divider);
> + struct rzv2h_cpg_priv *priv = ddiv->priv;
> + unsigned long flags = 0;
> + int value;
> + u32 val;
> + int ret;
> +
> + value = divider_get_val(rate, parent_rate, divider->table,
> + divider->width, divider->flags);
> + if (value < 0)
> + return value;
> +
> + spin_lock_irqsave(divider->lock, flags);
> +
> + ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
> + if (ret)
> + goto ddiv_timeout;
> +
> + val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift);
> + val &= ~(clk_div_mask(divider->width) << divider->shift);
> + val |= (u32)value << divider->shift;
> + writel(val, divider->reg);
> +
> + ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
v-- from here
> + if (ret)
> + goto ddiv_timeout;
> +
> + spin_unlock_irqrestore(divider->lock, flags);
> +
> + return 0;
> +
^-- to here
> +ddiv_timeout:
> + spin_unlock_irqrestore(divider->lock, flags);
> + return ret;
> +}
Marked code can be simply deleted.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread
* [PATCH 6.1.y-cip 08/85] clk: renesas: rzv2h: Add selective Runtime PM support for clocks
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (6 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 07/85] clk: renesas: rzv2h: Add support for dynamic switching divider clocks Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-20 8:58 ` Pavel Machek
2025-03-12 11:21 ` [PATCH 6.1.y-cip 09/85] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT Tommaso Merciai
` (77 subsequent siblings)
85 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 03108a2614ecab46af6e0d66f9fd61c0d80587f2 upstream.
Update `rzv2h_cpg_attach_dev` to prevent external and core clocks not tied
to the power domain from being managed by Runtime PM. This ensures that
only clocks originating from the domain are controlled, thereby avoiding
unintended handling of external and core clocks.
Additionally, introduce a `no_pm` flag in `mod_clock` and `rzv2h_mod_clk`
structures to exclude specific clocks from Runtime PM when needed. Some
clocks, such as those in the CRU block, require unique enable/disable
sequences that are incompatible with standard Runtime PM. For example,
the CSI-2 D-PHY clock initialization requires toggling individual clocks,
making Runtime PM unsuitable.
The helper function `rzv2h_cpg_is_pm_clk()` checks whether a clock should
be managed by Runtime PM based on this `no_pm` flag. New macros, such as
`DEF_MOD_NO_PM`, allow straightforward declaration of clocks that bypass
PM.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241202203916.48668-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/rzv2h-cpg.c | 44 ++++++++++++++++++++++++++++++---
drivers/clk/renesas/rzv2h-cpg.h | 12 ++++++---
2 files changed, 49 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 9fa00f5c1237..bbf0b4ee7b26 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -98,6 +98,7 @@ struct pll_clk {
*
* @priv: CPG private data
* @hw: handle between common and hardware-specific interfaces
+ * @no_pm: flag to indicate PM is not supported
* @on_index: register offset
* @on_bit: ON/MON bit
* @mon_index: monitor register offset
@@ -106,6 +107,7 @@ struct pll_clk {
struct mod_clock {
struct rzv2h_cpg_priv *priv;
struct clk_hw hw;
+ bool no_pm;
u8 on_index;
u8 on_bit;
s8 mon_index;
@@ -541,6 +543,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
clock->on_bit = mod->on_bit;
clock->mon_index = mod->mon_index;
clock->mon_bit = mod->mon_bit;
+ clock->no_pm = mod->no_pm;
clock->priv = priv;
clock->hw.init = &init;
@@ -668,17 +671,51 @@ struct rzv2h_cpg_pd {
struct generic_pm_domain genpd;
};
+static bool rzv2h_cpg_is_pm_clk(struct rzv2h_cpg_pd *pd,
+ const struct of_phandle_args *clkspec)
+{
+ if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
+ return false;
+
+ switch (clkspec->args[0]) {
+ case CPG_MOD: {
+ struct rzv2h_cpg_priv *priv = pd->priv;
+ unsigned int id = clkspec->args[1];
+ struct mod_clock *clock;
+
+ if (id >= priv->num_mod_clks)
+ return false;
+
+ if (priv->clks[priv->num_core_clks + id] == ERR_PTR(-ENOENT))
+ return false;
+
+ clock = to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id]));
+
+ return !clock->no_pm;
+ }
+
+ case CPG_CORE:
+ default:
+ return false;
+ }
+}
+
static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
+ struct rzv2h_cpg_pd *pd = container_of(domain, struct rzv2h_cpg_pd, genpd);
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
struct clk *clk;
+ unsigned int i;
int error;
- int i = 0;
- while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
- &clkspec)) {
+ for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {
+ if (!rzv2h_cpg_is_pm_clk(pd, &clkspec)) {
+ of_node_put(clkspec.np);
+ continue;
+ }
+
if (once) {
once = false;
error = pm_clk_create(dev);
@@ -700,7 +737,6 @@ static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device
error);
goto fail_put;
}
- i++;
}
return 0;
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 1c7a979ab790..99bc08bd7cc1 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -91,6 +91,7 @@ enum clk_types {
* @name: handle between common and hardware-specific interfaces
* @parent: id of parent clock
* @critical: flag to indicate the clock is critical
+ * @no_pm: flag to indicate PM is not supported
* @on_index: control register index
* @on_bit: ON bit
* @mon_index: monitor register index
@@ -100,17 +101,19 @@ struct rzv2h_mod_clk {
const char *name;
u16 parent;
bool critical;
+ bool no_pm;
u8 on_index;
u8 on_bit;
s8 mon_index;
u8 mon_bit;
};
-#define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _monindex, _monbit) \
+#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
{ \
.name = (_name), \
.parent = (_parent), \
.critical = (_critical), \
+ .no_pm = (_no_pm), \
.on_index = (_onindex), \
.on_bit = (_onbit), \
.mon_index = (_monindex), \
@@ -118,10 +121,13 @@ struct rzv2h_mod_clk {
}
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
- DEF_MOD_BASE(_name, _parent, false, _onindex, _onbit, _monindex, _monbit)
+ DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
- DEF_MOD_BASE(_name, _parent, true, _onindex, _onbit, _monindex, _monbit)
+ DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
+
+#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
+ DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
/**
* struct rzv2h_reset - Reset definitions
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 08/85] clk: renesas: rzv2h: Add selective Runtime PM support for clocks
2025-03-12 11:21 ` [PATCH 6.1.y-cip 08/85] clk: renesas: rzv2h: Add selective Runtime PM support for clocks Tommaso Merciai
@ 2025-03-20 8:58 ` Pavel Machek
0 siblings, 0 replies; 104+ messages in thread
From: Pavel Machek @ 2025-03-20 8:58 UTC (permalink / raw)
To: Tommaso Merciai
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 1128 bytes --]
Hi!
> +static bool rzv2h_cpg_is_pm_clk(struct rzv2h_cpg_pd *pd,
> + const struct of_phandle_args *clkspec)
> +{
> + if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
> + return false;
> +
> + switch (clkspec->args[0]) {
> + case CPG_MOD: {
> + struct rzv2h_cpg_priv *priv = pd->priv;
> + unsigned int id = clkspec->args[1];
> + struct mod_clock *clock;
> +
> + if (id >= priv->num_mod_clks)
> + return false;
> +
> + if (priv->clks[priv->num_core_clks + id] == ERR_PTR(-ENOENT))
> + return false;
> +
> + clock = to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id]));
> +
> + return !clock->no_pm;
> + }
> +
> + case CPG_CORE:
> + default:
> + return false;
> + }
> +}
Are there more entries likely to be added to the switch? If not, I
guess this should be
if (clkspec->args[0] != CPG_MOD)
return false;
and then getting rid of the switch.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread
* [PATCH 6.1.y-cip 09/85] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (7 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 08/85] clk: renesas: rzv2h: Add selective Runtime PM support for clocks Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 10/85] clk: renesas: r9a09g057: Add CA55 core clocks Tommaso Merciai
` (76 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 3aeccbe08171b79f82fb802393a6324c7b732669 upstream.
Add clock and reset entries for Generic Timer (GTM), I2C Bus Interface
(RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) IP blocks.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828093822.162855-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r9a09g057-cpg.c | 84 +++++++++++++++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.h | 4 ++
2 files changed, 88 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 9722b810e027..3ee32db5c0af 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -25,16 +25,31 @@ enum clk_ids {
/* PLL Clocks */
CLK_PLLCM33,
+ CLK_PLLCLN,
CLK_PLLDTY,
CLK_PLLCA55,
/* Internal Core Clocks */
CLK_PLLCM33_DIV16,
+ CLK_PLLCLN_DIV2,
+ CLK_PLLCLN_DIV8,
+ CLK_PLLCLN_DIV16,
+ CLK_PLLDTY_ACPU,
+ CLK_PLLDTY_ACPU_DIV4,
/* Module Clocks */
MOD_CLK_BASE,
};
+static const struct clk_div_table dtable_2_64[] = {
+ {0, 2},
+ {1, 4},
+ {2, 8},
+ {3, 16},
+ {4, 64},
+ {0, 0},
+};
+
static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -43,23 +58,92 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
/* PLL Clocks */
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+ DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
/* Internal Core Clocks */
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+ DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
+ DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
+ DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
+
+ DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
+ DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+
/* Core Clocks */
DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
};
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
+ DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
+ DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
+ DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
+ DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),
+ DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),
+ DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),
+ DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),
+ DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),
+ DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),
+ DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),
+ DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),
+ DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),
+ DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),
+ DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16),
+ DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17),
+ DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18),
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
+ DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),
+ DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),
+ DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),
+ DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),
+ DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),
+ DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),
+ DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),
+ DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),
+ DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),
+ DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3),
+ DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),
+ DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5),
+ DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
+ DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7),
+ DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8),
+ DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9),
+ DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
+ DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11),
+ DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
+ DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
+ DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
};
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
+ DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
+ DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
+ DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
+ DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
+ DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
+ DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
+ DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
+ DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
+ DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
+ DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
+ DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
+ DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
+ DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
+ DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
+ DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
+ DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
+ DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
+ DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
+ DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
+ DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
+ DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
+ DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
+ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
+ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
};
const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 99bc08bd7cc1..60016b6122a9 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -31,6 +31,10 @@ struct ddiv {
.monbit = _monbit \
})
+#define CPG_CDDIV0 (0x400)
+
+#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
+
/**
* Definitions of CPG Core Clocks
*
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 10/85] clk: renesas: r9a09g057: Add CA55 core clocks
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (8 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 09/85] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 11/85] clk: renesas: r9a09g057: Add clock and reset entries for ICU Tommaso Merciai
` (75 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 8cce33aed0b6383e91bb9d26dae11b1293101381 upstream.
Add CA55 core clocks which are derived from PLLCA55.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240918135957.290101-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r9a09g057-cpg.c | 16 ++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.h | 5 +++++
2 files changed, 21 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 3ee32db5c0af..a426d0aa4592 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -41,6 +41,14 @@ enum clk_ids {
MOD_CLK_BASE,
};
+static const struct clk_div_table dtable_1_8[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
static const struct clk_div_table dtable_2_64[] = {
{0, 2},
{1, 4},
@@ -74,6 +82,14 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
/* Core Clocks */
DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
+ DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55,
+ CDDIV1_DIVCTL0, dtable_1_8),
+ DEF_DDIV("ca55_0_coreclk1", R9A09G057_CA55_0_CORE_CLK1, CLK_PLLCA55,
+ CDDIV1_DIVCTL1, dtable_1_8),
+ DEF_DDIV("ca55_0_coreclk2", R9A09G057_CA55_0_CORE_CLK2, CLK_PLLCA55,
+ CDDIV1_DIVCTL2, dtable_1_8),
+ DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55,
+ CDDIV1_DIVCTL3, dtable_1_8),
DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
};
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 60016b6122a9..0723df4c1134 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -32,8 +32,13 @@ struct ddiv {
})
#define CPG_CDDIV0 (0x400)
+#define CPG_CDDIV1 (0x404)
#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
+#define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4)
+#define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
+#define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
+#define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
/**
* Definitions of CPG Core Clocks
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 11/85] clk: renesas: r9a09g057: Add clock and reset entries for ICU
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (9 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 10/85] clk: renesas: r9a09g057: Add CA55 core clocks Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 12/85] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets Tommaso Merciai
` (74 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
commit 44d13e198cbf031fdb8cb20b6bbbe82adcb951ca upstream.
Add clock and reset entries for the Renesas RZ/V2H(P) ICU IP block.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240930145244.356565-4-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r9a09g057-cpg.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index a426d0aa4592..7c4507fd34e6 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -94,6 +94,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
};
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
+ DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5),
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
@@ -135,6 +136,7 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
};
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
+ DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 12/85] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (10 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 11/85] clk: renesas: r9a09g057: Add clock and reset entries for ICU Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 13/85] clk: renesas: rzv2h: Add MSTOP support Tommaso Merciai
` (73 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit ee47b94102d2eaed23ac60910003cd0f3fade13c upstream.
Add support for the PLLVDO clock and its related CRU clocks and reset
entries in the r9a09g057 CPG driver. Introduce `CLK_PLLVDO` and associated
clocks like `CLK_PLLVDO_CRU0`, `CLK_PLLVDO_CRU1`, `CLK_PLLVDO_CRU2`, and
`CLK_PLLVDO_CRU3`, along with their corresponding dividers.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241202203916.48668-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r9a09g057-cpg.c | 45 +++++++++++++++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.h | 6 ++++
2 files changed, 51 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 7c4507fd34e6..5aa9710aa402 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -28,6 +28,7 @@ enum clk_ids {
CLK_PLLCLN,
CLK_PLLDTY,
CLK_PLLCA55,
+ CLK_PLLVDO,
/* Internal Core Clocks */
CLK_PLLCM33_DIV16,
@@ -35,7 +36,13 @@ enum clk_ids {
CLK_PLLCLN_DIV8,
CLK_PLLCLN_DIV16,
CLK_PLLDTY_ACPU,
+ CLK_PLLDTY_ACPU_DIV2,
CLK_PLLDTY_ACPU_DIV4,
+ CLK_PLLDTY_DIV16,
+ CLK_PLLVDO_CRU0,
+ CLK_PLLVDO_CRU1,
+ CLK_PLLVDO_CRU2,
+ CLK_PLLVDO_CRU3,
/* Module Clocks */
MOD_CLK_BASE,
@@ -49,6 +56,12 @@ static const struct clk_div_table dtable_1_8[] = {
{0, 0},
};
+static const struct clk_div_table dtable_2_4[] = {
+ {0, 2},
+ {1, 4},
+ {0, 0},
+};
+
static const struct clk_div_table dtable_2_64[] = {
{0, 2},
{1, 4},
@@ -69,6 +82,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
+ DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
/* Internal Core Clocks */
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
@@ -78,7 +92,14 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
+ DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+ DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
+
+ DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
+ DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
+ DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
+ DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
/* Core Clocks */
DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -133,6 +154,18 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
+ DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18),
+ DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19),
+ DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20),
+ DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21),
+ DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22),
+ DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23),
+ DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24),
+ DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25),
+ DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26),
+ DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27),
+ DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28),
+ DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29),
};
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -162,6 +195,18 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
+ DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
+ DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
+ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+ DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
+ DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
+ DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
+ DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */
+ DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */
+ DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */
+ DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
+ DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
+ DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
};
const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 0723df4c1134..ed8d2cad3260 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -33,12 +33,18 @@ struct ddiv {
#define CPG_CDDIV0 (0x400)
#define CPG_CDDIV1 (0x404)
+#define CPG_CDDIV3 (0x40C)
+#define CPG_CDDIV4 (0x410)
#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
#define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4)
#define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
#define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
#define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
+#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
+#define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16)
+#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
+#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
/**
* Definitions of CPG Core Clocks
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 13/85] clk: renesas: rzv2h: Add MSTOP support
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (11 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 12/85] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-20 9:02 ` Pavel Machek
2025-03-12 11:21 ` [PATCH 6.1.y-cip 14/85] clk: renesas: rzv2h: Add support for RZ/G3E SoC Tommaso Merciai
` (72 subsequent siblings)
85 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 9b6e63a777ea5fb85bf24f9cb5ba902eed4f1f2f upstream.
Add MSTOP support to control buses for the individual units on RZ/V2H.
Use per-bit (instead of group-based) configuration and atomic counters,
to ensure precise control over individual MSTOP bits, and to prevent
issues with shared dependencies between module clocks.
Co-developed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241213123550.289193-2-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r9a09g057-cpg.c | 155 +++++++++++++++++++---------
drivers/clk/renesas/rzv2h-cpg.c | 146 ++++++++++++++++++++++----
drivers/clk/renesas/rzv2h-cpg.h | 30 ++++--
3 files changed, 252 insertions(+), 79 deletions(-)
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 5aa9710aa402..a45b4020996b 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -115,57 +115,108 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
};
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
- DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5),
- DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
- DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
- DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
- DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),
- DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),
- DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),
- DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),
- DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),
- DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),
- DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),
- DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),
- DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),
- DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),
- DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16),
- DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17),
- DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18),
- DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
- DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),
- DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),
- DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),
- DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),
- DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),
- DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),
- DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),
- DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),
- DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),
- DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3),
- DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),
- DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5),
- DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
- DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7),
- DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8),
- DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9),
- DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
- DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11),
- DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
- DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
- DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
- DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18),
- DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19),
- DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20),
- DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21),
- DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22),
- DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23),
- DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24),
- DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25),
- DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26),
- DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27),
- DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28),
- DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29),
+ DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
+ BUS_MSTOP_NONE),
+ DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
+ BUS_MSTOP(5, BIT(10))),
+ DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
+ BUS_MSTOP(5, BIT(11))),
+ DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
+ BUS_MSTOP(2, BIT(13))),
+ DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
+ BUS_MSTOP(2, BIT(14))),
+ DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
+ BUS_MSTOP(11, BIT(13))),
+ DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
+ BUS_MSTOP(11, BIT(14))),
+ DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
+ BUS_MSTOP(11, BIT(15))),
+ DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
+ BUS_MSTOP(12, BIT(0))),
+ DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
+ BUS_MSTOP(3, BIT(10))),
+ DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
+ BUS_MSTOP(3, BIT(10))),
+ DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
+ BUS_MSTOP(1, BIT(0))),
+ DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
+ BUS_MSTOP(1, BIT(0))),
+ DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
+ BUS_MSTOP(5, BIT(12))),
+ DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
+ BUS_MSTOP(5, BIT(12))),
+ DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
+ BUS_MSTOP(5, BIT(13))),
+ DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
+ BUS_MSTOP(5, BIT(13))),
+ DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
+ BUS_MSTOP(3, BIT(14))),
+ DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
+ BUS_MSTOP(3, BIT(13))),
+ DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
+ BUS_MSTOP(1, BIT(1))),
+ DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
+ BUS_MSTOP(1, BIT(2))),
+ DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
+ BUS_MSTOP(1, BIT(3))),
+ DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
+ BUS_MSTOP(1, BIT(4))),
+ DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
+ BUS_MSTOP(1, BIT(5))),
+ DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
+ BUS_MSTOP(1, BIT(6))),
+ DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
+ BUS_MSTOP(1, BIT(7))),
+ DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
+ BUS_MSTOP(1, BIT(8))),
+ DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
+ BUS_MSTOP(8, BIT(2))),
+ DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
+ BUS_MSTOP(8, BIT(2))),
+ DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
+ BUS_MSTOP(8, BIT(2))),
+ DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
+ BUS_MSTOP(8, BIT(2))),
+ DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
+ BUS_MSTOP(8, BIT(3))),
+ DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
+ BUS_MSTOP(8, BIT(3))),
+ DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
+ BUS_MSTOP(8, BIT(3))),
+ DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
+ BUS_MSTOP(8, BIT(3))),
+ DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
+ BUS_MSTOP(8, BIT(4))),
+ DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
+ BUS_MSTOP(8, BIT(4))),
+ DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
+ BUS_MSTOP(8, BIT(4))),
+ DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
+ BUS_MSTOP(8, BIT(4))),
+ DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
+ BUS_MSTOP(9, BIT(4))),
+ DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
+ BUS_MSTOP(9, BIT(4))),
+ DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
+ BUS_MSTOP(9, BIT(4))),
+ DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
+ BUS_MSTOP(9, BIT(5))),
+ DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
+ BUS_MSTOP(9, BIT(5))),
+ DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
+ BUS_MSTOP(9, BIT(5))),
+ DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
+ BUS_MSTOP(9, BIT(6))),
+ DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
+ BUS_MSTOP(9, BIT(6))),
+ DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
+ BUS_MSTOP(9, BIT(6))),
+ DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
+ BUS_MSTOP(9, BIT(7))),
+ DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
+ BUS_MSTOP(9, BIT(7))),
+ DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
+ BUS_MSTOP(9, BIT(7))),
};
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -224,4 +275,6 @@ const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
/* Resets */
.resets = r9a09g057_resets,
.num_resets = ARRAY_SIZE(r9a09g057_resets),
+
+ .num_mstop_bits = 192,
};
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index bbf0b4ee7b26..6f096abda33c 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -23,6 +23,7 @@
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
+#include <linux/refcount.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
@@ -40,6 +41,9 @@
#define GET_RST_OFFSET(x) (0x900 + ((x) * 4))
#define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4))
+#define CPG_BUS_1_MSTOP (0xd00)
+#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
+
#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val)))
#define MDIV(val) FIELD_GET(GENMASK(15, 6), (val))
#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
@@ -64,6 +68,7 @@
* @resets: Array of resets
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
+ * @mstop_count: Array of mstop values
* @rcdev: Reset controller entity
*/
struct rzv2h_cpg_priv {
@@ -78,6 +83,8 @@ struct rzv2h_cpg_priv {
unsigned int num_resets;
unsigned int last_dt_core_clk;
+ atomic_t *mstop_count;
+
struct reset_controller_dev rcdev;
};
@@ -97,6 +104,7 @@ struct pll_clk {
* struct mod_clock - Module clock
*
* @priv: CPG private data
+ * @mstop_data: mstop data relating to module clock
* @hw: handle between common and hardware-specific interfaces
* @no_pm: flag to indicate PM is not supported
* @on_index: register offset
@@ -106,6 +114,7 @@ struct pll_clk {
*/
struct mod_clock {
struct rzv2h_cpg_priv *priv;
+ unsigned int mstop_data;
struct clk_hw hw;
bool no_pm;
u8 on_index;
@@ -433,8 +442,71 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
core->name, PTR_ERR(clk));
}
+static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv,
+ u32 mstop_data)
+{
+ unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
+ u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
+ unsigned int index = (mstop_index - 1) * 16;
+ atomic_t *mstop = &priv->mstop_count[index];
+ unsigned long flags;
+ unsigned int i;
+ u32 val = 0;
+
+ spin_lock_irqsave(&priv->rmw_lock, flags);
+ for_each_set_bit(i, &mstop_mask, 16) {
+ if (!atomic_read(&mstop[i]))
+ val |= BIT(i) << 16;
+ atomic_inc(&mstop[i]);
+ }
+ if (val)
+ writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
+ spin_unlock_irqrestore(&priv->rmw_lock, flags);
+}
+
+static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
+ u32 mstop_data)
+{
+ unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
+ u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
+ unsigned int index = (mstop_index - 1) * 16;
+ atomic_t *mstop = &priv->mstop_count[index];
+ unsigned long flags;
+ unsigned int i;
+ u32 val = 0;
+
+ spin_lock_irqsave(&priv->rmw_lock, flags);
+ for_each_set_bit(i, &mstop_mask, 16) {
+ if (!atomic_read(&mstop[i]) ||
+ atomic_dec_and_test(&mstop[i]))
+ val |= BIT(i) << 16 | BIT(i);
+ }
+ if (val)
+ writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
+ spin_unlock_irqrestore(&priv->rmw_lock, flags);
+}
+
+static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
+{
+ struct mod_clock *clock = to_mod_clock(hw);
+ struct rzv2h_cpg_priv *priv = clock->priv;
+ u32 bitmask;
+ u32 offset;
+
+ if (clock->mon_index >= 0) {
+ offset = GET_CLK_MON_OFFSET(clock->mon_index);
+ bitmask = BIT(clock->mon_bit);
+ } else {
+ offset = GET_CLK_ON_OFFSET(clock->on_index);
+ bitmask = BIT(clock->on_bit);
+ }
+
+ return readl(priv->base + offset) & bitmask;
+}
+
static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
{
+ bool enabled = rzv2h_mod_clock_is_enabled(hw);
struct mod_clock *clock = to_mod_clock(hw);
unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);
struct rzv2h_cpg_priv *priv = clock->priv;
@@ -446,11 +518,20 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
enable ? "ON" : "OFF");
+ if (enabled == enable)
+ return 0;
+
value = bitmask << 16;
- if (enable)
+ if (enable) {
value |= bitmask;
-
- writel(value, priv->base + reg);
+ writel(value, priv->base + reg);
+ if (clock->mstop_data != BUS_MSTOP_NONE)
+ rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);
+ } else {
+ if (clock->mstop_data != BUS_MSTOP_NONE)
+ rzv2h_mod_clock_mstop_disable(priv, clock->mstop_data);
+ writel(value, priv->base + reg);
+ }
if (!enable || clock->mon_index < 0)
return 0;
@@ -476,24 +557,6 @@ static void rzv2h_mod_clock_disable(struct clk_hw *hw)
rzv2h_mod_clock_endisable(hw, false);
}
-static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
-{
- struct mod_clock *clock = to_mod_clock(hw);
- struct rzv2h_cpg_priv *priv = clock->priv;
- u32 bitmask;
- u32 offset;
-
- if (clock->mon_index >= 0) {
- offset = GET_CLK_MON_OFFSET(clock->mon_index);
- bitmask = BIT(clock->mon_bit);
- } else {
- offset = GET_CLK_ON_OFFSET(clock->on_index);
- bitmask = BIT(clock->on_bit);
- }
-
- return readl(priv->base + offset) & bitmask;
-}
-
static const struct clk_ops rzv2h_mod_clock_ops = {
.enable = rzv2h_mod_clock_enable,
.disable = rzv2h_mod_clock_disable,
@@ -546,6 +609,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
clock->no_pm = mod->no_pm;
clock->priv = priv;
clock->hw.init = &init;
+ clock->mstop_data = mod->mstop_data;
ret = devm_clk_hw_register(dev, &clock->hw);
if (ret) {
@@ -555,6 +619,41 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
priv->clks[id] = clock->hw.clk;
+ /*
+ * Ensure the module clocks and MSTOP bits are synchronized when they are
+ * turned ON by the bootloader. Enable MSTOP bits for module clocks that were
+ * turned ON in an earlier boot stage.
+ */
+ if (clock->mstop_data != BUS_MSTOP_NONE &&
+ !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) {
+ rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);
+ } else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {
+ unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);
+ u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);
+ unsigned int index = (mstop_index - 1) * 16;
+ atomic_t *mstop = &priv->mstop_count[index];
+ unsigned long flags;
+ unsigned int i;
+ u32 val = 0;
+
+ /*
+ * Critical clocks are turned ON immediately upon registration, and the
+ * MSTOP counter is updated through the rzv2h_mod_clock_enable() path.
+ * However, if the critical clocks were already turned ON by the initial
+ * bootloader, synchronize the atomic counter here and clear the MSTOP bit.
+ */
+ spin_lock_irqsave(&priv->rmw_lock, flags);
+ for_each_set_bit(i, &mstop_mask, 16) {
+ if (atomic_read(&mstop[i]))
+ continue;
+ val |= BIT(i) << 16;
+ atomic_inc(&mstop[i]);
+ }
+ if (val)
+ writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
+ spin_unlock_irqrestore(&priv->rmw_lock, flags);
+ }
+
return;
fail:
@@ -822,6 +921,11 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
if (!clks)
return -ENOMEM;
+ priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits,
+ sizeof(*priv->mstop_count), GFP_KERNEL);
+ if (!priv->mstop_count)
+ return -ENOMEM;
+
priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
info->num_resets, GFP_KERNEL);
if (!priv->resets)
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index ed8d2cad3260..dcd65e9c09da 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -8,6 +8,8 @@
#ifndef __RENESAS_RZV2H_CPG_H__
#define __RENESAS_RZV2H_CPG_H__
+#include <linux/bitfield.h>
+
/**
* struct ddiv - Structure for dynamic switching divider
*
@@ -46,6 +48,12 @@ struct ddiv {
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
+#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
+#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
+#define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \
+ FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
+#define BUS_MSTOP_NONE GENMASK(31, 0)
+
/**
* Definitions of CPG Core Clocks
*
@@ -104,6 +112,7 @@ enum clk_types {
* struct rzv2h_mod_clk - Module Clocks definitions
*
* @name: handle between common and hardware-specific interfaces
+ * @mstop_data: packed data mstop register offset and mask
* @parent: id of parent clock
* @critical: flag to indicate the clock is critical
* @no_pm: flag to indicate PM is not supported
@@ -114,6 +123,7 @@ enum clk_types {
*/
struct rzv2h_mod_clk {
const char *name;
+ u32 mstop_data;
u16 parent;
bool critical;
bool no_pm;
@@ -123,9 +133,10 @@ struct rzv2h_mod_clk {
u8 mon_bit;
};
-#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
+#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
{ \
.name = (_name), \
+ .mstop_data = (_mstop), \
.parent = (_parent), \
.critical = (_critical), \
.no_pm = (_no_pm), \
@@ -135,14 +146,14 @@ struct rzv2h_mod_clk {
.mon_bit = (_monbit), \
}
-#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
- DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
+#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
+ DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
-#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
- DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
+#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
+ DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
-#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit) \
- DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
+#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
+ DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
/**
* struct rzv2h_reset - Reset definitions
@@ -184,6 +195,9 @@ struct rzv2h_reset {
*
* @resets: Array of Module Reset definitions
* @num_resets: Number of entries in resets[]
+ *
+ * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the
+ * number of CPG_BUS_m_MSTOP registers multiplied by 16.
*/
struct rzv2h_cpg_info {
/* Core Clocks */
@@ -200,6 +214,8 @@ struct rzv2h_cpg_info {
/* Resets */
const struct rzv2h_reset *resets;
unsigned int num_resets;
+
+ unsigned int num_mstop_bits;
};
extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 13/85] clk: renesas: rzv2h: Add MSTOP support
2025-03-12 11:21 ` [PATCH 6.1.y-cip 13/85] clk: renesas: rzv2h: Add MSTOP support Tommaso Merciai
@ 2025-03-20 9:02 ` Pavel Machek
0 siblings, 0 replies; 104+ messages in thread
From: Pavel Machek @ 2025-03-20 9:02 UTC (permalink / raw)
To: Tommaso Merciai
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 3883 bytes --]
Hi!
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> commit 9b6e63a777ea5fb85bf24f9cb5ba902eed4f1f2f upstream.
>
> Add MSTOP support to control buses for the individual units on RZ/V2H.
> Use per-bit (instead of group-based) configuration and atomic counters,
> to ensure precise control over individual MSTOP bits, and to prevent
> issues with shared dependencies between module clocks.
>
> Co-developed-by: Biju Das <biju.das.jz@bp.renesas.com>
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> +static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv,
> + u32 mstop_data)
> +{
> + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
> + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
> + unsigned int index = (mstop_index - 1) * 16;
> + atomic_t *mstop = &priv->mstop_count[index];
> + unsigned long flags;
> + unsigned int i;
> + u32 val = 0;
> +
> + spin_lock_irqsave(&priv->rmw_lock, flags);
> + for_each_set_bit(i, &mstop_mask, 16) {
> + if (!atomic_read(&mstop[i]))
> + val |= BIT(i) << 16;
> + atomic_inc(&mstop[i]);
> + }
> + if (val)
> + writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
> + spin_unlock_irqrestore(&priv->rmw_lock, flags);
> +}
> +
> +static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
> + u32 mstop_data)
> +{
> + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
> + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
> + unsigned int index = (mstop_index - 1) * 16;
> + atomic_t *mstop = &priv->mstop_count[index];
> + unsigned long flags;
> + unsigned int i;
> + u32 val = 0;
> +
> + spin_lock_irqsave(&priv->rmw_lock, flags);
> + for_each_set_bit(i, &mstop_mask, 16) {
> + if (!atomic_read(&mstop[i]) ||
> + atomic_dec_and_test(&mstop[i]))
> + val |= BIT(i) << 16 | BIT(i);
> + }
> + if (val)
> + writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
> + spin_unlock_irqrestore(&priv->rmw_lock, flags);
> +}
> @@ -555,6 +619,41 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
>
> priv->clks[id] = clock->hw.clk;
>
> + /*
> + * Ensure the module clocks and MSTOP bits are synchronized when they are
> + * turned ON by the bootloader. Enable MSTOP bits for module clocks that were
> + * turned ON in an earlier boot stage.
> + */
> + if (clock->mstop_data != BUS_MSTOP_NONE &&
> + !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) {
> + rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);
> + } else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {
> + unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);
> + u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);
> + unsigned int index = (mstop_index - 1) * 16;
> + atomic_t *mstop = &priv->mstop_count[index];
> + unsigned long flags;
> + unsigned int i;
> + u32 val = 0;
> +
> + /*
> + * Critical clocks are turned ON immediately upon registration, and the
> + * MSTOP counter is updated through the rzv2h_mod_clock_enable() path.
> + * However, if the critical clocks were already turned ON by the initial
> + * bootloader, synchronize the atomic counter here and clear the MSTOP bit.
> + */
> + spin_lock_irqsave(&priv->rmw_lock, flags);
> + for_each_set_bit(i, &mstop_mask, 16) {
> + if (atomic_read(&mstop[i]))
> + continue;
> + val |= BIT(i) << 16;
> + atomic_inc(&mstop[i]);
> + }
> + if (val)
> + writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
> + spin_unlock_irqrestore(&priv->rmw_lock, flags);
If these three could somehow be shared, it would be nice.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread
* [PATCH 6.1.y-cip 14/85] clk: renesas: rzv2h: Add support for RZ/G3E SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (12 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 13/85] clk: renesas: rzv2h: Add MSTOP support Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 15/85] clk: renesas: r9a09g047: Add CA55 core clocks Tommaso Merciai
` (71 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit bb6a9aaf670735d6583c76073ec41190f5404dc5 upstream.
The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with
more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1
are present only on the RZ/G3E SoC.
Add minimal clock and reset entries required to boot the Renesas RZ/G3E
SMARC EVK and binds it with the RZ/V2H CPG core driver.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a09g047-cpg.c | 102 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.c | 6 ++
drivers/clk/renesas/rzv2h-cpg.h | 1 +
5 files changed, 116 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 688c088a68d9..e1950ef22baa 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -39,6 +39,7 @@ config CLK_RENESAS
select CLK_R9A07G054 if ARCH_R9A07G054
select CLK_R9A08G045 if ARCH_R9A08G045
select CLK_R9A09G011 if ARCH_R9A09G011
+ select CLK_R9A09G047 if ARCH_R9A09G047
select CLK_R9A09G057 if ARCH_R9A09G057
select CLK_SH73A0 if ARCH_SH73A0
@@ -189,6 +190,10 @@ config CLK_R9A09G011
bool "RZ/V2M clock support" if COMPILE_TEST
select CLK_RZG2L
+config CLK_R9A09G047
+ bool "RZ/G3E clock support" if COMPILE_TEST
+ select CLK_RZV2H
+
config CLK_R9A09G057
bool "RZ/V2H(P) clock support" if COMPILE_TEST
select CLK_RZV2H
@@ -234,7 +239,7 @@ config CLK_RENESAS_VBATTB
select RESET_CONTROLLER
config CLK_RZV2H
- bool "RZ/V2H(P) family clock support" if COMPILE_TEST
+ bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST
select RESET_CONTROLLER
# Generic
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index e7ff58c0a480..a1fdc48c5c7d 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
+obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
new file mode 100644
index 000000000000..1178335dbed3
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G3E CPG driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+
+#include "rzv2h-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
+
+ /* External Input Clocks */
+ CLK_AUDIO_EXTAL,
+ CLK_RTXIN,
+ CLK_QEXTAL,
+
+ /* PLL Clocks */
+ CLK_PLLCM33,
+ CLK_PLLDTY,
+ CLK_PLLCA55,
+
+ /* Internal Core Clocks */
+ CLK_PLLCM33_DIV16,
+ CLK_PLLDTY_ACPU,
+ CLK_PLLDTY_ACPU_DIV4,
+
+ /* Module Clocks */
+ MOD_CLK_BASE,
+};
+
+static const struct clk_div_table dtable_2_64[] = {
+ {0, 2},
+ {1, 4},
+ {2, 8},
+ {3, 16},
+ {4, 64},
+ {0, 0},
+};
+
+static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
+ DEF_INPUT("rtxin", CLK_RTXIN),
+ DEF_INPUT("qextal", CLK_QEXTAL),
+
+ /* PLL Clocks */
+ DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+ DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
+ DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
+
+ /* Internal Core Clocks */
+ DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+
+ DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
+ DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+
+ /* Core Clocks */
+ DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
+ DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+};
+
+static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
+ DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
+ BUS_MSTOP(3, BIT(5))),
+ DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
+ BUS_MSTOP(3, BIT(14))),
+};
+
+static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
+ DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
+ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
+ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
+ DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
+};
+
+const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r9a09g047_core_clks,
+ .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r9a09g047_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks),
+ .num_hw_mod_clks = 28 * 16,
+
+ /* Resets */
+ .resets = r9a09g047_resets,
+ .num_resets = ARRAY_SIZE(r9a09g047_resets),
+
+ .num_mstop_bits = 208,
+};
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 6f096abda33c..1612864732e4 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -972,6 +972,12 @@ static const struct of_device_id rzv2h_cpg_match[] = {
.compatible = "renesas,r9a09g057-cpg",
.data = &r9a09g057_cpg_info,
},
+#endif
+#ifdef CONFIG_CLK_R9A09G047
+ {
+ .compatible = "renesas,r9a09g047-cpg",
+ .data = &r9a09g047_cpg_info,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index dcd65e9c09da..fd8eb985c75b 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -218,6 +218,7 @@ struct rzv2h_cpg_info {
unsigned int num_mstop_bits;
};
+extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
#endif /* __RENESAS_RZV2H_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 15/85] clk: renesas: r9a09g047: Add CA55 core clocks
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (13 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 14/85] clk: renesas: rzv2h: Add support for RZ/G3E SoC Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 16/85] clk: renesas: r9a09g047: Add I2C clocks/resets Tommaso Merciai
` (70 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 3baf0273c0627b7e6029304166df17e07c6796fb upstream.
Add CA55 core clocks which are derived from PLLCA55.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241213123550.289193-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r9a09g047-cpg.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 1178335dbed3..f5966c08de41 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -37,6 +37,14 @@ enum clk_ids {
MOD_CLK_BASE,
};
+static const struct clk_div_table dtable_1_8[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
static const struct clk_div_table dtable_2_64[] = {
{0, 2},
{1, 4},
@@ -65,6 +73,14 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
/* Core Clocks */
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
+ DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
+ CDDIV1_DIVCTL0, dtable_1_8),
+ DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55,
+ CDDIV1_DIVCTL1, dtable_1_8),
+ DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55,
+ CDDIV1_DIVCTL2, dtable_1_8),
+ DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
+ CDDIV1_DIVCTL3, dtable_1_8),
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 16/85] clk: renesas: r9a09g047: Add I2C clocks/resets
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (14 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 15/85] clk: renesas: r9a09g047: Add CA55 core clocks Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 17/85] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC Tommaso Merciai
` (69 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 29ebc6197403c643f389b59ba334e5bb53457103 upstream.
Add I2C{0..8} clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241216120029.143944-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r9a09g047-cpg.c | 32 +++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index f5966c08de41..536d922bed70 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -25,11 +25,13 @@ enum clk_ids {
/* PLL Clocks */
CLK_PLLCM33,
+ CLK_PLLCLN,
CLK_PLLDTY,
CLK_PLLCA55,
/* Internal Core Clocks */
CLK_PLLCM33_DIV16,
+ CLK_PLLCLN_DIV16,
CLK_PLLDTY_ACPU,
CLK_PLLDTY_ACPU_DIV4,
@@ -62,12 +64,15 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
/* PLL Clocks */
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+ DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
/* Internal Core Clocks */
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+ DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
+
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
@@ -89,6 +94,24 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(3, BIT(5))),
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
BUS_MSTOP(3, BIT(14))),
+ DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
+ BUS_MSTOP(3, BIT(13))),
+ DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
+ BUS_MSTOP(1, BIT(1))),
+ DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
+ BUS_MSTOP(1, BIT(2))),
+ DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
+ BUS_MSTOP(1, BIT(3))),
+ DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
+ BUS_MSTOP(1, BIT(4))),
+ DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
+ BUS_MSTOP(1, BIT(5))),
+ DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
+ BUS_MSTOP(1, BIT(6))),
+ DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
+ BUS_MSTOP(1, BIT(7))),
+ DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
+ BUS_MSTOP(1, BIT(8))),
};
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -96,6 +119,15 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
+ DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
+ DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
+ DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
+ DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
+ DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
+ DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
+ DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
+ DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
+ DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
};
const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 17/85] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (15 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 16/85] clk: renesas: r9a09g047: Add I2C clocks/resets Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 18/85] arm64: dts: renesas: r9a09g047: Add OPP table Tommaso Merciai
` (68 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 9977754eeebed749a071492d98e46700307c0bd1 upstream.
Add the initial DTSI for the RZ/G3E SoC.
The files in this commit have the following meaning:
- r9a09g047.dtsi: RZ/G3E family SoC common parts
- r9a09g047e57.dtsi: RZ/G3E R0A09G047E{4,5}{7,8} SoC specific parts
- r9a09g047e37.dtsi: RZ/G3E R0A09G047E{2,3}{7,8} SoC specific parts
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 144 ++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 +++
arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi | 13 ++
3 files changed, 175 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
new file mode 100644
index 000000000000..4176b9aa6892
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E SoC
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "renesas,r9a09g047";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ audio_extal_clk: audio-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x100000>;
+ cache-level = <3>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ qextal_clk: qextal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ rtxin_clk: rtxin-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpg: clock-controller@10420000 {
+ compatible = "renesas,r9a09g047-cpg";
+ reg = <0 0x10420000 0 0x10000>;
+ clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+ clock-names = "audio_extal", "rtxin", "qextal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ scif0: serial@11c01400 {
+ compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
+ reg = <0 0x11c01400 0 0x400>;
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eri", "rxi", "txi", "bri", "dri",
+ "tei", "tei-dri", "rxi-edge", "txi-edge";
+ clocks = <&cpg CPG_MOD 0x8f>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x95>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@14900000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x14900000 0 0x20000>,
+ <0x0 0x14940000 0 0x80000>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi
new file mode 100644
index 000000000000..e50d9159e832
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g047.dtsi"
+
+/ {
+ compatible = "renesas,r9a09g047e37", "renesas,r9a09g047";
+
+ cpus {
+ /delete-node/ cpu@200;
+ /delete-node/ cpu@300;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi
new file mode 100644
index 000000000000..98a5faebd47a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A09G047E57 SoC specific parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g047.dtsi"
+
+/ {
+ compatible = "renesas,r9a09g047e57", "renesas,r9a09g047";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 18/85] arm64: dts: renesas: r9a09g047: Add OPP table
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (16 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 17/85] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 19/85] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM Tommaso Merciai
` (67 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 8e96597f3c25007d292eabba9cfc9612e7d90f0f upstream.
Add OPP table for RZ/G3E SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-11-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 4176b9aa6892..39a7cfb3095b 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
clock-frequency = <0>;
};
+ /*
+ * The default cluster table is based on the assumption that the PLLCA55 clock
+ * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
+ * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
+ * clocked to 1.8GHz as well). The table below should be overridden in the board
+ * DTS based on the PLLCA55 clock frequency.
+ */
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-425000000 {
+ opp-hz = /bits/ 64 <425000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-212500000 {
+ opp-hz = /bits/ 64 <212500000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -30,6 +63,8 @@ cpu0: cpu@0 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
@@ -38,6 +73,8 @@ cpu1: cpu@100 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@200 {
@@ -46,6 +83,8 @@ cpu2: cpu@200 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@300 {
@@ -54,6 +93,8 @@ cpu3: cpu@300 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
+ operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 19/85] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (17 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 18/85] arm64: dts: renesas: r9a09g047: Add OPP table Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 20/85] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board Tommaso Merciai
` (66 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit e0379695728b0d79c20bc1a904bb4168d4f117c0 upstream.
Add initial support for the RZ/G3E SMARC SoM with 4GB memory,
audio_extal, qextal and rtxin clks.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-12-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../boot/dts/renesas/rzg3e-smarc-som.dtsi | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
new file mode 100644
index 000000000000..6b583ae2ac52
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R9A09G047E57 SMARC SoM board.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/ {
+ compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* First 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0xf8000000>;
+ };
+};
+
+&audio_extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&qextal_clk {
+ clock-frequency = <24000000>;
+};
+
+&rtxin_clk {
+ clock-frequency = <32768>;
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 20/85] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (18 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 19/85] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:21 ` [PATCH 6.1.y-cip 21/85] soc: renesas: Add RZ/G3E (R9A09G047) config option Tommaso Merciai
` (65 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit c4d87fe3cd4eab905f235ecfdd09313be9bc0e99 upstream.
Add the initial device tree for the Renesas RZ/G3E SMARC EVK board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-13-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/Makefile | 2 ++
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 18 ++++++++++++++
.../boot/dts/renesas/renesas-smarc2.dtsi | 24 +++++++++++++++++++
3 files changed, 44 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 7b0f06600f20..48f1924ed388 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -89,5 +89,7 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
+dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
+
dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
new file mode 100644
index 000000000000..d4d61bd03969
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E SMARC EVK board
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include "r9a09g047e57.dtsi"
+#include "rzg3e-smarc-som.dtsi"
+#include "renesas-smarc2.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK version 2 based on r9a09g047e57";
+ compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
+ "renesas,r9a09g047e57", "renesas,r9a09g047";
+};
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
new file mode 100644
index 000000000000..e378d55e6e9b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ SMARC Carrier-II Board.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/ {
+ model = "Renesas RZ SMARC Carrier-II Board";
+ compatible = "renesas,smarc2-evk";
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial3:115200n8";
+ };
+
+ aliases {
+ serial3 = &scif0;
+ };
+};
+
+&scif0 {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 21/85] soc: renesas: Add RZ/G3E (R9A09G047) config option
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (19 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 20/85] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-14 10:25 ` Pavel Machek
2025-03-12 11:21 ` [PATCH 6.1.y-cip 22/85] arm64: defconfig: Enable R9A09G047 SoC Tommaso Merciai
` (64 subsequent siblings)
85 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 12e0bd600e3c2f33f9db0e3b91f6b8d8d95b7dbe upstream.
Add a configuration option for the RZ/G3E SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/soc/renesas/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 171be915cdac..e0eb3fbc3ca6 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -338,6 +338,11 @@ config ARCH_R9A09G011
help
This enables support for the Renesas RZ/V2M SoC.
+config ARCH_R9A09G047
+ bool "ARM64 Platform support for RZ/G3E"
+ help
+ This enables support for the Renesas RZ/G3E SoC variants.
+
endif # ARM64
if RISCV
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 21/85] soc: renesas: Add RZ/G3E (R9A09G047) config option
2025-03-12 11:21 ` [PATCH 6.1.y-cip 21/85] soc: renesas: Add RZ/G3E (R9A09G047) config option Tommaso Merciai
@ 2025-03-14 10:25 ` Pavel Machek
2025-03-14 10:58 ` Tommaso Merciai
0 siblings, 1 reply; 104+ messages in thread
From: Pavel Machek @ 2025-03-14 10:25 UTC (permalink / raw)
To: Tommaso Merciai
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 554 bytes --]
Hi!
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> commit 12e0bd600e3c2f33f9db0e3b91f6b8d8d95b7dbe upstream.
There's strange whitespace between "commit" and hash.
> Add a configuration option for the RZ/G3E SoC.
But what I wanted to say is that this seems like good place where to
split the series. If you are enabling it, it should already be
booting.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread
* Re: [PATCH 6.1.y-cip 21/85] soc: renesas: Add RZ/G3E (R9A09G047) config option
2025-03-14 10:25 ` Pavel Machek
@ 2025-03-14 10:58 ` Tommaso Merciai
0 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-14 10:58 UTC (permalink / raw)
To: Pavel Machek
Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar, tomm.merciai
Hi Pavel,
Thanks for your review.
On Fri, Mar 14, 2025 at 11:25:48AM +0100, Pavel Machek wrote:
> Hi!
>
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > commit 12e0bd600e3c2f33f9db0e3b91f6b8d8d95b7dbe upstream.
>
> There's strange whitespace between "commit" and hash.
Ouch.
Will fix that, thanks.
>
> > Add a configuration option for the RZ/G3E SoC.
>
> But what I wanted to say is that this seems like good place where to
> split the series. If you are enabling it, it should already be
> booting.
Fully agree, thanks.
At this point we can boot using initramfs.
>
> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Regards,
Tommaso.
^ permalink raw reply [flat|nested] 104+ messages in thread
* [PATCH 6.1.y-cip 22/85] arm64: defconfig: Enable R9A09G047 SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (20 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 21/85] soc: renesas: Add RZ/G3E (R9A09G047) config option Tommaso Merciai
@ 2025-03-12 11:21 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 23/85] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H Tommaso Merciai
` (63 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:21 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit a40f02b2923b6d58e76cfef760b8ed61a00f1d53 upstream.
Enable support for the Renesas RZ/G3E (R9A09G047) SoC in the ARM64
defconfig.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-14-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index a15bfa82fe59..459c1fac90ff 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1182,6 +1182,7 @@ CONFIG_ARCH_R9A07G044=y
CONFIG_ARCH_R9A07G054=y
CONFIG_ARCH_R9A08G045=y
CONFIG_ARCH_R9A09G011=y
+CONFIG_ARCH_R9A09G047=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ARCH_TEGRA_132_SOC=y
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 23/85] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (21 preceding siblings ...)
2025-03-12 11:21 ` [PATCH 6.1.y-cip 22/85] arm64: defconfig: Enable R9A09G047 SoC Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 24/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties Tommaso Merciai
` (62 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 3e4863d24818a41db42b4f2680715f204657839e upstream.
RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical
ports in DT using RZV2H_* macros.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241216195325.164212-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../pinctrl/renesas,r9a09g057-pinctrl.h | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
new file mode 100644
index 000000000000..2e83bf43160b
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZV2H_Px = Offset address of PFC_P_mn - 0x20 */
+#define RZV2H_P0 0
+#define RZV2H_P1 1
+#define RZV2H_P2 2
+#define RZV2H_P3 3
+#define RZV2H_P4 4
+#define RZV2H_P5 5
+#define RZV2H_P6 6
+#define RZV2H_P7 7
+#define RZV2H_P8 8
+#define RZV2H_P9 9
+#define RZV2H_PA 10
+#define RZV2H_PB 11
+
+#define RZV2H_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
+#define RZV2H_GPIO(port, pin) RZG2L_GPIO(RZV2H_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 24/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (22 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 23/85] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 25/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the object Tommaso Merciai
` (61 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit a76932e45e9b56ac24ee947294fbb52c3713f839 upstream.
On the RZ/G3S SMARC platform, the 'input' property is utilized in
gpio-hog nodes, and the 'output-enable' property is used for ETH0/1 TXC
pins. Update the binding documentation to include these properties,
addressing the following dtbs_check warnings:
arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: pinctrl@11030000: key-1-gpio-hog: 'anyOf' conditional failed, one must be fixed:
'input' does not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: pinctrl@11030000: eth0: 'anyOf' conditional failed, one must be fixed:
'output-enable' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240313083828.5048-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index b8937e01be92..845225d58cd0 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -120,7 +120,9 @@ additionalProperties:
slew-rate: true
gpio-hog: true
gpios: true
+ input: true
input-enable: true
+ output-enable: true
output-high: true
output-low: true
line-name: true
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 25/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the object
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (23 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 24/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 26/85] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC Tommaso Merciai
` (60 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 26771100519af263e3b04b635bc917f8dfbdb77c upstream.
Drop the bogus check from object as this didn't really add restriction
check.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240423175900.702640-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 ---------------
1 file changed, 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 845225d58cd0..235cefe60f5d 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -78,21 +78,6 @@ additionalProperties:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
- - if:
- properties:
- compatible:
- contains:
- enum:
- - renesas,r9a08g045-pinctrl
- then:
- properties:
- drive-strength: false
- output-impedance-ohms: false
- slew-rate: false
- else:
- properties:
- drive-strength-microamp: false
-
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 26/85] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (24 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 25/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the object Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 27/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties Tommaso Merciai
` (59 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit fb73d663b31398aea8528fb231e660c4958b29ff upstream.
Add documentation for the pin controller found on the Renesas RZ/V2H(P)
(R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L
family:
- Additional bits need to be set during pinmuxing,
- The GPIO pin count is different.
Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is
added for the RZ/V2H(P) SoC.
Also, add the 'renesas,output-impedance' property. The drive strength
settings on RZ/V2H(P) depend on the different power rails coming out from
the PMIC (connected via I2C). These power rails (required for drive
strength) can be 1.2V, 1.8V, or 3.3V.
Pins are grouped into 4 groups:
Group 1: Impedance
- 150/75/38/25 ohms (at 3.3V)
- 130/65/33/22 ohms (at 1.8V)
Group 2: Impedance
- 50/40/33/25 ohms (at 1.8V)
Group 3: Impedance
- 150/75/37.5/25 ohms (at 3.3V)
- 130/65/33/22 ohms (at 1.8V)
Group 4: Impedance
- 110/55/30/20 ohms (at 1.8V)
- 150/75/38/25 ohms (at 1.2V)
The 'renesas,output-impedance' property, as documented, can be
[0, 1, 2, 3], these correspond to register bit values that can
be set in the PFC_IOLH_mn register, which adjusts the drive
strength value and is pin-dependent.
As power rail information may not be available very early in the boot
process, the 'renesas,output-impedance' property is added instead of
reusing the 'output-impedance-ohms' property.
Also, allow bias-disable, bias-pull-down and bias-pull-up properties
as these can be used to configure the pins.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240606085133.632307-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 37 +++++++++++++++++--
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 235cefe60f5d..7d7e66eaabf1 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
+ - renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
- enum:
@@ -66,10 +67,14 @@ properties:
maxItems: 1
resets:
- items:
- - description: GPIO_RSTN signal
- - description: GPIO_PORT_RESETN signal
- - description: GPIO_SPARE_RESETN signal
+ oneOf:
+ - items:
+ - description: GPIO_RSTN signal
+ - description: GPIO_PORT_RESETN signal
+ - description: GPIO_SPARE_RESETN signal
+ - items:
+ - description: PFC main reset
+ - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
additionalProperties:
anyOf:
@@ -111,6 +116,16 @@ additionalProperties:
output-high: true
output-low: true
line-name: true
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ renesas,output-impedance:
+ description:
+ Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
+ property corresponds to register bit values that can be set in the PFC_IOLH_mn
+ register, which adjusts the drive strength value and is pin-dependent.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
- type: object
properties:
@@ -122,6 +137,20 @@ additionalProperties:
allOf:
- $ref: "pinctrl.yaml#"
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g057-pinctrl
+ then:
+ properties:
+ resets:
+ maxItems: 2
+ else:
+ properties:
+ resets:
+ minItems: 3
+
required:
- compatible
- reg
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 27/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (25 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 26/85] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 28/85] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC Tommaso Merciai
` (58 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit f07e2b681edd8d8ed25048b958fdcfb55abaf487 upstream.
On the RZ/V2H(P) SoC one can configure the 'input-schmitt-{enable,disable}',
'drive-open-drain' and 'drive-push-pull' of multiplexed pins. Update the
binding documentation to include these properties.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/20241004123658.764557-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 7d7e66eaabf1..1a16fc06c96a 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -119,6 +119,10 @@ additionalProperties:
bias-disable: true
bias-pull-down: true
bias-pull-up: true
+ input-schmitt-enable: true
+ input-schmitt-disable: true
+ drive-open-drain: true
+ drive-push-pull: true
renesas,output-impedance:
description:
Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 28/85] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (26 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 27/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 29/85] pinctrl: renesas: rzg2l: Allow more bits for pin configuration Tommaso Merciai
` (57 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 5c7fb203d0dbfbfeed51991a4f98499b245634a7 upstream.
Add documentation for the pin controller found on the Renesas RZ/G3E
(R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has more
pins(P00-PS3).
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241216195325.164212-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 7 +++-
.../pinctrl/renesas,r9a09g047-pinctrl.h | 41 +++++++++++++++++++
2 files changed, 46 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 1a16fc06c96a..716df90d5c09 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
+ - renesas,r9a09g047-pinctrl # RZ/G3E
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
@@ -125,7 +126,7 @@ additionalProperties:
drive-push-pull: true
renesas,output-impedance:
description:
- Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
+ Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
property corresponds to register bit values that can be set in the PFC_IOLH_mn
register, which adjusts the drive strength value and is pin-dependent.
$ref: /schemas/types.yaml#/definitions/uint32
@@ -145,7 +146,9 @@ allOf:
properties:
compatible:
contains:
- const: renesas,r9a09g057-pinctrl
+ enum:
+ - renesas,r9a09g047-pinctrl
+ - renesas,r9a09g057-pinctrl
then:
properties:
resets:
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
new file mode 100644
index 000000000000..5917096720bd
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G3E family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */
+#define RZG3E_P0 0
+#define RZG3E_P1 1
+#define RZG3E_P2 2
+#define RZG3E_P3 3
+#define RZG3E_P4 4
+#define RZG3E_P5 5
+#define RZG3E_P6 6
+#define RZG3E_P7 7
+#define RZG3E_P8 8
+#define RZG3E_PA 10
+#define RZG3E_PB 11
+#define RZG3E_PC 12
+#define RZG3E_PD 13
+#define RZG3E_PE 14
+#define RZG3E_PF 15
+#define RZG3E_PG 16
+#define RZG3E_PH 17
+#define RZG3E_PJ 19
+#define RZG3E_PK 20
+#define RZG3E_PL 21
+#define RZG3E_PM 22
+#define RZG3E_PS 28
+
+#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
+#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 29/85] pinctrl: renesas: rzg2l: Allow more bits for pin configuration
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (27 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 28/85] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 30/85] pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg Tommaso Merciai
` (56 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 8081a03793d3276c50d55a6f561872168eccf944 upstream.
The pin configuration bits have been growing for every new SoCs being
added for the pinctrl-rzg2l driver which would mean updating the macros
every time for each new configuration. To avoid this allocate additional
bits for pin configuration by relocating the known fixed bits to the very
end of the configuration.
Also update the size of 'cfg' to 'u64' to allow more configuration bits
in the 'struct rzg2l_variable_pin_cfg'.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 30 ++++++++++++++-----------
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index cbb4780fb2d0..33eff02c6206 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -77,9 +77,9 @@
PIN_CFG_FILNUM | \
PIN_CFG_FILCLKSEL)
-#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28)
-#define PIN_CFG_PIN_REG_MASK GENMASK(27, 20)
-#define PIN_CFG_MASK GENMASK(19, 0)
+#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55)
+#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47)
+#define PIN_CFG_MASK GENMASK_ULL(46, 0)
/*
* m indicates the bitmap of supported pins, a is the register index
@@ -101,8 +101,8 @@
* (b * 8) and f is the pin configuration capabilities supported.
*/
#define RZG2L_SINGLE_PIN BIT_ULL(63)
-#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24)
-#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20)
+#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)
+#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)
#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
@@ -240,9 +240,9 @@ struct rzg2l_dedicated_configs {
* @pin: port pin
*/
struct rzg2l_variable_pin_cfg {
- u32 cfg:20;
- u32 port:5;
- u32 pin:3;
+ u64 cfg:47;
+ u64 port:5;
+ u64 pin:3;
};
struct rzg2l_pinctrl_data {
@@ -1081,7 +1081,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
u64 *pin_data = pin->drv_data;
unsigned int arg = 0;
- u32 off, cfg;
+ u32 off;
+ u64 cfg;
int ret;
u8 bit;
@@ -1185,7 +1186,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
u64 *pin_data = pin->drv_data;
enum pin_config_param param;
unsigned int i, arg, index;
- u32 cfg, off;
+ u32 off;
+ u64 cfg;
int ret;
u8 bit;
@@ -2413,9 +2415,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
for (u32 port = 0; port < nports; port++) {
bool has_iolh, has_ien;
- u32 off, caps;
+ u64 cfg, caps;
u8 pincnt;
- u64 cfg;
+ u32 off;
cfg = pctrl->data->port_pin_configs[port];
off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
@@ -2459,12 +2461,14 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
{
struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;
+ u64 caps;
+ u32 i;
/*
* Make sure entries in pctrl->data->n_dedicated_pins[] having the same
* port offset are close together.
*/
- for (u32 i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
+ for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
bool has_iolh, has_ien;
u32 off, next_off = 0;
u64 cfg, next_cfg;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 30/85] pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (28 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 29/85] pinctrl: renesas: rzg2l: Allow more bits for pin configuration Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 31/85] pinctrl: renesas: rzg2l: Enable variable configuration for all Tommaso Merciai
` (55 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 13a8cae6e561d607474f905028781a5aee7205cb upstream.
Drop the rzg2l_variable_pin_cfg struct and instead use the
RZG2L_VARIABLE_PIN_CFG_PACK() macro for the variable pin configuration.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 187 +++++++-----------------
1 file changed, 54 insertions(+), 133 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 33eff02c6206..24eb4a375ce5 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -113,6 +113,13 @@
FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \
FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))
+#define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52)
+#define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47)
+#define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \
+ (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \
+ FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
+ FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
+
#define P(off) (0x0000 + (off))
#define PM(off) (0x0100 + (off) * 2)
#define PMC(off) (0x0200 + (off))
@@ -233,18 +240,6 @@ struct rzg2l_dedicated_configs {
u64 config;
};
-/**
- * struct rzg2l_variable_pin_cfg - pin data cfg
- * @cfg: port pin configuration
- * @port: port number
- * @pin: port pin
- */
-struct rzg2l_variable_pin_cfg {
- u64 cfg:47;
- u64 port:5;
- u64 pin:3;
-};
-
struct rzg2l_pinctrl_data {
const char * const *port_pins;
const u64 *port_pin_configs;
@@ -253,7 +248,7 @@ struct rzg2l_pinctrl_data {
unsigned int n_port_pins;
unsigned int n_dedicated_pins;
const struct rzg2l_hwcfg *hwcfg;
- const struct rzg2l_variable_pin_cfg *variable_pin_cfg;
+ const u64 *variable_pin_cfg;
unsigned int n_variable_pin_cfg;
};
@@ -330,131 +325,57 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
unsigned int i;
for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {
- if (pctrl->data->variable_pin_cfg[i].port == port &&
- pctrl->data->variable_pin_cfg[i].pin == pin)
- return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg;
+ u64 cfg = pctrl->data->variable_pin_cfg[i];
+
+ if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&
+ FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)
+ return (pincfg & ~PIN_CFG_VARIABLE) | FIELD_GET(PIN_CFG_MASK, cfg);
}
return 0;
}
-static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = {
- {
- .port = 20,
- .pin = 0,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 20,
- .pin = 1,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 20,
- .pin = 2,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 20,
- .pin = 3,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 20,
- .pin = 4,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 20,
- .pin = 5,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 20,
- .pin = 6,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 20,
- .pin = 7,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 23,
- .pin = 1,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_NOGPIO_INT
- },
- {
- .port = 23,
- .pin = 2,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 23,
- .pin = 3,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 23,
- .pin = 4,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 23,
- .pin = 5,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 24,
- .pin = 0,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 24,
- .pin = 1,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 24,
- .pin = 2,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 24,
- .pin = 3,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 24,
- .pin = 4,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_NOGPIO_INT,
- },
- {
- .port = 24,
- .pin = 5,
- .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
- PIN_CFG_NOGPIO_INT,
- },
+static const u64 r9a07g043f_variable_pin_cfg[] = {
+ RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_NOGPIO_INT),
+ RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
+ PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ PIN_CFG_NOGPIO_INT),
};
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 31/85] pinctrl: renesas: rzg2l: Enable variable configuration for all
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (29 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 30/85] pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 32/85] pinctrl: renesas: rzg2l: Validate power registers for SD and ETH Tommaso Merciai
` (54 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 08b68ae5a0276f293c8da602f963f6de68b3599b upstream.
Enable parsing of variable configuration for all architectures. This
prepares for adding support for the RZ/V2H SoC, which utilizes the ARM64
architecture and features port pins with variable configuration.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 24eb4a375ce5..0d3ffd761762 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -316,7 +316,6 @@ struct rzg2l_pinctrl {
static const u16 available_ps[] = { 1800, 2500, 3300 };
-#ifdef CONFIG_RISCV
static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
u64 pincfg,
unsigned int port,
@@ -335,6 +334,7 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
return 0;
}
+#ifdef CONFIG_RISCV
static const u64 r9a07g043f_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
@@ -2219,13 +2219,11 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
if (i && !(i % RZG2L_PINS_PER_PORT))
j++;
pin_data[i] = pctrl->data->port_pin_configs[j];
-#ifdef CONFIG_RISCV
if (pin_data[i] & PIN_CFG_VARIABLE)
pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
pin_data[i],
j,
i % RZG2L_PINS_PER_PORT);
-#endif
pins[i].drv_data = &pin_data[i];
}
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 32/85] pinctrl: renesas: rzg2l: Validate power registers for SD and ETH
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (30 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 31/85] pinctrl: renesas: rzg2l: Enable variable configuration for all Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 33/85] pinctrl: renesas: rzg2l: Add function pointer for PFC register locking Tommaso Merciai
` (53 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit a3a632ed87f0913779092c30bd0ea7dfd81601f3 upstream.
On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
resulting in invalid register offsets. Ensure that the register offsets
are valid before any read/write operations are performed. If the power
registers are not available, both SD and ETH will be set to '0'.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 0d3ffd761762..b6b53757d803 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2503,8 +2503,10 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true);
for (u8 i = 0; i < 2; i++) {
- cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));
- cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
+ if (regs->sd_ch)
+ cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));
+ if (regs->eth_poc)
+ cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
}
cache->qspi = readb(pctrl->base + QSPI);
@@ -2535,8 +2537,10 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
writeb(cache->qspi, pctrl->base + QSPI);
writeb(cache->eth_mode, pctrl->base + ETH_MODE);
for (u8 i = 0; i < 2; i++) {
- writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
- writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i));
+ if (regs->sd_ch)
+ writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
+ if (regs->eth_poc)
+ writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i));
}
rzg2l_pinctrl_pm_setup_pfc(pctrl);
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 33/85] pinctrl: renesas: rzg2l: Add function pointer for PFC register locking
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (31 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 32/85] pinctrl: renesas: rzg2l: Validate power registers for SD and ETH Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 34/85] pinctrl: renesas: rzg2l: Add function pointer for PMC register write Tommaso Merciai
` (52 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 14c32dc1f63d0de865e67c04c919ae036de20f87 upstream.
On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers.
However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls
writing to both PFC and PMC registers. Additionally, BIT(7) B0WI is
undocumented for the PWPR register on RZ/V2H(P) SoC. To accommodate these
differences across SoC variants, introduce the pwpr_pfc_lock_unlock()
function pointer.
Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_lock_unlock(.., false)
is now called before PMC read/write and pwpr_pfc_lock_unlock(.., true) is
now called after PMC read/write this is to keep changes minimal for
RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 44 +++++++++++++++----------
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index b6b53757d803..95b51f31c387 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -240,6 +240,8 @@ struct rzg2l_dedicated_configs {
u64 config;
};
+struct rzg2l_pinctrl;
+
struct rzg2l_pinctrl_data {
const char * const *port_pins;
const u64 *port_pin_configs;
@@ -250,6 +252,7 @@ struct rzg2l_pinctrl_data {
const struct rzg2l_hwcfg *hwcfg;
const u64 *variable_pin_cfg;
unsigned int n_variable_pin_cfg;
+ void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
};
/**
@@ -382,7 +385,6 @@ static const u64 r9a07g043f_variable_pin_cfg[] = {
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 pin, u8 off, u8 func)
{
- const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
unsigned long flags;
u32 reg;
@@ -393,27 +395,23 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
reg &= ~(PM_MASK << (pin * 2));
writew(reg, pctrl->base + PM(off));
+ pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
+
/* Temporarily switch to GPIO mode with PMC register */
reg = readb(pctrl->base + PMC(off));
writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
- /* Set the PWPR register to allow PFC register to write */
- writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
- writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
-
/* Select Pin function mode with PFC register */
reg = readl(pctrl->base + PFC(off));
reg &= ~(PFC_MASK << (pin * 4));
writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
- /* Set the PWPR register to be write-protected */
- writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
- writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
-
/* Switch to Peripheral pin function with PMC register */
reg = readb(pctrl->base + PMC(off));
writeb(reg | BIT(pin), pctrl->base + PMC(off));
+ pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
+
spin_unlock_irqrestore(&pctrl->lock, flags);
};
@@ -2439,12 +2437,8 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
{
u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
- const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
- const struct rzg2l_register_offsets *regs = &hwcfg->regs;
- /* Set the PWPR register to allow PFC register to write. */
- writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
- writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
+ pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
/* Restore port registers. */
for (u32 port = 0; port < nports; port++) {
@@ -2487,9 +2481,7 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
}
}
- /* Set the PWPR register to be write-protected. */
- writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
- writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
+ pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
}
static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
@@ -2551,6 +2543,21 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
return 0;
}
+static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
+{
+ const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
+
+ if (lock) {
+ /* Set the PWPR register to be write-protected */
+ writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
+ writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
+ } else {
+ /* Set the PWPR register to allow PFC register to write */
+ writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
+ writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
+ }
+}
+
static const struct rzg2l_hwcfg rzg2l_hwcfg = {
.regs = {
.pwpr = 0x3014,
@@ -2608,6 +2615,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.variable_pin_cfg = r9a07g043f_variable_pin_cfg,
.n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
#endif
+ .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
};
static struct rzg2l_pinctrl_data r9a07g044_data = {
@@ -2619,6 +2627,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
.hwcfg = &rzg2l_hwcfg,
+ .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
};
static struct rzg2l_pinctrl_data r9a08g045_data = {
@@ -2629,6 +2638,7 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
.hwcfg = &rzg3s_hwcfg,
+ .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
};
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 34/85] pinctrl: renesas: rzg2l: Add function pointer for PMC register write
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (32 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 33/85] pinctrl: renesas: rzg2l: Add function pointer for PFC register locking Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 35/85] pinctrl: renesas: rzg2l: Add function pointers for OEN register access Tommaso Merciai
` (51 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit ede014cd1ea6422d7436bd0a1771fe0d7b0fe12a upstream.
Introduces pmc_writeb() function pointer, in the struct
rzg2l_pinctrl_data to facilitate writing to the PMC register. On the
RZ/V2H(P) SoC, unlocking the PWPR.REGWE_A bit before writing to PMC
registers is required, whereas this is not the case for the existing
RZ/G2L family. This addition enables the reuse of existing code for
RZ/V2H(P). Additionally, populate this function pointer with
appropriate data for existing SoCs.
Note that this functionality is only handled in rzg2l_gpio_request(), as
PMC unlock/lock during PFC setup will be taken care of in the
pwpr_pfc_lock_unlock() function pointer.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 95b51f31c387..947fcd39b168 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -253,6 +253,7 @@ struct rzg2l_pinctrl_data {
const u64 *variable_pin_cfg;
unsigned int n_variable_pin_cfg;
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
+ void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
};
/**
@@ -382,6 +383,11 @@ static const u64 r9a07g043f_variable_pin_cfg[] = {
};
#endif
+static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
+{
+ writeb(val, pctrl->base + offset);
+}
+
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 pin, u8 off, u8 func)
{
@@ -1329,7 +1335,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
/* Select GPIO mode in PMC Register */
reg8 = readb(pctrl->base + PMC(off));
reg8 &= ~BIT(bit);
- writeb(reg8, pctrl->base + PMC(off));
+ pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));
spin_unlock_irqrestore(&pctrl->lock, flags);
@@ -2616,6 +2622,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
#endif
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
+ .pmc_writeb = &rzg2l_pmc_writeb,
};
static struct rzg2l_pinctrl_data r9a07g044_data = {
@@ -2628,6 +2635,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
.hwcfg = &rzg2l_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
+ .pmc_writeb = &rzg2l_pmc_writeb,
};
static struct rzg2l_pinctrl_data r9a08g045_data = {
@@ -2639,6 +2647,7 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
.hwcfg = &rzg3s_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
+ .pmc_writeb = &rzg2l_pmc_writeb,
};
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 35/85] pinctrl: renesas: rzg2l: Add function pointers for OEN register access
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (33 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 34/85] pinctrl: renesas: rzg2l: Add function pointer for PMC register write Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 36/85] pinctrl: renesas: rzg2l: Add support to configure slew-rate Tommaso Merciai
` (50 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 7d566a4d270c52ffffd04b78b753bb3ce8cbb867 upstream.
Introduce function pointers oen_read() and oen_write(), in the struct
rzg2l_pinctrl_data to facilitate reading and writing to the PFC_OEN
register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_B bit before
writing to the PFC_OEN register is necessary, and the PFC_OEN register
has more bits compared to the RZ/G2L family. To handle these
differences between RZ/G2L and RZ/V2H(P) and to reuse the existing code
for RZ/V2H(P), these function pointers are introduced.
Additionally, populate these function pointers with appropriate data for
existing SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 947fcd39b168..430a7638a9d3 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -254,6 +254,8 @@ struct rzg2l_pinctrl_data {
unsigned int n_variable_pin_cfg;
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
+ u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
+ int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);
};
/**
@@ -1035,7 +1037,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
- arg = rzg2l_read_oen(pctrl, cfg, _pin, bit);
+ arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit);
if (!arg)
return -EINVAL;
break;
@@ -1144,7 +1146,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_OUTPUT_ENABLE:
arg = pinconf_to_config_argument(_configs[i]);
- ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg);
+ ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg);
if (ret)
return ret;
break;
@@ -2623,6 +2625,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
#endif
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
};
static struct rzg2l_pinctrl_data r9a07g044_data = {
@@ -2636,6 +2640,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.hwcfg = &rzg2l_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
};
static struct rzg2l_pinctrl_data r9a08g045_data = {
@@ -2648,6 +2654,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.hwcfg = &rzg3s_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
};
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 36/85] pinctrl: renesas: rzg2l: Add support to configure slew-rate
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (34 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 35/85] pinctrl: renesas: rzg2l: Add function pointers for OEN register access Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 37/85] pinctrl: renesas: rzg2l: Add support for pull-up/down Tommaso Merciai
` (49 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit b588b53b2c474bdebbac0a663e0a6a0390db2fdf upstream.
Add support to configure slew-rate property of the pin.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 430a7638a9d3..596e101f5b2d 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -126,6 +126,7 @@
#define PFC(off) (0x0400 + (off) * 4)
#define PIN(off) (0x0800 + (off))
#define IOLH(off) (0x1000 + (off) * 8)
+#define SR(off) (0x1400 + (off) * 8)
#define IEN(off) (0x1800 + (off) * 8)
#define ISEL(off) (0x2C00 + (off) * 8)
#define SD_CH(off, ch) ((off) + (ch) * 4)
@@ -144,6 +145,7 @@
#define PFC_MASK 0x07
#define IEN_MASK 0x01
#define IOLH_MASK 0x03
+#define SR_MASK 0x01
#define PM_INPUT 0x1
#define PM_OUTPUT 0x2
@@ -1049,6 +1051,13 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
arg = ret;
break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (!(cfg & PIN_CFG_SR))
+ return -EINVAL;
+
+ arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);
+ break;
+
case PIN_CONFIG_DRIVE_STRENGTH: {
unsigned int index;
@@ -1155,6 +1164,15 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
settings.power_source = pinconf_to_config_argument(_configs[i]);
break;
+ case PIN_CONFIG_SLEW_RATE:
+ arg = pinconf_to_config_argument(_configs[i]);
+
+ if (!(cfg & PIN_CFG_SR) || arg > 1)
+ return -EINVAL;
+
+ rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg);
+ break;
+
case PIN_CONFIG_DRIVE_STRENGTH:
arg = pinconf_to_config_argument(_configs[i]);
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 37/85] pinctrl: renesas: rzg2l: Add support for pull-up/down
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (35 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 36/85] pinctrl: renesas: rzg2l: Add support to configure slew-rate Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 38/85] pinctrl: renesas: rzg2l: Pass pincontrol device to pinconf_generic_parse_dt_config() Tommaso Merciai
` (48 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 19d4bce9ce876ad0ee4240ebd849b730b3dc3763 upstream.
Add support to configure bias-disable, bias-pull-up, and bias-pull-down
properties of the pin.
Two new function pointers, hw_to_bias_param() and bias_param_to_hw(),
are introduced in the struct rzg2l_pinctrl_data to configure bias
settings, as the values in the PUPD register differ when compared to the
RZ/G2L family and the RZ/V2H(P) SoC.
Value | RZ/G2L | RZ/V2H
---------------------------------
00b: | Bias Disabled | Pull up/down disabled
01b: | Pull-up | Pull up/down disabled
10b: | Pull-down | Pull-down
11b: | Prohibited | Pull-up
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-12-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 72 +++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 596e101f5b2d..33c96661092b 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -128,6 +128,7 @@
#define IOLH(off) (0x1000 + (off) * 8)
#define SR(off) (0x1400 + (off) * 8)
#define IEN(off) (0x1800 + (off) * 8)
+#define PUPD(off) (0x1C00 + (off) * 8)
#define ISEL(off) (0x2C00 + (off) * 8)
#define SD_CH(off, ch) ((off) + (ch) * 4)
#define ETH_POC(off, ch) ((off) + (ch) * 4)
@@ -146,6 +147,7 @@
#define IEN_MASK 0x01
#define IOLH_MASK 0x03
#define SR_MASK 0x01
+#define PUPD_MASK 0x03
#define PM_INPUT 0x1
#define PM_OUTPUT 0x2
@@ -258,6 +260,8 @@ struct rzg2l_pinctrl_data {
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);
+ int (*hw_to_bias_param)(unsigned int val);
+ int (*bias_param_to_hw)(enum pin_config_param param);
};
/**
@@ -1000,6 +1004,38 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8
return 0;
}
+static int rzg2l_hw_to_bias_param(unsigned int bias)
+{
+ switch (bias) {
+ case 0:
+ return PIN_CONFIG_BIAS_DISABLE;
+ case 1:
+ return PIN_CONFIG_BIAS_PULL_UP;
+ case 2:
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static int rzg2l_bias_param_to_hw(enum pin_config_param param)
+{
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ return 0;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ return 1;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ return 2;
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int _pin,
unsigned long *config)
@@ -1058,6 +1094,23 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);
break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!(cfg & PIN_CFG_PUPD))
+ return -EINVAL;
+
+ arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK);
+ ret = pctrl->data->hw_to_bias_param(arg);
+ if (ret < 0)
+ return ret;
+
+ if (ret != param)
+ return -EINVAL;
+ /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */
+ arg = 1;
+ break;
+
case PIN_CONFIG_DRIVE_STRENGTH: {
unsigned int index;
@@ -1173,6 +1226,19 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg);
break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!(cfg & PIN_CFG_PUPD))
+ return -EINVAL;
+
+ ret = pctrl->data->bias_param_to_hw(param);
+ if (ret < 0)
+ return ret;
+
+ rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret);
+ break;
+
case PIN_CONFIG_DRIVE_STRENGTH:
arg = pinconf_to_config_argument(_configs[i]);
@@ -2645,6 +2711,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.pmc_writeb = &rzg2l_pmc_writeb,
.oen_read = &rzg2l_read_oen,
.oen_write = &rzg2l_write_oen,
+ .hw_to_bias_param = &rzg2l_hw_to_bias_param,
+ .bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
static struct rzg2l_pinctrl_data r9a07g044_data = {
@@ -2660,6 +2728,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.pmc_writeb = &rzg2l_pmc_writeb,
.oen_read = &rzg2l_read_oen,
.oen_write = &rzg2l_write_oen,
+ .hw_to_bias_param = &rzg2l_hw_to_bias_param,
+ .bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
static struct rzg2l_pinctrl_data r9a08g045_data = {
@@ -2674,6 +2744,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.pmc_writeb = &rzg2l_pmc_writeb,
.oen_read = &rzg2l_read_oen,
.oen_write = &rzg2l_write_oen,
+ .hw_to_bias_param = &rzg2l_hw_to_bias_param,
+ .bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 38/85] pinctrl: renesas: rzg2l: Pass pincontrol device to pinconf_generic_parse_dt_config()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (36 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 37/85] pinctrl: renesas: rzg2l: Add support for pull-up/down Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 39/85] pinctrl: renesas: rzg2l: Add support for custom parameters Tommaso Merciai
` (47 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 6f38a02ad8e0335dd4dda2c42dd599e254cdd91a upstream.
Pass the pincontrol device pointer to pinconf_generic_parse_dt_config()
in preparation for passing custom params.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-13-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 33c96661092b..9c1f32f6e1e4 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -531,7 +531,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
+ ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
if (ret < 0)
return ret;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 39/85] pinctrl: renesas: rzg2l: Add support for custom parameters
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (37 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 38/85] pinctrl: renesas: rzg2l: Pass pincontrol device to pinconf_generic_parse_dt_config() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 40/85] pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc() Tommaso Merciai
` (46 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit d930e8f783daef890980c0ca209a0f4f9ae73160 upstream.
In preparation for passing custom params for RZ/V2H(P) SoC assign the
custom params that are being passed via struct rzg2l_pinctrl_data.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-14-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 9c1f32f6e1e4..538959643cde 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -256,6 +256,11 @@ struct rzg2l_pinctrl_data {
const struct rzg2l_hwcfg *hwcfg;
const u64 *variable_pin_cfg;
unsigned int n_variable_pin_cfg;
+ unsigned int num_custom_params;
+ const struct pinconf_generic_params *custom_params;
+#ifdef CONFIG_DEBUG_FS
+ const struct pin_config_item *custom_conf_items;
+#endif
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
@@ -2290,6 +2295,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
pctrl->desc.confops = &rzg2l_pinctrl_confops;
pctrl->desc.owner = THIS_MODULE;
+ if (pctrl->data->num_custom_params) {
+ pctrl->desc.num_custom_params = pctrl->data->num_custom_params;
+ pctrl->desc.custom_params = pctrl->data->custom_params;
+#ifdef CONFIG_DEBUG_FS
+ pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items;
+#endif
+ }
pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
if (!pins)
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 40/85] pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (38 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 39/85] pinctrl: renesas: rzg2l: Add support for custom parameters Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 41/85] pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC Tommaso Merciai
` (45 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 951eaac107631b26649b00cf5f5d9d7d83d8bca4 upstream.
To keep consistency with rzg2l_pinctrl_set_pfc_mode(), acquire the lock
in rzg2l_pinctrl_pm_setup_pfc() during PFC setup.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-15-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 538959643cde..d42ce90af83a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2541,7 +2541,9 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b
static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
{
u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
+ unsigned long flags;
+ spin_lock_irqsave(&pctrl->lock, flags);
pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
/* Restore port registers. */
@@ -2586,6 +2588,7 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
}
pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
+ spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 41/85] pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (39 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 40/85] pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 42/85] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide Tommaso Merciai
` (44 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 9bd95ac86e700ab8b1a6c225685e0e5afe426b4e upstream.
Add pinctrl driver support for RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-16-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 374 +++++++++++++++++++++++-
1 file changed, 371 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index d42ce90af83a..8c29c8d3c574 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -58,6 +58,10 @@
#define PIN_CFG_OEN BIT(15)
#define PIN_CFG_VARIABLE BIT(16)
#define PIN_CFG_NOGPIO_INT BIT(17)
+#define PIN_CFG_NOD BIT(18) /* N-ch Open Drain */
+#define PIN_CFG_SMT BIT(19) /* Schmitt-trigger input control */
+#define PIN_CFG_ELC BIT(20)
+#define PIN_CFG_IOLH_RZV2H BIT(21)
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
(PIN_CFG_IOLH_##group | \
@@ -72,6 +76,11 @@
#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
PIN_CFG_SOFT_PS)
+#define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \
+ PIN_CFG_NOD | \
+ PIN_CFG_SR | \
+ PIN_CFG_SMT)
+
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
PIN_CFG_FILONOFF | \
PIN_CFG_FILNUM | \
@@ -134,6 +143,7 @@
#define ETH_POC(off, ch) ((off) + (ch) * 4)
#define QSPI (0x3008)
#define ETH_MODE (0x3018)
+#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
#define PVDD_2500 2 /* I/O domain voltage 2.5V */
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
@@ -141,6 +151,8 @@
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
+#define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */
+#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
#define PM_MASK 0x03
#define PFC_MASK 0x07
@@ -159,6 +171,19 @@
#define RZG2L_TINT_IRQ_START_INDEX 9
#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
+/* Custom pinconf parameters */
+#define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1)
+
+static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {
+ { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
+};
+
+#ifdef CONFIG_DEBUG_FS
+static const struct pin_config_item renesas_rzv2h_conf_items[] = {
+ PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
+};
+#endif
+
/* Read/write 8 bits register */
#define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \
do { \
@@ -351,6 +376,15 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
return 0;
}
+static const u64 r9a09g057_variable_pin_cfg[] = {
+ RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+};
+
#ifdef CONFIG_RISCV
static const u64 r9a07g043f_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
@@ -401,6 +435,17 @@ static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
writeb(val, pctrl->base + offset);
}
+static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
+{
+ const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
+ u8 pwpr;
+
+ pwpr = readb(pctrl->base + regs->pwpr);
+ writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr);
+ writeb(val, pctrl->base + offset);
+ writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
+}
+
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 pin, u8 off, u8 func)
{
@@ -1041,14 +1086,104 @@ static int rzg2l_bias_param_to_hw(enum pin_config_param param)
return -EINVAL;
}
+static int rzv2h_hw_to_bias_param(unsigned int bias)
+{
+ switch (bias) {
+ case 0:
+ case 1:
+ return PIN_CONFIG_BIAS_DISABLE;
+ case 2:
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+ case 3:
+ return PIN_CONFIG_BIAS_PULL_UP;
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static int rzv2h_bias_param_to_hw(enum pin_config_param param)
+{
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ return 0;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ return 2;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ return 3;
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
+{
+ static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
+ "XSPI0_RESET0N", "XSPI0_CS0N",
+ "XSPI0_CKN", "XSPI0_CKP" };
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
+ if (!strcmp(pin_desc->name, pin_names[i]))
+ return i;
+ }
+
+ /* Should not happen. */
+ return 0;
+}
+
+static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
+{
+ u8 bit;
+
+ if (!(caps & PIN_CFG_OEN))
+ return 0;
+
+ bit = rzv2h_pin_to_oen_bit(pctrl, offset);
+
+ return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
+}
+
+static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
+{
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
+ const struct rzg2l_register_offsets *regs = &hwcfg->regs;
+ unsigned long flags;
+ u8 val, bit;
+ u8 pwpr;
+
+ if (!(caps & PIN_CFG_OEN))
+ return -EINVAL;
+
+ bit = rzv2h_pin_to_oen_bit(pctrl, offset);
+ spin_lock_irqsave(&pctrl->lock, flags);
+ val = readb(pctrl->base + PFC_OEN);
+ if (oen)
+ val &= ~BIT(bit);
+ else
+ val |= BIT(bit);
+
+ pwpr = readb(pctrl->base + regs->pwpr);
+ writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
+ writeb(val, pctrl->base + PFC_OEN);
+ writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
+ spin_unlock_irqrestore(&pctrl->lock, flags);
+
+ return 0;
+}
+
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int _pin,
unsigned long *config)
{
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
+ u32 param = pinconf_to_config_param(*config);
u64 *pin_data = pin->drv_data;
unsigned int arg = 0;
u32 off;
@@ -1159,6 +1294,13 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
}
+ case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
+ if (!(cfg & PIN_CFG_IOLH_RZV2H))
+ return -EINVAL;
+
+ arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
+ break;
+
default:
return -ENOTSUPP;
}
@@ -1178,9 +1320,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
u64 *pin_data = pin->drv_data;
- enum pin_config_param param;
unsigned int i, arg, index;
- u32 off;
+ u32 off, param;
u64 cfg;
int ret;
u8 bit;
@@ -1285,6 +1426,16 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
break;
+ case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
+ if (!(cfg & PIN_CFG_IOLH_RZV2H))
+ return -EINVAL;
+
+ arg = pinconf_to_config_argument(_configs[i]);
+ if (arg > 3)
+ return -EINVAL;
+ rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);
+ break;
+
default:
return -EOPNOTSUPP;
}
@@ -1732,6 +1883,39 @@ static const u64 r9a08g045_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
};
+static const char * const rzv2h_gpio_names[] = {
+ "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
+ "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
+ "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
+ "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
+ "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
+ "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
+ "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
+ "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
+ "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
+ "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97",
+ "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
+ "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
+};
+
+static const u64 r9a09g057_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
+ RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */
+ RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
+ PIN_CFG_NOD), /* P2 */
+ RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
+ RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
+ RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
+ RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS |
+ PIN_CFG_ELC), /* P6 */
+ RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */
+ RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS |
+ PIN_CFG_ELC), /* P8 */
+ RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */
+ RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */
+ RZG2L_GPIO_PORT_PACK(6, 0x2b, PIN_CFG_VARIABLE), /* PB */
+};
+
static const struct {
struct rzg2l_dedicated_configs common[35];
struct rzg2l_dedicated_configs rzg2l_pins[7];
@@ -1858,6 +2042,138 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
PIN_CFG_IO_VMC_SD1)) },
};
+static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
+ PIN_CFG_FILCLKSEL)) },
+ { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN)) },
+ { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_NOD)) },
+ { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_NOD)) },
+ { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
+ { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
+ { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
+ { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
+ { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
+ { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
+ { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
+ { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
+ { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
+ { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
+ { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
+ { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
+ { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
+ { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
+ { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
+ { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
+ { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
+ { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
+ { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
+ { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
+ { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
+};
+
static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
{
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
@@ -2394,6 +2710,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
ARRAY_SIZE(rzg2l_gpio_names));
+ BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzv2h_gpio_names));
+
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
@@ -2665,6 +2984,22 @@ static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
}
}
+static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
+{
+ const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
+ u8 pwpr;
+
+ if (lock) {
+ /* Set the PWPR register to be write-protected */
+ pwpr = readb(pctrl->base + regs->pwpr);
+ writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
+ } else {
+ /* Set the PWPR register to allow PFC and PMC register to write */
+ pwpr = readb(pctrl->base + regs->pwpr);
+ writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr);
+ }
+}
+
static const struct rzg2l_hwcfg rzg2l_hwcfg = {
.regs = {
.pwpr = 0x3014,
@@ -2710,6 +3045,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
.oen_max_port = 7, /* P7_1 is the maximum OEN port. */
};
+static const struct rzg2l_hwcfg rzv2h_hwcfg = {
+ .regs = {
+ .pwpr = 0x3c04,
+ },
+};
+
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
@@ -2763,6 +3104,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
+static struct rzg2l_pinctrl_data r9a09g057_data = {
+ .port_pins = rzv2h_gpio_names,
+ .port_pin_configs = r9a09g057_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
+ .dedicated_pins = rzv2h_dedicated_pins,
+ .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
+ .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins),
+ .hwcfg = &rzv2h_hwcfg,
+ .variable_pin_cfg = r9a09g057_variable_pin_cfg,
+ .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
+ .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
+ .custom_params = renesas_rzv2h_custom_bindings,
+#ifdef CONFIG_DEBUG_FS
+ .custom_conf_items = renesas_rzv2h_conf_items,
+#endif
+ .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
+ .pmc_writeb = &rzv2h_pmc_writeb,
+ .oen_read = &rzv2h_oen_read,
+ .oen_write = &rzv2h_oen_write,
+ .hw_to_bias_param = &rzv2h_hw_to_bias_param,
+ .bias_param_to_hw = &rzv2h_bias_param_to_hw,
+};
+
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
{
.compatible = "renesas,r9a07g043-pinctrl",
@@ -2776,6 +3140,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
.compatible = "renesas,r9a08g045-pinctrl",
.data = &r9a08g045_data,
},
+ {
+ .compatible = "renesas,r9a09g057-pinctrl",
+ .data = &r9a09g057_data,
+ },
{ /* sentinel */ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 42/85] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (40 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 41/85] pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 43/85] pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62) Tommaso Merciai
` (43 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 0a5e40f9c29756dec3da573edce3f4b3194e6f91 upstream.
Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum
value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 8c29c8d3c574..b4ad4a4d2046 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -88,7 +88,7 @@
#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55)
#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47)
-#define PIN_CFG_MASK GENMASK_ULL(46, 0)
+#define PIN_CFG_MASK GENMASK_ULL(31, 0)
/*
* m indicates the bitmap of supported pins, a is the register index
@@ -1187,7 +1187,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
u64 *pin_data = pin->drv_data;
unsigned int arg = 0;
u32 off;
- u64 cfg;
+ u32 cfg;
int ret;
u8 bit;
@@ -1322,7 +1322,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
u64 *pin_data = pin->drv_data;
unsigned int i, arg, index;
u32 off, param;
- u64 cfg;
+ u32 cfg;
int ret;
u8 bit;
@@ -2755,9 +2755,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
for (u32 port = 0; port < nports; port++) {
bool has_iolh, has_ien;
- u64 cfg, caps;
+ u32 off, caps;
u8 pincnt;
- u32 off;
+ u64 cfg;
cfg = pctrl->data->port_pin_configs[port];
off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
@@ -2801,7 +2801,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
{
struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;
- u64 caps;
+ u32 caps;
u32 i;
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 43/85] pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62)
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (41 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 42/85] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 44/85] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file Tommaso Merciai
` (42 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit f0cdf878a22b91141d6050deed0eac70ab982ebc upstream.
Shift the bit masks for `PIN_CFG_PIN_MAP_MASK` and `PIN_CFG_PIN_REG_MASK`,
to accommodate `PIN_CFG_VARIABLE` using `BIT(62)`.
Previously, these bit masks were placed higher up in the bit range, which
did not leave room for `PIN_CFG_VARIABLE` at `BIT(62)`. By adjusting these
masks, we ensure that `PIN_CFG_VARIABLE` can occupy `BIT(62)` without any
conflicts. The updated masks are now:
- `PIN_CFG_PIN_MAP_MASK`: `GENMASK_ULL(61, 54)` (was `GENMASK_ULL(62, 55)`)
- `PIN_CFG_PIN_REG_MASK`: `GENMASK_ULL(53, 46)` (was `GENMASK_ULL(54, 47)`)
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240618174831.415583-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index b4ad4a4d2046..2a8223a9e226 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -86,8 +86,8 @@
PIN_CFG_FILNUM | \
PIN_CFG_FILCLKSEL)
-#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55)
-#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47)
+#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
+#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
#define PIN_CFG_MASK GENMASK_ULL(31, 0)
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 44/85] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (42 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 43/85] pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62) Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 45/85] pinctrl: renesas: rzg2l: Reorganize variable configuration macro Tommaso Merciai
` (41 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 13dcd63dc704b33a8ad94f1d161c0f5dad243a5b upstream.
Define `RZG2L_SINGLE_PIN` at the top of the file to clarify its use for
dedicated pins for improved readability.
While at it update the comment for `RZG2L_SINGLE_PIN_PACK` macro and place
it just above the macro for clarity.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240618174831.415583-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 2a8223a9e226..d38df51c7118 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -63,6 +63,8 @@
#define PIN_CFG_ELC BIT(20)
#define PIN_CFG_IOLH_RZV2H BIT(21)
+#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
+
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
(PIN_CFG_IOLH_##group | \
PIN_CFG_PUPD | \
@@ -104,15 +106,13 @@
*/
#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
-/*
- * BIT(63) indicates dedicated pin, p is the register index while
- * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
- * (b * 8) and f is the pin configuration capabilities supported.
- */
-#define RZG2L_SINGLE_PIN BIT_ULL(63)
#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)
#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)
-
+/*
+ * p is the register index while referencing to SR/IEN/IOLH/FILxx
+ * registers, b is the register bits (b * 8) and f is the pin
+ * configuration capabilities supported.
+ */
#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 45/85] pinctrl: renesas: rzg2l: Reorganize variable configuration macro
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (43 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 44/85] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 46/85] pinctrl: renesas: rzg2l: Clarify OEN read/write support Tommaso Merciai
` (40 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 87d084bcbf1e8dbe97753e20d30fe9d56a97e6be upstream.
The `PIN_CFG_VARIABLE` macro did not indicate the capabilities of a pin
but served as a flag indicating that the pins of a port have different
capabilities.
To better reflect its purpose, move the `PIN_CFG_VARIABLE` macro beside
`RZG2L_SINGLE_PIN` and rename it to `RZG2L_VARIABLE_CFG`. Additionally,
introduce new macros for packing variable port configurations:
- `RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)`: Combines `RZG2L_VARIABLE_CFG`
with `RZG2L_GPIO_PORT_PACK` to handle variable pin configurations
for a packed port.
- `RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)`: Combines
`RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_SPARSE_PACK` to handle
variable pin configurations for a sparse port.
Due to the above change the configuration macros have been reorganized
as follows:
- Shift the bit positions of `PIN_CFG_NOGPIO_INT`, `PIN_CFG_NOD`,
`PIN_CFG_SMT`, `PIN_CFG_ELC`, and `PIN_CFG_IOLH_RZV2H` down by one
to accommodate the removal of `PIN_CFG_VARIABLE`.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240618174831.415583-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 29 +++++++++++++++----------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index d38df51c7118..7d76e0962e5c 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -56,14 +56,14 @@
#define PIN_CFG_IOLH_C BIT(13)
#define PIN_CFG_SOFT_PS BIT(14)
#define PIN_CFG_OEN BIT(15)
-#define PIN_CFG_VARIABLE BIT(16)
-#define PIN_CFG_NOGPIO_INT BIT(17)
-#define PIN_CFG_NOD BIT(18) /* N-ch Open Drain */
-#define PIN_CFG_SMT BIT(19) /* Schmitt-trigger input control */
-#define PIN_CFG_ELC BIT(20)
-#define PIN_CFG_IOLH_RZV2H BIT(21)
+#define PIN_CFG_NOGPIO_INT BIT(16)
+#define PIN_CFG_NOD BIT(17) /* N-ch Open Drain */
+#define PIN_CFG_SMT BIT(18) /* Schmitt-trigger input control */
+#define PIN_CFG_ELC BIT(19)
+#define PIN_CFG_IOLH_RZV2H BIT(20)
#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
+#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
(PIN_CFG_IOLH_##group | \
@@ -99,12 +99,17 @@
#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
+#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \
+ (RZG2L_VARIABLE_CFG | \
+ RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0))
/*
* n indicates number of pins in the port, a is the register index
* and f is pin configuration capabilities supported.
*/
#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
+#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \
+ RZG2L_GPIO_PORT_PACK(n, a, 0))
#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)
#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)
@@ -370,7 +375,7 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&
FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)
- return (pincfg & ~PIN_CFG_VARIABLE) | FIELD_GET(PIN_CFG_MASK, cfg);
+ return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);
}
return 0;
@@ -1835,13 +1840,13 @@ static const u64 r9a07g043_gpio_configs[] = {
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
- RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
- RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */
- RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */
+ RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |
PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
PIN_CFG_NOGPIO_INT), /* P25 */
@@ -1913,7 +1918,7 @@ static const u64 r9a09g057_gpio_configs[] = {
PIN_CFG_ELC), /* P8 */
RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */
RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */
- RZG2L_GPIO_PORT_PACK(6, 0x2b, PIN_CFG_VARIABLE), /* PB */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */
};
static const struct {
@@ -2637,7 +2642,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
if (i && !(i % RZG2L_PINS_PER_PORT))
j++;
pin_data[i] = pctrl->data->port_pin_configs[j];
- if (pin_data[i] & PIN_CFG_VARIABLE)
+ if (pin_data[i] & RZG2L_VARIABLE_CFG)
pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
pin_data[i],
j,
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 46/85] pinctrl: renesas: rzg2l: Clarify OEN read/write support
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (44 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 45/85] pinctrl: renesas: rzg2l: Reorganize variable configuration macro Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 47/85] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions Tommaso Merciai
` (39 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Paul Barker <paul.barker.ct@bp.renesas.com>
commit 07dd08c39eb4b645a0e2f2440a54326b49944705 upstream.
We currently support OEN read/write for the RZ/G3S SoC but not the
RZ/G2L SoC family (consisting of RZ/G2L, RZ/G2LC, RZ/G2UL, RZ/V2L &
RZ/Five). The appropriate functions are renamed to clarify this and to
match the callback names.
We should also only set the oen_read and oen_write function pointers for
the devices which support these operations. This requires us to check
that these function pointers are valid before calling them.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240625200316.4282-2-paul.barker.ct@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 28 ++++++++++++-------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 7d76e0962e5c..5159dff565b7 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -999,7 +999,7 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
return false;
}
-static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
+static bool rzg3s_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
{
if (!(caps & PIN_CFG_OEN))
return false;
@@ -1010,7 +1010,7 @@ static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
return true;
}
-static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
+static u8 rzg3s_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
{
if (pin)
pin *= 2;
@@ -1021,31 +1021,31 @@ static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
return pin;
}
-static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
+static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
{
u8 max_port = pctrl->data->hwcfg->oen_max_port;
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
u8 bit;
- if (!rzg2l_oen_is_supported(caps, pin, max_pin))
+ if (!rzg3s_oen_is_supported(caps, pin, max_pin))
return 0;
- bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
+ bit = rzg3s_pin_to_oen_bit(offset, pin, max_port);
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
}
-static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
+static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
{
u8 max_port = pctrl->data->hwcfg->oen_max_port;
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
unsigned long flags;
u8 val, bit;
- if (!rzg2l_oen_is_supported(caps, pin, max_pin))
+ if (!rzg3s_oen_is_supported(caps, pin, max_pin))
return -EINVAL;
- bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
+ bit = rzg3s_pin_to_oen_bit(offset, pin, max_port);
spin_lock_irqsave(&pctrl->lock, flags);
val = readb(pctrl->base + ETH_MODE);
@@ -1220,6 +1220,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
+ if (!pctrl->data->oen_read)
+ return -EOPNOTSUPP;
arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit);
if (!arg)
return -EINVAL;
@@ -1359,6 +1361,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_OUTPUT_ENABLE:
arg = pinconf_to_config_argument(_configs[i]);
+ if (!pctrl->data->oen_write)
+ return -EOPNOTSUPP;
ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg);
if (ret)
return ret;
@@ -3070,8 +3074,6 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
#endif
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
@@ -3087,8 +3089,6 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.hwcfg = &rzg2l_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
@@ -3103,8 +3103,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.hwcfg = &rzg3s_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
+ .oen_read = &rzg3s_oen_read,
+ .oen_write = &rzg3s_oen_write,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 47/85] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (45 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 46/85] pinctrl: renesas: rzg2l: Clarify OEN read/write support Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 48/85] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L Tommaso Merciai
` (38 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Paul Barker <paul.barker.ct@bp.renesas.com>
commit a9024a323af2235a6d11cbbde924c6dde8bd355b upstream.
The variable naming in the various OEN functions has been confusing. We
were passing the _pin & bit variables from rzg2l_pinctrl_pinconf_get()
and rzg2l_pinctrl_pinconf_set() as the offset & pin argument to the
oen_read() and oen_write() functions. This doesn't make sense, the first
of these isn't actually an offset and the second is not needed for
RZ/V2H but leads to confusion with the bit variable used within these
functions.
To tidy this up, instead pass the _pin variable directly to the
oen_read() and oen_write() functions with consistent naming. Then
rzg3s_read_oen() and rzg3s_write_oen() can use macros to get the port
and pin numbers it needs.
Instead of passing the pin capabilities into oen_read() and oen_write(),
check that the pin supports OEN before calling these functions.
Also, merge rzg3s_oen_is_supported() into rzg3s_pin_to_oen_bit() to give
a single translation function which returns an error if the pin doesn't
support OEN. While we're here, remove an unnecessary branch and clarify
the variable naming. Lastly, check that we are not dealing with a
dedicated pin before calling RZG2L_PIN_ID_TO_{PORT,PIN}().
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240625200316.4282-3-paul.barker.ct@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 85 +++++++++++--------------
1 file changed, 36 insertions(+), 49 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 5159dff565b7..6b383f2baf47 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -293,8 +293,8 @@ struct rzg2l_pinctrl_data {
#endif
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
- u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
- int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);
+ u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
+ int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
int (*hw_to_bias_param)(unsigned int val);
int (*bias_param_to_hw)(enum pin_config_param param);
};
@@ -999,53 +999,46 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
return false;
}
-static bool rzg3s_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
+static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
{
- if (!(caps & PIN_CFG_OEN))
- return false;
-
- if (pin > max_pin)
- return false;
+ u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
+ u8 port, pin, bit;
- return true;
-}
+ if (*pin_data & RZG2L_SINGLE_PIN)
+ return -EINVAL;
-static u8 rzg3s_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
-{
- if (pin)
- pin *= 2;
+ port = RZG2L_PIN_ID_TO_PORT(_pin);
+ pin = RZG2L_PIN_ID_TO_PIN(_pin);
+ if (pin > pctrl->data->hwcfg->oen_max_pin)
+ return -EINVAL;
- if (offset / RZG2L_PINS_PER_PORT == max_port)
- pin += 1;
+ bit = pin * 2;
+ if (port == pctrl->data->hwcfg->oen_max_port)
+ bit += 1;
- return pin;
+ return bit;
}
-static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
+static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
{
- u8 max_port = pctrl->data->hwcfg->oen_max_port;
- u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
- u8 bit;
-
- if (!rzg3s_oen_is_supported(caps, pin, max_pin))
- return 0;
+ int bit;
- bit = rzg3s_pin_to_oen_bit(offset, pin, max_port);
+ bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
+ if (bit < 0)
+ return bit;
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
}
-static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
+static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
{
- u8 max_port = pctrl->data->hwcfg->oen_max_port;
- u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
unsigned long flags;
- u8 val, bit;
-
- if (!rzg3s_oen_is_supported(caps, pin, max_pin))
- return -EINVAL;
+ int bit;
+ u8 val;
- bit = rzg3s_pin_to_oen_bit(offset, pin, max_port);
+ bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
+ if (bit < 0)
+ return bit;
spin_lock_irqsave(&pctrl->lock, flags);
val = readb(pctrl->base + ETH_MODE);
@@ -1124,12 +1117,12 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param)
return -EINVAL;
}
-static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
+static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
{
static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
"XSPI0_RESET0N", "XSPI0_CS0N",
"XSPI0_CKN", "XSPI0_CKP" };
- const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
+ const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
unsigned int i;
for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
@@ -1141,19 +1134,16 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
return 0;
}
-static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
+static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
{
u8 bit;
- if (!(caps & PIN_CFG_OEN))
- return 0;
-
- bit = rzv2h_pin_to_oen_bit(pctrl, offset);
+ bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
}
-static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
+static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
{
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
@@ -1161,10 +1151,7 @@ static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8
u8 val, bit;
u8 pwpr;
- if (!(caps & PIN_CFG_OEN))
- return -EINVAL;
-
- bit = rzv2h_pin_to_oen_bit(pctrl, offset);
+ bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
spin_lock_irqsave(&pctrl->lock, flags);
val = readb(pctrl->base + PFC_OEN);
if (oen)
@@ -1220,9 +1207,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
- if (!pctrl->data->oen_read)
+ if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN))
return -EOPNOTSUPP;
- arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit);
+ arg = pctrl->data->oen_read(pctrl, _pin);
if (!arg)
return -EINVAL;
break;
@@ -1361,9 +1348,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_OUTPUT_ENABLE:
arg = pinconf_to_config_argument(_configs[i]);
- if (!pctrl->data->oen_write)
+ if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN))
return -EOPNOTSUPP;
- ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg);
+ ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
if (ret)
return ret;
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 48/85] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (46 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 47/85] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 49/85] pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support PIN_CFG_OEN Tommaso Merciai
` (37 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Paul Barker <paul.barker.ct@bp.renesas.com>
commit 2453e858e945e5e2fa8da9fde8584995e7dd17d1 upstream.
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
signal is selectable to support an Ethernet PHY operating in either MII
or RGMII mode. By default, the signal is configured as an input and MII
mode is supported. The ETH_MODE register can be modified to configure
this signal as an output to support RGMII mode.
As this signal is by default an input, and can optionally be switched to
an output, it maps neatly onto an `output-enable` property in the device
tree.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240625200316.4282-4-paul.barker.ct@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 67 +++++++++++++++++++++++--
1 file changed, 63 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 6b383f2baf47..ba0122b46da0 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -999,6 +999,60 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
return false;
}
+static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
+{
+ u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
+ u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
+ u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
+
+ if (pin > pctrl->data->hwcfg->oen_max_pin)
+ return -EINVAL;
+
+ /*
+ * We can determine which Ethernet interface we're dealing with from
+ * the caps.
+ */
+ if (caps & PIN_CFG_IO_VMC_ETH0)
+ return 0;
+ if (caps & PIN_CFG_IO_VMC_ETH1)
+ return 1;
+
+ return -EINVAL;
+}
+
+static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
+{
+ int bit;
+
+ bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
+ if (bit < 0)
+ return 0;
+
+ return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
+}
+
+static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
+{
+ unsigned long flags;
+ int bit;
+ u8 val;
+
+ bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
+ if (bit < 0)
+ return bit;
+
+ spin_lock_irqsave(&pctrl->lock, flags);
+ val = readb(pctrl->base + ETH_MODE);
+ if (oen)
+ val &= ~BIT(bit);
+ else
+ val |= BIT(bit);
+ writeb(val, pctrl->base + ETH_MODE);
+ spin_unlock_irqrestore(&pctrl->lock, flags);
+
+ return 0;
+}
+
static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
{
u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
@@ -1775,7 +1829,7 @@ static const u64 r9a07g044_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
@@ -1784,7 +1838,7 @@ static const u64 r9a07g044_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -1808,13 +1862,13 @@ static const u64 r9a07g044_gpio_configs[] = {
static const u64 r9a07g043_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -3007,6 +3061,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
},
.iolh_groupb_oi = { 100, 66, 50, 33, },
+ .oen_max_pin = 0,
};
static const struct rzg2l_hwcfg rzg3s_hwcfg = {
@@ -3061,6 +3116,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
#endif
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
@@ -3076,6 +3133,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.hwcfg = &rzg2l_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 49/85] pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support PIN_CFG_OEN
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (47 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 48/85] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 50/85] pinctrl: renesas: rzg2l: Use dev_err_probe() Tommaso Merciai
` (36 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit d56abfed1c02814b5ee96b0ed1f989ea9d7f6cbb upstream.
Update the rzg2l_pinctrl_pinconf_get() function to return -EINVAL for
PIN_CONFIG_OUTPUT_ENABLE config if the pin doesn't support the PIN_CFG_OEN
configuration.
-EINVAL is a valid error when dumping the pin configurations. Returning
-EOPNOTSUPP for a pin that does not support PIN_CFG_OEN resulted in the
message 'ERROR READING CONFIG SETTING 16' being printed during dumping
pinconf-pins.
For consistency do similar change in rzg2l_pinctrl_pinconf_set() for
PIN_CONFIG_OUTPUT_ENABLE config.
Fixes: a9024a323af2 ("pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240723164744.505233-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index ba0122b46da0..7168495da565 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1261,7 +1261,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
- if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN))
+ if (!(cfg & PIN_CFG_OEN))
+ return -EINVAL;
+ if (!pctrl->data->oen_read)
return -EOPNOTSUPP;
arg = pctrl->data->oen_read(pctrl, _pin);
if (!arg)
@@ -1402,7 +1404,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_OUTPUT_ENABLE:
arg = pinconf_to_config_argument(_configs[i]);
- if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN))
+ if (!(cfg & PIN_CFG_OEN))
+ return -EINVAL;
+ if (!pctrl->data->oen_write)
return -EOPNOTSUPP;
ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
if (ret)
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 50/85] pinctrl: renesas: rzg2l: Use dev_err_probe()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (48 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 49/85] pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support PIN_CFG_OEN Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 51/85] mm/util: Introduce kmemdup_array() Tommaso Merciai
` (35 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit f73f63b24491fa43641daf3b6162d2a451bd8481 upstream.
Replace dev_err()->dev_err_probe() to simpilfy probe
helper functions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240728090421.7136-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 37 +++++++++----------------
1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 7168495da565..bc671807bad5 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2600,16 +2600,13 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
return -EPROBE_DEFER;
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
- if (ret) {
- dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
- return ret;
- }
+ if (ret)
+ return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n");
if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
- of_args.args[2] != pctrl->data->n_port_pins) {
- dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
- return -EINVAL;
- }
+ of_args.args[2] != pctrl->data->n_port_pins)
+ return dev_err_probe(pctrl->dev, -EINVAL,
+ "gpio-ranges does not match selected SOC\n");
chip->names = pctrl->data->port_pins;
chip->request = rzg2l_gpio_request;
@@ -2641,10 +2638,8 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
pctrl->gpio_range.name = chip->label;
pctrl->gpio_range.gc = chip;
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
- if (ret) {
- dev_err(pctrl->dev, "failed to add GPIO controller\n");
- return ret;
- }
+ if (ret)
+ return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n");
dev_dbg(pctrl->dev, "Registered gpio controller\n");
@@ -2730,22 +2725,16 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
&pctrl->pctl);
- if (ret) {
- dev_err(pctrl->dev, "pinctrl registration failed\n");
- return ret;
- }
+ if (ret)
+ return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n");
ret = pinctrl_enable(pctrl->pctl);
- if (ret) {
- dev_err(pctrl->dev, "pinctrl enable failed\n");
- return ret;
- }
+ if (ret)
+ dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");
ret = rzg2l_gpio_register(pctrl);
- if (ret) {
- dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
- return ret;
- }
+ if (ret)
+ return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n");
return 0;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 51/85] mm/util: Introduce kmemdup_array()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (49 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 50/85] pinctrl: renesas: rzg2l: Use dev_err_probe() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 52/85] pinctrl: renesas: Switch to use kmemdup_array() Tommaso Merciai
` (34 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Kartik <kkartik@nvidia.com>
commit 7092e9b3bed1252c7d3f5812b9fb9d82375b73a6 upstream.
Introduce kmemdup_array() API to duplicate `n` number of elements
from a given array. This internally uses kmemdup to allocate and duplicate
the `src` array.
Signed-off-by: Kartik <kkartik@nvidia.com>
Acked-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
include/linux/string.h | 1 +
mm/util.c | 17 +++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/include/linux/string.h b/include/linux/string.h
index 422606e98cc4..066203187c8d 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -218,6 +218,7 @@ extern const char *kstrdup_const(const char *s, gfp_t gfp);
extern char *kstrndup(const char *s, size_t len, gfp_t gfp);
extern void *kmemdup(const void *src, size_t len, gfp_t gfp);
extern char *kmemdup_nul(const char *s, size_t len, gfp_t gfp);
+extern void *kmemdup_array(const void *src, size_t element_size, size_t count, gfp_t gfp);
extern char **argv_split(gfp_t gfp, const char *str, int *argcp);
extern void argv_free(char **argv);
diff --git a/mm/util.c b/mm/util.c
index d3a2877c176f..770803ece795 100644
--- a/mm/util.c
+++ b/mm/util.c
@@ -133,6 +133,23 @@ void *kmemdup(const void *src, size_t len, gfp_t gfp)
}
EXPORT_SYMBOL(kmemdup);
+/**
+ * kmemdup_array - duplicate a given array.
+ *
+ * @src: array to duplicate.
+ * @element_size: size of each element of array.
+ * @count: number of elements to duplicate from array.
+ * @gfp: GFP mask to use.
+ *
+ * Return: duplicated array of @src or %NULL in case of error,
+ * result is physically contiguous. Use kfree() to free.
+ */
+void *kmemdup_array(const void *src, size_t element_size, size_t count, gfp_t gfp)
+{
+ return kmemdup(src, size_mul(element_size, count), gfp);
+}
+EXPORT_SYMBOL(kmemdup_array);
+
/**
* kmemdup_nul - Create a NUL-terminated string from unterminated data
* @s: The data to stringify
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 52/85] pinctrl: renesas: Switch to use kmemdup_array()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (50 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 51/85] mm/util: Introduce kmemdup_array() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 53/85] pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API Tommaso Merciai
` (33 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Shen Lichuan <shenlichuan@vivo.com>
commit 5e633f572bbae9397ee50347bbe0529894de4137 upstream.
Let kmemdup_array() take care of multiplication and possible overflow.
Signed-off-by: Shen Lichuan <shenlichuan@vivo.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240822061438.14617-1-shenlichuan@vivo.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 +--
drivers/pinctrl/renesas/pinctrl-rzv2m.c | 3 +--
drivers/pinctrl/renesas/pinctrl.c | 3 +--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index bc671807bad5..4c111fb27845 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -527,8 +527,7 @@ static int rzg2l_map_add_config(struct pinctrl_map *map,
{
unsigned long *cfgs;
- cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
- GFP_KERNEL);
+ cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
if (!cfgs)
return -ENOMEM;
diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c
index c2845f665412..32fa51abc2d3 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c
@@ -196,8 +196,7 @@ static int rzv2m_map_add_config(struct pinctrl_map *map,
{
unsigned long *cfgs;
- cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
- GFP_KERNEL);
+ cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
if (!cfgs)
return -ENOMEM;
diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index b74147800319..0cbeb70c1d7b 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -87,8 +87,7 @@ static int sh_pfc_map_add_config(struct pinctrl_map *map,
{
unsigned long *cfgs;
- cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
- GFP_KERNEL);
+ cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
if (cfgs == NULL)
return -ENOMEM;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 53/85] pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (51 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 52/85] pinctrl: renesas: Switch to use kmemdup_array() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 54/85] pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration Tommaso Merciai
` (32 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Andy Shevchenko <andy.shevchenko@gmail.com>
commit dad83b9527030e29cc3148f7274910cf40fe7f1a upstream.
of_node_to_fwnode() is a IRQ domain specific implementation of
of_fwnode_handle(). Replace the former with more suitable API.
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240822230104.707812-1-andy.shevchenko@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 4c111fb27845..bd739879055a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -15,6 +15,7 @@
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
+#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
@@ -2623,7 +2624,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
girq = &chip->irq;
gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);
- girq->fwnode = of_node_to_fwnode(np);
+ girq->fwnode = dev_fwnode(pctrl->dev);
girq->parent_domain = parent_domain;
girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 54/85] pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (52 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 53/85] pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 55/85] pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases Tommaso Merciai
` (31 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit befcded23454825ca2cc4c24626b68c75fcb1528 upstream.
Support for enabling the digital noise filter, and support for
configuring the noise filter stages (via the FILNUM register) and the
sampling interval (via the FILCLKSEL register) are related: a pin
supports either all or none of them. Hence simplify declaring digital
noise filter support for a pin by using a single feature flag instead of
three separate flags.
This patch removes the PIN_CFG_FILNUM and PIN_CFG_FILCLKSEL configuration
macros and renames PIN_CFG_FILONOFF to PIN_CFG_NF.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240829194841.84398-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 52 ++++++++++---------------
1 file changed, 20 insertions(+), 32 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index bd739879055a..d5249955c9a4 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -51,17 +51,15 @@
#define PIN_CFG_IO_VMC_QSPI BIT(7)
#define PIN_CFG_IO_VMC_ETH0 BIT(8)
#define PIN_CFG_IO_VMC_ETH1 BIT(9)
-#define PIN_CFG_FILONOFF BIT(10)
-#define PIN_CFG_FILNUM BIT(11)
-#define PIN_CFG_FILCLKSEL BIT(12)
-#define PIN_CFG_IOLH_C BIT(13)
-#define PIN_CFG_SOFT_PS BIT(14)
-#define PIN_CFG_OEN BIT(15)
-#define PIN_CFG_NOGPIO_INT BIT(16)
-#define PIN_CFG_NOD BIT(17) /* N-ch Open Drain */
-#define PIN_CFG_SMT BIT(18) /* Schmitt-trigger input control */
-#define PIN_CFG_ELC BIT(19)
-#define PIN_CFG_IOLH_RZV2H BIT(20)
+#define PIN_CFG_NF BIT(10) /* Digital noise filter */
+#define PIN_CFG_IOLH_C BIT(11)
+#define PIN_CFG_SOFT_PS BIT(12)
+#define PIN_CFG_OEN BIT(13)
+#define PIN_CFG_NOGPIO_INT BIT(14)
+#define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
+#define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
+#define PIN_CFG_ELC BIT(17)
+#define PIN_CFG_IOLH_RZV2H BIT(18)
#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
@@ -69,9 +67,7 @@
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
(PIN_CFG_IOLH_##group | \
PIN_CFG_PUPD | \
- PIN_CFG_FILONOFF | \
- PIN_CFG_FILNUM | \
- PIN_CFG_FILCLKSEL)
+ PIN_CFG_NF)
#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
PIN_CFG_SR)
@@ -84,10 +80,7 @@
PIN_CFG_SR | \
PIN_CFG_SMT)
-#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
- PIN_CFG_FILONOFF | \
- PIN_CFG_FILNUM | \
- PIN_CFG_FILCLKSEL)
+#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)
#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
@@ -394,13 +387,13 @@ static const u64 r9a09g057_variable_pin_cfg[] = {
#ifdef CONFIG_RISCV
static const u64 r9a07g043f_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ PIN_CFG_NF |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ PIN_CFG_NF |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ PIN_CFG_NF |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
@@ -431,7 +424,7 @@ static const u64 r9a07g043f_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_NOGPIO_INT),
RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ PIN_CFG_NF |
PIN_CFG_NOGPIO_INT),
};
#endif
@@ -1887,8 +1880,7 @@ static const u64 r9a07g043_gpio_configs[] = {
#ifdef CONFIG_RISCV
/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
- PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
- PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
+ PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
@@ -1896,8 +1888,7 @@ static const u64 r9a07g043_gpio_configs[] = {
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */
- RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |
- PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
+ RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF |
PIN_CFG_NOGPIO_INT), /* P25 */
0x0, /* P26 */
0x0, /* P27 */
@@ -1975,8 +1966,7 @@ static const struct {
struct rzg2l_dedicated_configs rzg2l_pins[7];
} rzg2l_dedicated_pins = {
.common = {
- { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
- (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
@@ -2057,8 +2047,7 @@ static const struct {
};
static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
- { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
- PIN_CFG_FILCLKSEL)) },
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) },
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
PIN_CFG_SOFT_PS)) },
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
@@ -2097,8 +2086,7 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
};
static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
- { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
- PIN_CFG_FILCLKSEL)) },
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
PIN_CFG_IEN)) },
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 55/85] pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (53 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 54/85] pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 56/85] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX Tommaso Merciai
` (30 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 1325820dd085809645bdd89a2fd408a05b4a5492 upstream.
Refactor the `rzg2l_pinctrl_pinconf_set()` function by moving the call to
`arg = pinconf_to_config_argument(_configs[i])` to the beginning of the
loop. Previously, this call was redundantly made in most cases within the
switch statement.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240829194841.84398-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index d5249955c9a4..5919a9c441be 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1385,9 +1385,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(_configs[i]);
+ arg = pinconf_to_config_argument(_configs[i]);
switch (param) {
case PIN_CONFIG_INPUT_ENABLE:
- arg = pinconf_to_config_argument(_configs[i]);
if (!(cfg & PIN_CFG_IEN))
return -EINVAL;
@@ -1396,7 +1396,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
- arg = pinconf_to_config_argument(_configs[i]);
if (!(cfg & PIN_CFG_OEN))
return -EINVAL;
if (!pctrl->data->oen_write)
@@ -1407,12 +1406,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_POWER_SOURCE:
- settings.power_source = pinconf_to_config_argument(_configs[i]);
+ settings.power_source = arg;
break;
case PIN_CONFIG_SLEW_RATE:
- arg = pinconf_to_config_argument(_configs[i]);
-
if (!(cfg & PIN_CFG_SR) || arg > 1)
return -EINVAL;
@@ -1433,8 +1430,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_DRIVE_STRENGTH:
- arg = pinconf_to_config_argument(_configs[i]);
-
if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
return -EINVAL;
@@ -1454,12 +1449,10 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
!hwcfg->drive_strength_ua)
return -EINVAL;
- settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]);
+ settings.drive_strength_ua = arg;
break;
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
- arg = pinconf_to_config_argument(_configs[i]);
-
if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
return -EINVAL;
@@ -1477,7 +1470,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
if (!(cfg & PIN_CFG_IOLH_RZV2H))
return -EINVAL;
- arg = pinconf_to_config_argument(_configs[i]);
if (arg > 3)
return -EINVAL;
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 56/85] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (54 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 55/85] pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 57/85] pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register() Tommaso Merciai
` (29 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
commit 1d930d4bf8e68c2a7122a6d0899a99f0370c45b1 upstream.
The RZ/V2H(P) SoC has 16 IRQ interrupts, while every other SoC has 8,
and this affects the start index of TINT interrupts (1 + 16 = 17, rather
than 1 + 8 = 9).
Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace it with a
new member within struct rzg2l_hwcfg.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20240930145244.356565-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 5919a9c441be..4ccdcb145704 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -167,7 +167,6 @@
#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
#define RZG2L_TINT_MAX_INTERRUPT 32
-#define RZG2L_TINT_IRQ_START_INDEX 9
#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
/* Custom pinconf parameters */
@@ -246,6 +245,7 @@ enum rzg2l_iolh_index {
* @iolh_groupb_ua: IOLH group B uA specific values
* @iolh_groupc_ua: IOLH group C uA specific values
* @iolh_groupb_oi: IOLH group B output impedance specific values
+ * @tint_start_index: the start index for the TINT interrupts
* @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
* @func_base: base number for port function (see register PFC)
* @oen_max_pin: the maximum pin number supporting output enable
@@ -257,6 +257,7 @@ struct rzg2l_hwcfg {
u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
u16 iolh_groupb_oi[4];
+ u16 tint_start_index;
bool drive_strength_ua;
u8 func_base;
u8 oen_max_pin;
@@ -2379,7 +2380,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
rzg2l_gpio_irq_endisable(pctrl, child, true);
pctrl->hwirq[irq] = child;
- irq += RZG2L_TINT_IRQ_START_INDEX;
+ irq += pctrl->data->hwcfg->tint_start_index;
/* All these interrupts are level high in the CPU */
*parent_type = IRQ_TYPE_LEVEL_HIGH;
@@ -3034,6 +3035,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
},
.iolh_groupb_oi = { 100, 66, 50, 33, },
+ .tint_start_index = 9,
.oen_max_pin = 0,
};
@@ -3063,6 +3065,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
/* 3v3 power source */
[RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
},
+ .tint_start_index = 9,
.drive_strength_ua = true,
.func_base = 1,
.oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
@@ -3073,6 +3076,7 @@ static const struct rzg2l_hwcfg rzv2h_hwcfg = {
.regs = {
.pwpr = 0x3c04,
},
+ .tint_start_index = 17,
};
static struct rzg2l_pinctrl_data r9a07g043_data = {
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 57/85] pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (55 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 56/85] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 58/85] pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs Tommaso Merciai
` (28 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 1737715a4c2c08f207c94cc1f3af3c5945318d29 upstream.
Fix the missing return statement in the error path of
rzg2l_pinctrl_register().
Fixes: f73f63b24491fa43 ("pinctrl: renesas: rzg2l: Use dev_err_probe()")
Reported-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Closes: https://lore.kernel.org/all/OS0PR01MB638837327E5487B71D88A70392712@OS0PR01MB6388.jpnprd01.prod.outlook.com/
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241003082550.33341-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 4ccdcb145704..c6ee32a7a941 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2711,7 +2711,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
ret = pinctrl_enable(pctrl->pctl);
if (ret)
- dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");
+ return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");
ret = rzg2l_gpio_register(pctrl);
if (ret)
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 58/85] pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (56 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 57/85] pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 59/85] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger Tommaso Merciai
` (27 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 9d75b70061917fbfe3247e2594879e5a14d3e24a upstream.
Add support for enabling and disabling open-drain outputs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241004123658.764557-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index c6ee32a7a941..834fac5db21e 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -138,6 +138,7 @@
#define IEN(off) (0x1800 + (off) * 8)
#define PUPD(off) (0x1C00 + (off) * 8)
#define ISEL(off) (0x2C00 + (off) * 8)
+#define NOD(off) (0x3000 + (off) * 8)
#define SD_CH(off, ch) ((off) + (ch) * 4)
#define ETH_POC(off, ch) ((off) + (ch) * 4)
#define QSPI (0x3008)
@@ -159,6 +160,7 @@
#define IOLH_MASK 0x03
#define SR_MASK 0x01
#define PUPD_MASK 0x03
+#define NOD_MASK 0x01
#define PM_INPUT 0x1
#define PM_OUTPUT 0x2
@@ -1338,6 +1340,18 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
}
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (!(cfg & PIN_CFG_NOD))
+ return -EINVAL;
+
+ arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK);
+ if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL)
+ return -EINVAL;
+ if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN)
+ return -EINVAL;
+ break;
+
case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
if (!(cfg & PIN_CFG_IOLH_RZV2H))
return -EINVAL;
@@ -1467,6 +1481,15 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (!(cfg & PIN_CFG_NOD))
+ return -EINVAL;
+
+ rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK,
+ param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0);
+ break;
+
case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
if (!(cfg & PIN_CFG_IOLH_RZV2H))
return -EINVAL;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 59/85] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (57 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 58/85] pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 60/85] pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper Tommaso Merciai
` (26 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 725933a54f718af5362ec39971b2933d8bdf6994 upstream.
Add support for configuring the multiplexed pins as schmitt-trigger
inputs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241004123658.764557-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 834fac5db21e..36f1a82352fb 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -139,6 +139,7 @@
#define PUPD(off) (0x1C00 + (off) * 8)
#define ISEL(off) (0x2C00 + (off) * 8)
#define NOD(off) (0x3000 + (off) * 8)
+#define SMT(off) (0x3400 + (off) * 8)
#define SD_CH(off, ch) ((off) + (ch) * 4)
#define ETH_POC(off, ch) ((off) + (ch) * 4)
#define QSPI (0x3008)
@@ -161,6 +162,7 @@
#define SR_MASK 0x01
#define PUPD_MASK 0x03
#define NOD_MASK 0x01
+#define SMT_MASK 0x01
#define PM_INPUT 0x1
#define PM_OUTPUT 0x2
@@ -1352,6 +1354,15 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
return -EINVAL;
break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!(cfg & PIN_CFG_SMT))
+ return -EINVAL;
+
+ arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK);
+ if (!arg)
+ return -EINVAL;
+ break;
+
case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
if (!(cfg & PIN_CFG_IOLH_RZV2H))
return -EINVAL;
@@ -1490,6 +1501,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0);
break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!(cfg & PIN_CFG_SMT))
+ return -EINVAL;
+
+ rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg);
+ break;
+
case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
if (!(cfg & PIN_CFG_IOLH_RZV2H))
return -EINVAL;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 60/85] pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (58 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 59/85] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 61/85] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table Tommaso Merciai
` (25 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit f407af78c8d3b6035f81152b15ad67063f42514e upstream.
Because rzg2l_gpio_populate_parent_fwspec() and
gpiochip_populate_parent_fwspec_twocell() are identical.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241017113942.139712-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 +----------------
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 36f1a82352fb..353f9b139413 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2433,21 +2433,6 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
return ret;
}
-static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip,
- union gpio_irq_fwspec *gfwspec,
- unsigned int parent_hwirq,
- unsigned int parent_type)
-{
- struct irq_fwspec *fwspec = &gfwspec->fwspec;
-
- fwspec->fwnode = chip->irq.parent_domain->fwnode;
- fwspec->param_count = 2;
- fwspec->param[0] = parent_hwirq;
- fwspec->param[1] = parent_type;
-
- return 0;
-}
-
static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
{
struct irq_domain *domain = pctrl->gpio_chip.irq.domain;
@@ -2649,7 +2634,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
girq->fwnode = dev_fwnode(pctrl->dev);
girq->parent_domain = parent_domain;
girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
- girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
+ girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
girq->init_valid_mask = rzg2l_init_irq_valid_mask;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 61/85] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (59 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 60/85] pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 62/85] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC Tommaso Merciai
` (24 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 0ce66380a7c7566c91d4a159751d5801280957c1 upstream.
Currently r9a09g057_variable_pin_cfg table uses port 11 instead of port PB
as mentioned in the hardware manual. Update the r9a09g057_variable_pin_cfg
table with alpha-numeric port names to match with the hardware manual.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241216195325.164212-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 353f9b139413..045033fc84f2 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -25,6 +25,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
+#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#include "../core.h"
@@ -381,12 +382,12 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
}
static const u64 r9a09g057_variable_pin_cfg[] = {
- RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),
- RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
- RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
- RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
- RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
- RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
};
#ifdef CONFIG_RISCV
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 62/85] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (60 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 61/85] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 63/85] pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E Tommaso Merciai
` (23 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 829356da700bbe07e13b4403997bf8c5aac64660 upstream.
Add pinctrl driver support for RZ/G3E SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241216195325.164212-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/Kconfig | 1 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 173 ++++++++++++++++++++++++
2 files changed, 174 insertions(+)
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 5fc190fa2f68..6efe4bc69831 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -41,6 +41,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A779G0 if ARCH_R8A779G0
select PINCTRL_RZG2L if ARCH_RZG2L
select PINCTRL_RZV2M if ARCH_R9A09G011
+ select PINCTRL_RZG2L if ARCH_R9A09G047
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 045033fc84f2..36ef1b558ae3 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -25,6 +25,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
+#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
@@ -381,6 +382,44 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
return 0;
}
+static const u64 r9a09g047_variable_pin_cfg[] = {
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
+};
+
static const u64 r9a09g057_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
@@ -1963,6 +2002,73 @@ static const u64 r9a08g045_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
};
+static const char * const rzg3e_gpio_names[] = {
+ "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
+ "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
+ "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
+ "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
+ "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
+ "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
+ "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
+ "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
+ "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
+ "", "", "", "", "", "", "", "",
+ "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
+ "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
+ "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
+ "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
+ "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
+ "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
+ "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
+ "", "", "", "", "", "", "", "",
+ "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
+ "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
+ "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
+ "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
+};
+
+static const u64 r9a09g047_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
+ RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS |
+ PIN_CFG_ELC), /* P1 */
+ RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
+ PIN_CFG_NOD), /* P2 */
+ RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
+ RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
+ RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
+ RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */
+ RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS |
+ PIN_CFG_ELC), /* P7 */
+ RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */
+ 0x0,
+ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
+ RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */
+ RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
+ RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */
+ RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
+ 0x0,
+ RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
+ RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */
+ RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */
+ RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */
+};
+
static const char * const rzv2h_gpio_names[] = {
"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
@@ -2251,6 +2357,43 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
};
+static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
+ { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
+ { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
+ { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
+ { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
+ { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7,
+ (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+};
+
static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
{
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
@@ -2761,6 +2904,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
ARRAY_SIZE(rzg2l_gpio_names));
+ BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzg3e_gpio_names));
+
BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
ARRAY_SIZE(rzv2h_gpio_names));
@@ -3159,6 +3305,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
+static struct rzg2l_pinctrl_data r9a09g047_data = {
+ .port_pins = rzg3e_gpio_names,
+ .port_pin_configs = r9a09g047_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs),
+ .dedicated_pins = rzg3e_dedicated_pins,
+ .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
+ .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
+ .hwcfg = &rzv2h_hwcfg,
+ .variable_pin_cfg = r9a09g047_variable_pin_cfg,
+ .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
+ .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
+ .custom_params = renesas_rzv2h_custom_bindings,
+#ifdef CONFIG_DEBUG_FS
+ .custom_conf_items = renesas_rzv2h_conf_items,
+#endif
+ .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
+ .pmc_writeb = &rzv2h_pmc_writeb,
+ .oen_read = &rzv2h_oen_read,
+ .oen_write = &rzv2h_oen_write,
+ .hw_to_bias_param = &rzv2h_hw_to_bias_param,
+ .bias_param_to_hw = &rzv2h_bias_param_to_hw,
+};
+
static struct rzg2l_pinctrl_data r9a09g057_data = {
.port_pins = rzv2h_gpio_names,
.port_pin_configs = r9a09g057_gpio_configs,
@@ -3195,6 +3364,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
.compatible = "renesas,r9a08g045-pinctrl",
.data = &r9a08g045_data,
},
+ {
+ .compatible = "renesas,r9a09g047-pinctrl",
+ .data = &r9a09g047_data,
+ },
{
.compatible = "renesas,r9a09g057-pinctrl",
.data = &r9a09g057_data,
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 63/85] pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (61 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 62/85] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 64/85] arm64: dts: renesas: r9a09g047: Add pincontrol node Tommaso Merciai
` (22 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit accabfaae0940f9427c782bfee7340ce4c15151c upstream.
The PFC_MASK value for the PFC_mx registers is currently hardcoded to
0x07, which is correct for SoCs in the RZ/G2L family, but insufficient
for RZ/V2H and RZ/G3E, where the mask value should be 0x0f. This
discrepancy causes incorrect PFC register configuration on RZ/V2H and
RZ/G3E SoCs.
On RZ/G2L, the PFC_mx bitfields are also 4 bits wide, with bit 4 marked
as reserved. The reserved bits are documented to read as zero and be
ignored when written. Updating the PFC_MASK definition from 0x07 to
0x0f ensures compatibility with both SoC families while maintaining
correct behavior on RZ/G2L.
Fixes: 9bd95ac86e70 ("pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC")
Cc: stable@vger.kernel.org
Reported-by: Hien Huynh <hien.huynh.px@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250110221045.594596-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 36ef1b558ae3..6e5715328682 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -158,7 +158,7 @@
#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
#define PM_MASK 0x03
-#define PFC_MASK 0x07
+#define PFC_MASK 0x0f
#define IEN_MASK 0x01
#define IOLH_MASK 0x03
#define SR_MASK 0x01
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 64/85] arm64: dts: renesas: r9a09g047: Add pincontrol node
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (62 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 63/85] pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 65/85] dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the end Tommaso Merciai
` (21 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 987040d4601e98e32c53837ef76aad115c4966f7 upstream.
Add pincontrol node to RZ/G3E ("R9A09G047") SoC DTSI.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241216195325.164212-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 39a7cfb3095b..15711f9b6038 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -131,6 +131,19 @@ soc: soc {
#size-cells = <2>;
ranges;
+ pinctrl: pinctrl@10410000 {
+ compatible = "renesas,r9a09g047-pinctrl";
+ reg = <0 0x10410000 0 0x10000>;
+ clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 232>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xa5>, <&cpg 0xa6>;
+ };
+
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g047-cpg";
reg = <0 0x10420000 0 0x10000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 65/85] dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the end
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (63 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 64/85] arm64: dts: renesas: r9a09g047: Add pincontrol node Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 66/85] dt-bindings: serial: renesas,scif: Validate 'interrupts' and 'interrupt-names' Tommaso Merciai
` (20 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 220fb8ff6d326d91fed8a0a44e3ac0a2f34d3f9c upstream.
In preparation for adding more validation checks move the ref for
'serial.yaml' to the end and also move reset check in 'allOf' block.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240604170513.522631-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
.../bindings/serial/renesas,scif.yaml | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 1b5b6ce6de0d..77587b0c8642 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -9,9 +9,6 @@ title: Renesas Serial Communication Interface with FIFO (SCIF)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
-allOf:
- - $ref: serial.yaml#
-
properties:
compatible:
oneOf:
@@ -159,18 +156,21 @@ required:
- clock-names
- power-domains
-if:
- properties:
- compatible:
- contains:
- enum:
- - renesas,rcar-gen2-scif
- - renesas,rcar-gen3-scif
- - renesas,rcar-gen4-scif
- - renesas,scif-r9a07g044
-then:
- required:
- - resets
+allOf:
+ - $ref: serial.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-scif
+ - renesas,rcar-gen3-scif
+ - renesas,rcar-gen4-scif
+ - renesas,scif-r9a07g044
+ then:
+ required:
+ - resets
unevaluatedProperties: false
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 66/85] dt-bindings: serial: renesas,scif: Validate 'interrupts' and 'interrupt-names'
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (64 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 65/85] dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the end Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 67/85] dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as required Tommaso Merciai
` (19 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit d057a1e3e475c6d9e24ce2e79c3f3daf367e33d8 upstream.
This commit adds support to validate the 'interrupts' and 'interrupt-names'
properties for every supported SoC. This ensures proper handling and
configuration of interrupt-related properties across supported platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240604170513.522631-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
.../bindings/serial/renesas,scif.yaml | 73 ++++++++++++++-----
1 file changed, 55 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 77587b0c8642..20132a3202fd 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -85,11 +85,6 @@ properties:
oneOf:
- items:
- description: A combined interrupt
- - items:
- - description: Error interrupt
- - description: Receive buffer full interrupt
- - description: Transmit buffer empty interrupt
- - description: Break interrupt
- items:
- description: Error interrupt
- description: Receive buffer full interrupt
@@ -97,21 +92,17 @@ properties:
- description: Break interrupt
- description: Data Ready interrupt
- description: Transmit End interrupt
+ minItems: 4
interrupt-names:
- oneOf:
- - items:
- - const: eri
- - const: rxi
- - const: txi
- - const: bri
- - items:
- - const: eri
- - const: rxi
- - const: txi
- - const: bri
- - const: dri
- - const: tei
+ minItems: 4
+ items:
+ - const: eri
+ - const: rxi
+ - const: txi
+ - const: bri
+ - const: dri
+ - const: tei
clocks:
minItems: 1
@@ -172,6 +163,52 @@ allOf:
required:
- resets
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen1-scif
+ - renesas,rcar-gen2-scif
+ - renesas,rcar-gen3-scif
+ - renesas,rcar-gen4-scif
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+
+ interrupt-names: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,scif-r7s72100
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+
+ interrupt-names:
+ maxItems: 4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,scif-r7s9210
+ - renesas,scif-r9a07g044
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+
+ interrupt-names:
+ minItems: 6
+
unevaluatedProperties: false
examples:
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 67/85] dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as required
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (65 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 66/85] dt-bindings: serial: renesas,scif: Validate 'interrupts' and 'interrupt-names' Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 68/85] dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF support Tommaso Merciai
` (18 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 034e4422ddb5ec9075d550f4668be0a3e85e6a3e upstream.
As all the SoCs having multiple interrupts have 'interrupt-names' property
in their respective DTSIs, make 'interrupt-names' property as required
so that we can validate them using dtbs_check.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240604170513.522631-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
Documentation/devicetree/bindings/serial/renesas,scif.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 20132a3202fd..252c1e6102a9 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -178,6 +178,9 @@ allOf:
maxItems: 1
interrupt-names: false
+ else:
+ required:
+ - interrupt-names
- if:
properties:
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 68/85] dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF support
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (66 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 67/85] dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as required Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 69/85] dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif Tommaso Merciai
` (17 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 964a80cfbf56f5fa88f09d704c311ed6db0a361f upstream.
Document support for the Serial Communication Interface with FIFO (SCIF)
available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
(R9A07G044) SoC, with the following differences:
- RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready
and two for Rx and Tx buffer full, all of which are edge-triggered.
- RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both
synchronous and asynchronous modes.
- There are differences in the configuration of certain registers such
as SCSMR, SCFCR, and SCSPTR between the two SoCs.
To handle these differences in the driver, a new SoC-specific compatible
string is added, ensuring proper handling of the unique features and
register configurations of the RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240604170513.522631-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
.../bindings/serial/renesas,scif.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 252c1e6102a9..7b997adec92f 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -78,6 +78,8 @@ properties:
- renesas,scif-r9a08g045 # RZ/G3S
- const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
+ - const: renesas,scif-r9a09g057 # RZ/V2H(P)
+
reg:
maxItems: 1
@@ -92,6 +94,9 @@ properties:
- description: Break interrupt
- description: Data Ready interrupt
- description: Transmit End interrupt
+ - description: Transmit End/Data Ready interrupt
+ - description: Receive buffer full interrupt (EDGE trigger)
+ - description: Transmit buffer empty interrupt (EDGE trigger)
minItems: 4
interrupt-names:
@@ -103,6 +108,9 @@ properties:
- const: bri
- const: dri
- const: tei
+ - const: tei-dri
+ - const: rxi-edge
+ - const: txi-edge
clocks:
minItems: 1
@@ -159,6 +167,7 @@ allOf:
- renesas,rcar-gen3-scif
- renesas,rcar-gen4-scif
- renesas,scif-r9a07g044
+ - renesas,scif-r9a09g057
then:
required:
- resets
@@ -208,9 +217,30 @@ allOf:
properties:
interrupts:
minItems: 6
+ maxItems: 6
interrupt-names:
minItems: 6
+ maxItems: 6
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,scif-r9a09g057
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ interrupts:
+ minItems: 9
+
+ interrupt-names:
+ minItems: 9
unevaluatedProperties: false
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 69/85] dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (67 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 68/85] dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF support Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 70/85] serial: sh-sci: describe locking requirements for invalidating RXDMA Tommaso Merciai
` (16 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit d828c6726fe5642d1c71e9edbc4799c959b471cf upstream.
Document scif bindings for the Renesas RZ/G3E (a.k.a r9a09g047) SoC.
SCIF interface in Renesas RZ/G3E is similar to the one available in
RZ/V2H.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241122124558.149827-2-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
Documentation/devicetree/bindings/serial/renesas,scif.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 7b997adec92f..8fb7fcc99720 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -80,6 +80,11 @@ properties:
- const: renesas,scif-r9a09g057 # RZ/V2H(P)
+ - items:
+ - enum:
+ - renesas,scif-r9a09g047 # RZ/G3E
+ - const: renesas,scif-r9a09g057 # RZ/V2H fallback
+
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 70/85] serial: sh-sci: describe locking requirements for invalidating RXDMA
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (68 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 69/85] dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 71/85] serial: sh-sci: Add support for RZ/V2H(P) SoC Tommaso Merciai
` (15 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Wolfram Sang <wsa+renesas@sang-engineering.com>
commit 8efc440549087de41abadf62f4bde1d827135338 upstream.
Make sure everyone knows that calling this function needs protection.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20240506114016.30498-8-wsa+renesas@sang-engineering.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/sh-sci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 69f8ac561513..7c93c9a1079b 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1264,6 +1264,7 @@ static int sci_dma_rx_find_active(struct sci_port *s)
return -1;
}
+/* Must only be called with uart_port_lock taken */
static void sci_dma_rx_chan_invalidate(struct sci_port *s)
{
unsigned int i;
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 71/85] serial: sh-sci: Add support for RZ/V2H(P) SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (69 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 70/85] serial: sh-sci: describe locking requirements for invalidating RXDMA Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 72/85] serial: sh-sci: Use plain struct copy in early_console_setup() Tommaso Merciai
` (14 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 2f50304e9efb69604040feadc13f9590be8cd391 upstream.
Add serial support for RZ/V2H(P) SoC with earlycon.
The SCIF interface in the Renesas RZ/V2H(P) is similar to that available
in the RZ/G2L (R9A07G044) SoC, with the following differences:
- RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready
and two for Rx and Tx buffer full, all of which are edge-triggered.
- RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both
synchronous and asynchronous modes.
- There are differences in the configuration of certain registers such
as SCSMR, SCFCR, and SCSPTR between the two SoCs.
To handle these differences on RZ/V2H(P) SoC SCIx_RZV2H_SCIF_REGTYPE
is added.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240604170513.522631-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/sh-sci.c | 61 ++++++++++++++++++++++++++++++++-----
include/linux/serial_sci.h | 1 +
2 files changed, 54 insertions(+), 8 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 7c93c9a1079b..ff69124e5336 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -319,6 +319,37 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
.error_clear = SCIF_ERROR_CLEAR,
},
+ /*
+ * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
+ * with below differences,
+ * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
+ * TEI-DRI, RXI-EDGE and TXI-EDGE.
+ * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
+ * - SCFCR register does not have SCFCR_MCE bit.
+ * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
+ */
+ [SCIx_RZV2H_SCIF_REGTYPE] = {
+ .regs = {
+ [SCSMR] = { 0x00, 16 },
+ [SCBRR] = { 0x02, 8 },
+ [SCSCR] = { 0x04, 16 },
+ [SCxTDR] = { 0x06, 8 },
+ [SCxSR] = { 0x08, 16 },
+ [SCxRDR] = { 0x0a, 8 },
+ [SCFCR] = { 0x0c, 16 },
+ [SCFDR] = { 0x0e, 16 },
+ [SCSPTR] = { 0x10, 16 },
+ [SCLSR] = { 0x12, 16 },
+ [SEMR] = { 0x14, 8 },
+ },
+ .fifosize = 16,
+ .overrun_reg = SCLSR,
+ .overrun_mask = SCLSR_ORER,
+ .sampling_rate_mask = SCI_SR(32),
+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
+ .error_clear = SCIF_ERROR_CLEAR,
+ },
+
/*
* Common SH-3 SCIF definitions.
*/
@@ -758,10 +789,10 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag)
/* Enable CTS# pin function */
ctrl &= ~SCPCR_CTSC;
}
- serial_port_out(port, SCPDR, data);
- serial_port_out(port, SCPCR, ctrl);
- } else if (sci_getreg(port, SCSPTR)->size) {
- u16 status = serial_port_in(port, SCSPTR);
+ sci_serial_out(port, SCPDR, data);
+ sci_serial_out(port, SCPCR, ctrl);
+ } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
+ u16 status = sci_serial_in(port, SCSPTR);
/* RTS# is always output; and active low, unless autorts */
status |= SCSPTR_RTSIO;
@@ -2132,8 +2163,9 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
if (!(mctrl & TIOCM_RTS)) {
/* Disable Auto RTS */
- serial_port_out(port, SCFCR,
- serial_port_in(port, SCFCR) & ~SCFCR_MCE);
+ if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
+ sci_serial_out(port, SCFCR,
+ sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
/* Clear RTS */
sci_set_rts(port, 0);
@@ -2145,8 +2177,9 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
}
/* Enable Auto RTS */
- serial_port_out(port, SCFCR,
- serial_port_in(port, SCFCR) | SCFCR_MCE);
+ if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
+ sci_serial_out(port, SCFCR,
+ sci_serial_in(port, SCFCR) | SCFCR_MCE);
} else {
/* Set RTS */
sci_set_rts(port, 1);
@@ -3226,6 +3259,10 @@ static const struct of_device_id of_sci_match[] = {
.compatible = "renesas,scif-r9a07g044",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
},
+ {
+ .compatible = "renesas,scif-r9a09g057",
+ .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE),
+ },
/* Family-specific types */
{
.compatible = "renesas,rcar-gen1-scif",
@@ -3558,6 +3595,13 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device,
return early_console_setup(device, PORT_SCIF);
}
+static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE;
+ return early_console_setup(device, PORT_SCIF);
+}
+
static int __init scifa_early_console_setup(struct earlycon_device *device,
const char *opt)
{
@@ -3578,6 +3622,7 @@ OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 1c89611e0e06..0f2f50b8d28e 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -37,6 +37,7 @@ enum {
SCIx_SH7705_SCIF_REGTYPE,
SCIx_HSCIF_REGTYPE,
SCIx_RZ_SCIFA_REGTYPE,
+ SCIx_RZV2H_SCIF_REGTYPE,
SCIx_NR_REGTYPES,
};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 72/85] serial: sh-sci: Use plain struct copy in early_console_setup()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (70 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 71/85] serial: sh-sci: Add support for RZ/V2H(P) SoC Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 73/85] serial: sh-sci: Check if TX data was written to device in .tx_empty() Tommaso Merciai
` (13 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit c1117a2fefbcce30cced3a180585e0adebc0fa89 upstream.
Using memcpy() prevents the compiler from doing any checking on the
types of the passed pointer parameters. Copy the structure using struct
assignment instead, to increase type-safety.
No change in generated code on all relevant architectures
(arm/arm64/riscv/sh).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/e097e5c11afe5bd4c01135779c9a40e707ef6374.1733243287.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/sh-sci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index ff69124e5336..d1140fec861b 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3566,7 +3566,7 @@ static int __init early_console_setup(struct earlycon_device *device,
device->port.serial_in = sci_serial_in;
device->port.serial_out = sci_serial_out;
device->port.type = type;
- memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
+ sci_ports[0].port = device->port;
port_cfg.type = type;
sci_ports[0].cfg = &port_cfg;
sci_ports[0].params = sci_probe_regmap(&port_cfg);
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 73/85] serial: sh-sci: Check if TX data was written to device in .tx_empty()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (71 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 72/85] serial: sh-sci: Use plain struct copy in early_console_setup() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 74/85] serial: sh-sci: Move runtime PM enable to sci_probe_single() Tommaso Merciai
` (12 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 7cc0e0a43a91052477c2921f924a37d9c3891f0c upstream.
On the Renesas RZ/G3S, when doing suspend to RAM, the uart_suspend_port()
is called. The uart_suspend_port() calls 3 times the
struct uart_port::ops::tx_empty() before shutting down the port.
According to the documentation, the struct uart_port::ops::tx_empty()
API tests whether the transmitter FIFO and shifter for the port is
empty.
The Renesas RZ/G3S SCIFA IP reports the number of data units stored in the
transmit FIFO through the FDR (FIFO Data Count Register). The data units
in the FIFOs are written in the shift register and transmitted from there.
The TEND bit in the Serial Status Register reports if the data was
transmitted from the shift register.
In the previous code, in the tx_empty() API implemented by the sh-sci
driver, it is considered that the TX is empty if the hardware reports the
TEND bit set and the number of data units in the FIFO is zero.
According to the HW manual, the TEND bit has the following meaning:
0: Transmission is in the waiting state or in progress.
1: Transmission is completed.
It has been noticed that when opening the serial device w/o using it and
then switch to a power saving mode, the tx_empty() call in the
uart_port_suspend() function fails, leading to the "Unable to drain
transmitter" message being printed on the console. This is because the
TEND=0 if nothing has been transmitted and the FIFOs are empty. As the
TEND=0 has double meaning (waiting state, in progress) we can't
determined the scenario described above.
Add a software workaround for this. This sets a variable if any data has
been sent on the serial console (when using PIO) or if the DMA callback has
been called (meaning something has been transmitted). In the tx_empty()
API the status of the DMA transaction is also checked and if it is
completed or in progress the code falls back in checking the hardware
registers instead of relying on the software variable.
Fixes: 73a19e4c0301 ("serial: sh-sci: Add DMA support.")
Cc: stable@vger.kernel.org
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20241125115856.513642-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/sh-sci.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index d1140fec861b..19fa3f8f4a6d 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -158,6 +158,7 @@ struct sci_port {
bool has_rtscts;
bool autorts;
+ bool tx_occurred;
};
#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
@@ -853,6 +854,7 @@ static void sci_transmit_chars(struct uart_port *port)
{
struct circ_buf *xmit = &port->state->xmit;
unsigned int stopped = uart_tx_stopped(port);
+ struct sci_port *s = to_sci_port(port);
unsigned short status;
unsigned short ctrl;
int count;
@@ -889,6 +891,7 @@ static void sci_transmit_chars(struct uart_port *port)
}
serial_port_out(port, SCxTDR, c);
+ s->tx_occurred = true;
port->icount.tx++;
} while (--count > 0);
@@ -1249,6 +1252,7 @@ static void sci_dma_tx_complete(void *arg)
uart_write_wakeup(port);
if (!uart_circ_empty(xmit)) {
+ s->tx_occurred = true;
s->cookie_tx = 0;
schedule_work(&s->work_tx);
} else {
@@ -1738,6 +1742,19 @@ static void sci_flush_buffer(struct uart_port *port)
s->cookie_tx = -EINVAL;
}
}
+
+static void sci_dma_check_tx_occurred(struct sci_port *s)
+{
+ struct dma_tx_state state;
+ enum dma_status status;
+
+ if (!s->chan_tx)
+ return;
+
+ status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
+ if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
+ s->tx_occurred = true;
+}
#else /* !CONFIG_SERIAL_SH_SCI_DMA */
static inline void sci_request_dma(struct uart_port *port)
{
@@ -1747,6 +1764,10 @@ static inline void sci_free_dma(struct uart_port *port)
{
}
+static void sci_dma_check_tx_occurred(struct sci_port *s)
+{
+}
+
#define sci_flush_buffer NULL
#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
@@ -2083,6 +2104,12 @@ static unsigned int sci_tx_empty(struct uart_port *port)
{
unsigned short status = serial_port_in(port, SCxSR);
unsigned short in_tx_fifo = sci_txfill(port);
+ struct sci_port *s = to_sci_port(port);
+
+ sci_dma_check_tx_occurred(s);
+
+ if (!s->tx_occurred)
+ return TIOCSER_TEMT;
return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
}
@@ -2255,6 +2282,7 @@ static int sci_startup(struct uart_port *port)
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
+ s->tx_occurred = false;
sci_request_dma(port);
ret = sci_request_irq(s);
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 74/85] serial: sh-sci: Move runtime PM enable to sci_probe_single()
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (72 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 73/85] serial: sh-sci: Check if TX data was written to device in .tx_empty() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 75/85] serial: sh-sci: Clean sci_ports[0] after at earlycon exit Tommaso Merciai
` (11 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 239f11209e5f282e16f5241b99256e25dd0614b6 upstream.
Relocate the runtime PM enable operation to sci_probe_single(). This change
prepares the codebase for upcoming fixes.
While at it, replace the existing logic with a direct call to
devm_pm_runtime_enable() and remove sci_cleanup_single(). The
devm_pm_runtime_enable() function automatically handles disabling runtime
PM during driver removal.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20250116182249.3828577-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/sh-sci.c | 24 ++++++------------------
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 19fa3f8f4a6d..9aa1db20c700 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3063,10 +3063,6 @@ static int sci_init_single(struct platform_device *dev,
ret = sci_init_clocks(sci_port, &dev->dev);
if (ret < 0)
return ret;
-
- port->dev = &dev->dev;
-
- pm_runtime_enable(&dev->dev);
}
port->type = p->type;
@@ -3096,11 +3092,6 @@ static int sci_init_single(struct platform_device *dev,
return 0;
}
-static void sci_cleanup_single(struct sci_port *port)
-{
- pm_runtime_disable(port->port.dev);
-}
-
#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
static void serial_console_putchar(struct uart_port *port, unsigned char ch)
@@ -3258,8 +3249,6 @@ static int sci_remove(struct platform_device *dev)
sci_ports_in_use &= ~BIT(port->port.line);
uart_remove_one_port(&sci_uart_driver, &port->port);
- sci_cleanup_single(port);
-
if (port->port.fifosize > 1)
device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
@@ -3425,6 +3414,11 @@ static int sci_probe_single(struct platform_device *dev,
if (ret)
return ret;
+ sciport->port.dev = &dev->dev;
+ ret = devm_pm_runtime_enable(&dev->dev);
+ if (ret)
+ return ret;
+
sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
if (IS_ERR(sciport->gpios))
return PTR_ERR(sciport->gpios);
@@ -3438,13 +3432,7 @@ static int sci_probe_single(struct platform_device *dev,
sciport->port.flags |= UPF_HARD_FLOW;
}
- ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
- if (ret) {
- sci_cleanup_single(sciport);
- return ret;
- }
-
- return 0;
+ return uart_add_one_port(&sci_uart_driver, &sciport->port);
}
static int sci_probe(struct platform_device *dev)
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 75/85] serial: sh-sci: Clean sci_ports[0] after at earlycon exit
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (73 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 74/85] serial: sh-sci: Move runtime PM enable to sci_probe_single() Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 76/85] serial: sh-sci: Increment the runtime usage counter for the earlycon device Tommaso Merciai
` (10 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 5f1017069933489add0c08659673443c9905659e upstream.
The early_console_setup() function initializes sci_ports[0].port with an
object of type struct uart_port obtained from the struct earlycon_device
passed as an argument to early_console_setup().
Later, during serial port probing, the serial port used as earlycon
(e.g., port A) might be remapped to a different position in the sci_ports[]
array, and a different serial port (e.g., port B) might be assigned to slot
0. For example:
sci_ports[0] = port B
sci_ports[X] = port A
In this scenario, the new port mapped at index zero (port B) retains the
data associated with the earlycon configuration. Consequently, after the
Linux boot process, any access to the serial port now mapped to
sci_ports[0] (port B) will block the original earlycon port (port A).
To address this, introduce an early_console_exit() function to clean up
sci_ports[0] when earlycon is exited.
To prevent the cleanup of sci_ports[0] while the serial device is still
being used by earlycon, introduce the struct sci_port::probing flag and
account for it in early_console_exit().
Fixes: 0b0cced19ab1 ("serial: sh-sci: Add CONFIG_SERIAL_EARLYCON support")
Cc: stable@vger.kernel.org
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20250116182249.3828577-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/sh-sci.c | 32 ++++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 9aa1db20c700..f8e4062d9b4c 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -167,6 +167,7 @@ static struct sci_port sci_ports[SCI_NPORTS];
static unsigned long sci_ports_in_use;
static struct uart_driver sci_uart_driver;
static bool sci_uart_earlycon;
+static bool sci_uart_earlycon_dev_probing;
static inline struct sci_port *
to_sci_port(struct uart_port *uart)
@@ -3385,7 +3386,8 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
static int sci_probe_single(struct platform_device *dev,
unsigned int index,
struct plat_sci_port *p,
- struct sci_port *sciport)
+ struct sci_port *sciport,
+ struct resource *sci_res)
{
int ret;
@@ -3432,6 +3434,14 @@ static int sci_probe_single(struct platform_device *dev,
sciport->port.flags |= UPF_HARD_FLOW;
}
+ if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
+ /*
+ * Skip cleanup the sci_port[0] in early_console_exit(), this
+ * port is the same as the earlycon one.
+ */
+ sci_uart_earlycon_dev_probing = true;
+ }
+
return uart_add_one_port(&sci_uart_driver, &sciport->port);
}
@@ -3490,7 +3500,7 @@ static int sci_probe(struct platform_device *dev)
platform_set_drvdata(dev, sp);
- ret = sci_probe_single(dev, dev_id, p, sp);
+ ret = sci_probe_single(dev, dev_id, p, sp, res);
if (ret)
return ret;
@@ -3573,6 +3583,22 @@ sh_early_platform_init_buffer("earlyprintk", &sci_driver,
#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
static struct plat_sci_port port_cfg;
+static int early_console_exit(struct console *co)
+{
+ struct sci_port *sci_port = &sci_ports[0];
+
+ /*
+ * Clean the slot used by earlycon. A new SCI device might
+ * map to this slot.
+ */
+ if (!sci_uart_earlycon_dev_probing) {
+ memset(sci_port, 0, sizeof(*sci_port));
+ sci_uart_earlycon = false;
+ }
+
+ return 0;
+}
+
static int __init early_console_setup(struct earlycon_device *device,
int type)
{
@@ -3592,6 +3618,8 @@ static int __init early_console_setup(struct earlycon_device *device,
SCSCR_RE | SCSCR_TE | port_cfg.scscr);
device->con->write = serial_console_write;
+ device->con->exit = early_console_exit;
+
return 0;
}
static int __init sci_early_console_setup(struct earlycon_device *device,
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 76/85] serial: sh-sci: Increment the runtime usage counter for the earlycon device
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (74 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 75/85] serial: sh-sci: Clean sci_ports[0] after at earlycon exit Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 77/85] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol Tommaso Merciai
` (9 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 651dee03696e1dfde6d9a7e8664bbdcd9a10ea7f upstream.
In the sh-sci driver, serial ports are mapped to the sci_ports[] array,
with earlycon mapped at index zero.
The uart_add_one_port() function eventually calls __device_attach(),
which, in turn, calls pm_request_idle(). The identified code path is as
follows:
uart_add_one_port() ->
serial_ctrl_register_port() ->
serial_core_register_port() ->
serial_core_port_device_add() ->
serial_base_port_add() ->
device_add() ->
bus_probe_device() ->
device_initial_probe() ->
__device_attach() ->
// ...
if (dev->p->dead) {
// ...
} else if (dev->driver) {
// ...
} else {
// ...
pm_request_idle(dev);
// ...
}
The earlycon device clocks are enabled by the bootloader. However, the
pm_request_idle() call in __device_attach() disables the SCI port clocks
while earlycon is still active.
The earlycon write function, serial_console_write(), calls
sci_poll_put_char() via serial_console_putchar(). If the SCI port clocks
are disabled, writing to earlycon may sometimes cause the SR.TDFE bit to
remain unset indefinitely, causing the while loop in sci_poll_put_char()
to never exit. On single-core SoCs, this can result in the system being
blocked during boot when this issue occurs.
To resolve this, increment the runtime PM usage counter for the earlycon
SCI device before registering the UART port.
Fixes: 0b0cced19ab1 ("serial: sh-sci: Add CONFIG_SERIAL_EARLYCON support")
Cc: stable@vger.kernel.org
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20250116182249.3828577-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/tty/serial/sh-sci.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index f8e4062d9b4c..3f5c319215d2 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3435,6 +3435,22 @@ static int sci_probe_single(struct platform_device *dev,
}
if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
+ /*
+ * In case:
+ * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
+ * - it now maps to an alias other than zero and
+ * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
+ * available in bootargs)
+ *
+ * we need to avoid disabling clocks and PM domains through the runtime
+ * PM APIs called in __device_attach(). For this, increment the runtime
+ * PM reference counter (the clocks and PM domains were already enabled
+ * by the bootloader). Otherwise the earlycon may access the HW when it
+ * has no clocks enabled leading to failures (infinite loop in
+ * sci_poll_put_char()).
+ */
+ pm_runtime_get_noresume(&dev->dev);
+
/*
* Skip cleanup the sci_port[0] in early_console_exit(), this
* port is the same as the earlycon one.
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 77/85] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (75 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 76/85] serial: sh-sci: Increment the runtime usage counter for the earlycon device Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 78/85] dt-bindings: i2c: renesas,riic: Document RZ/Five SoC Tommaso Merciai
` (8 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 9e269561b363038d573a69755c9eeabc9258837f upstream.
Add device node for SCIF pincontrol.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241216195325.164212-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index d4d61bd03969..c063d47e2952 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -7,6 +7,7 @@
/dts-v1/;
+#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
#include "r9a09g047e57.dtsi"
#include "rzg3e-smarc-som.dtsi"
#include "renesas-smarc2.dtsi"
@@ -16,3 +17,15 @@ / {
compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
"renesas,r9a09g047e57", "renesas,r9a09g047";
};
+
+&pinctrl {
+ scif_pins: scif {
+ pins = "SCIF_TXD", "SCIF_RXD";
+ renesas,output-impedance = <1>;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif_pins>;
+ pinctrl-names = "default";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 78/85] dt-bindings: i2c: renesas,riic: Document RZ/Five SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (76 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 77/85] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 79/85] dt-bindings: i2c: renesas,riic: Document R9A09G057 support Tommaso Merciai
` (7 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit de917701da5d5ccb31825dca850ac49399e0f289 upstream.
The RIIC block on the RZ/Five SoC is identical to one found on the RZ/G2UL
SoC. "renesas,riic-r9a07g043" compatible string will be used on the
RZ/Five SoC so to make this clear, update the comment to include RZ/Five
SoC.
No driver changes are required as generic compatible string
"renesas,riic-rz" will be used as a fallback on RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
---
Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
index d3c0d5c427ac..2291a7cd619b 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
@@ -19,7 +19,7 @@ properties:
- enum:
- renesas,riic-r7s72100 # RZ/A1H
- renesas,riic-r7s9210 # RZ/A2M
- - renesas,riic-r9a07g043 # RZ/G2UL
+ - renesas,riic-r9a07g043 # RZ/G2UL and RZ/Five
- renesas,riic-r9a07g044 # RZ/G2{L,LC}
- renesas,riic-r9a07g054 # RZ/V2L
- const: renesas,riic-rz # RZ/A or RZ/G2L
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 79/85] dt-bindings: i2c: renesas,riic: Document R9A09G057 support
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (77 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 78/85] dt-bindings: i2c: renesas,riic: Document RZ/Five SoC Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 80/85] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support Tommaso Merciai
` (6 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit c1f39c62eb09fa2e692a9377295ecbd0740c0914 upstream.
Document support for the I2C Bus Interface (RIIC) available in the
Renesas RZ/V2H(P) (R9A09G057) SoC.
The RIIC interface in the Renesas RZ/V2H(P) differs from RZ/A in a
couple of ways:
- Register offsets for the RZ/V2H(P) SoC differ from those of the
RZ/A SoC.
- RZ/V2H register access is limited to 8-bit, whereas RZ/A supports
8/16/32-bit.
- RZ/V2H has bit differences in the slave address register.
To accommodate these differences, a new compatible string
"renesas,riic-r9a09g057" is added.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
---
.../devicetree/bindings/i2c/renesas,riic.yaml | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
index 2291a7cd619b..91ecf17b7a81 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
@@ -15,14 +15,17 @@ allOf:
properties:
compatible:
- items:
- - enum:
- - renesas,riic-r7s72100 # RZ/A1H
- - renesas,riic-r7s9210 # RZ/A2M
- - renesas,riic-r9a07g043 # RZ/G2UL and RZ/Five
- - renesas,riic-r9a07g044 # RZ/G2{L,LC}
- - renesas,riic-r9a07g054 # RZ/V2L
- - const: renesas,riic-rz # RZ/A or RZ/G2L
+ oneOf:
+ - items:
+ - enum:
+ - renesas,riic-r7s72100 # RZ/A1H
+ - renesas,riic-r7s9210 # RZ/A2M
+ - renesas,riic-r9a07g043 # RZ/G2UL and RZ/Five
+ - renesas,riic-r9a07g044 # RZ/G2{L,LC}
+ - renesas,riic-r9a07g054 # RZ/V2L
+ - const: renesas,riic-rz # RZ/A or RZ/G2L
+
+ - const: renesas,riic-r9a09g057 # RZ/V2H(P)
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 80/85] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (78 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 79/85] dt-bindings: i2c: renesas,riic: Document R9A09G057 support Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 81/85] dt-bindings: i2c: renesas,riic: Document the R9A09G047 support Tommaso Merciai
` (5 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit caad8883e4202c4ba002b9b1adc62e123f739394 upstream.
Document the Renesas RZ/G3S (R9A08G045) RIIC IP. This is compatible with
the version available on Renesas RZ/V2H (R9A09G075).
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
---
Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
index 91ecf17b7a81..60578c3ad4b9 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
@@ -25,6 +25,10 @@ properties:
- renesas,riic-r9a07g054 # RZ/V2L
- const: renesas,riic-rz # RZ/A or RZ/G2L
+ - items:
+ - const: renesas,riic-r9a08g045 # RZ/G3S
+ - const: renesas,riic-r9a09g057 # RZ/V2H(P)
+
- const: renesas,riic-r9a09g057 # RZ/V2H(P)
reg:
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 81/85] dt-bindings: i2c: renesas,riic: Document the R9A09G047 support
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (79 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 80/85] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:22 ` [PATCH 6.1.y-cip 82/85] i2c: riic: Introduce helper functions for I2C read/write operations Tommaso Merciai
` (4 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit 567ef9035f820ecd3e6fcc142003f396848b31f7 upstream.
Document support for the I2C Bus Interface (RIIC) found in the Renesas
RZ/G3E (R9A09G047) SoC. This IP is compatible with Renesas RZ/V2H
(R9A09G057) RIIC IP.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20241216202436.185773-1-biju.das.jz@bp.renesas.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
---
Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
index 60578c3ad4b9..7656c6d8ded1 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
@@ -26,7 +26,9 @@ properties:
- const: renesas,riic-rz # RZ/A or RZ/G2L
- items:
- - const: renesas,riic-r9a08g045 # RZ/G3S
+ - enum:
+ - renesas,riic-r9a08g045 # RZ/G3S
+ - renesas,riic-r9a09g047 # RZ/G3E
- const: renesas,riic-r9a09g057 # RZ/V2H(P)
- const: renesas,riic-r9a09g057 # RZ/V2H(P)
@@ -89,6 +91,7 @@ if:
- renesas,riic-r9a07g043
- renesas,riic-r9a07g044
- renesas,riic-r9a07g054
+ - renesas,riic-r9a09g057
then:
required:
- resets
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 82/85] i2c: riic: Introduce helper functions for I2C read/write operations
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (80 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 81/85] dt-bindings: i2c: renesas,riic: Document the R9A09G047 support Tommaso Merciai
@ 2025-03-12 11:22 ` Tommaso Merciai
2025-03-12 11:23 ` [PATCH 6.1.y-cip 83/85] i2c: riic: Pass register offsets and chip details as OF data Tommaso Merciai
` (3 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:22 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 26c7871100f2933a2827b217320366e89cef5a4c upstream.
Introduce helper functions for performing I2C read and write operations
in the RIIC driver.
These helper functions lay the groundwork for adding support for the
RZ/V2H SoC. This is essential because the register offsets for the RZ/V2H
SoC differ from those of the RZ/A SoC. By abstracting the read and write
operations, we can seamlessly adapt the driver to support different SoC
variants without extensive modifications.
This patch is part of the preparation process for integrating support for
the RZ/V2H SoC into the RIIC driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
---
drivers/i2c/busses/i2c-riic.c | 56 +++++++++++++++++++++--------------
1 file changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 6f8ce656183c..46fd6c249c7e 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -106,9 +106,19 @@ struct riic_irq_desc {
char *name;
};
+static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset)
+{
+ writeb(val, riic->base + offset);
+}
+
+static inline u8 riic_readb(struct riic_dev *riic, u8 offset)
+{
+ return readb(riic->base + offset);
+}
+
static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
{
- writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
+ riic_writeb(riic, (riic_readb(riic, reg) & ~clear) | set, reg);
}
static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
@@ -120,7 +130,7 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
pm_runtime_get_sync(adap->dev.parent);
- if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
+ if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) {
riic->err = -EBUSY;
goto out;
}
@@ -128,7 +138,7 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
reinit_completion(&riic->msg_done);
riic->err = 0;
- writeb(0, riic->base + RIIC_ICSR2);
+ riic_writeb(riic, 0, RIIC_ICSR2);
for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
riic->bytes_left = RIIC_INIT_MSG;
@@ -136,9 +146,9 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
riic->msg = &msgs[i];
riic->is_last = (i == num - 1);
- writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
+ riic_writeb(riic, ICIER_NAKIE | ICIER_TIE, RIIC_ICIER);
- writeb(start_bit, riic->base + RIIC_ICCR2);
+ riic_writeb(riic, start_bit, RIIC_ICCR2);
time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
if (time_left == 0)
@@ -192,7 +202,7 @@ static irqreturn_t riic_tdre_isr(int irq, void *data)
* value could be moved to the shadow shift register right away. So
* this must be after updates to ICIER (where we want to disable TIE)!
*/
- writeb(val, riic->base + RIIC_ICDRT);
+ riic_writeb(riic, val, RIIC_ICDRT);
return IRQ_HANDLED;
}
@@ -201,9 +211,9 @@ static irqreturn_t riic_tend_isr(int irq, void *data)
{
struct riic_dev *riic = data;
- if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
+ if (riic_readb(riic, RIIC_ICSR2) & ICSR2_NACKF) {
/* We got a NACKIE */
- readb(riic->base + RIIC_ICDRR); /* dummy read */
+ riic_readb(riic, RIIC_ICDRR); /* dummy read */
riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
riic->err = -ENXIO;
} else if (riic->bytes_left) {
@@ -212,7 +222,7 @@ static irqreturn_t riic_tend_isr(int irq, void *data)
if (riic->is_last || riic->err) {
riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
- writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
+ riic_writeb(riic, ICCR2_SP, RIIC_ICCR2);
} else {
/* Transfer is complete, but do not send STOP */
riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
@@ -231,7 +241,7 @@ static irqreturn_t riic_rdrf_isr(int irq, void *data)
if (riic->bytes_left == RIIC_INIT_MSG) {
riic->bytes_left = riic->msg->len;
- readb(riic->base + RIIC_ICDRR); /* dummy read */
+ riic_readb(riic, RIIC_ICDRR); /* dummy read */
return IRQ_HANDLED;
}
@@ -239,7 +249,7 @@ static irqreturn_t riic_rdrf_isr(int irq, void *data)
/* STOP must come before we set ACKBT! */
if (riic->is_last) {
riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
- writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
+ riic_writeb(riic, ICCR2_SP, RIIC_ICCR2);
}
riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
@@ -249,7 +259,7 @@ static irqreturn_t riic_rdrf_isr(int irq, void *data)
}
/* Reading acks the RIE interrupt */
- *riic->buf = readb(riic->base + RIIC_ICDRR);
+ *riic->buf = riic_readb(riic, RIIC_ICDRR);
riic->buf++;
riic->bytes_left--;
@@ -261,10 +271,10 @@ static irqreturn_t riic_stop_isr(int irq, void *data)
struct riic_dev *riic = data;
/* read back registers to confirm writes have fully propagated */
- writeb(0, riic->base + RIIC_ICSR2);
- readb(riic->base + RIIC_ICSR2);
- writeb(0, riic->base + RIIC_ICIER);
- readb(riic->base + RIIC_ICIER);
+ riic_writeb(riic, 0, RIIC_ICSR2);
+ riic_readb(riic, RIIC_ICSR2);
+ riic_writeb(riic, 0, RIIC_ICIER);
+ riic_readb(riic, RIIC_ICIER);
complete(&riic->msg_done);
@@ -366,15 +376,15 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
/* Changing the order of accessing IICRST and ICE may break things! */
- writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
+ riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1);
riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
- writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
- writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
- writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
+ riic_writeb(riic, ICMR1_CKS(cks), RIIC_ICMR1);
+ riic_writeb(riic, brh | ICBR_RESERVED, RIIC_ICBRH);
+ riic_writeb(riic, brl | ICBR_RESERVED, RIIC_ICBRL);
- writeb(0, riic->base + RIIC_ICSER);
- writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
+ riic_writeb(riic, 0, RIIC_ICSER);
+ riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3);
riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
@@ -482,7 +492,7 @@ static int riic_i2c_remove(struct platform_device *pdev)
struct riic_dev *riic = platform_get_drvdata(pdev);
pm_runtime_get_sync(&pdev->dev);
- writeb(0, riic->base + RIIC_ICIER);
+ riic_writeb(riic, 0, RIIC_ICIER);
pm_runtime_put(&pdev->dev);
i2c_del_adapter(&riic->adapter);
pm_runtime_disable(&pdev->dev);
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 83/85] i2c: riic: Pass register offsets and chip details as OF data
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (81 preceding siblings ...)
2025-03-12 11:22 ` [PATCH 6.1.y-cip 82/85] i2c: riic: Introduce helper functions for I2C read/write operations Tommaso Merciai
@ 2025-03-12 11:23 ` Tommaso Merciai
2025-03-12 11:23 ` [PATCH 6.1.y-cip 84/85] i2c: riic: Add support for R9A09G057 SoC Tommaso Merciai
` (2 subsequent siblings)
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:23 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 748ee3b2a477821957adfe0ee7d1fd11d0f9a512 upstream.
With an increasing number of SoCs reusing this driver, each with slight
variations in the RIIC IP, it becomes necessary to support passing these
details as OF data. This approach simplifies the extension of the driver
for other SoCs.
This patch lays the groundwork for adding support for the Renesas RZ/V2H
SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
---
drivers/i2c/busses/i2c-riic.c | 56 +++++++++++++++++++++++++----------
1 file changed, 41 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 46fd6c249c7e..3dc806f72b78 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -47,18 +47,6 @@
#include <linux/pm_runtime.h>
#include <linux/reset.h>
-#define RIIC_ICCR1 0x00
-#define RIIC_ICCR2 0x04
-#define RIIC_ICMR1 0x08
-#define RIIC_ICMR3 0x10
-#define RIIC_ICSER 0x18
-#define RIIC_ICIER 0x1c
-#define RIIC_ICSR2 0x24
-#define RIIC_ICBRL 0x34
-#define RIIC_ICBRH 0x38
-#define RIIC_ICDRT 0x3c
-#define RIIC_ICDRR 0x40
-
#define ICCR1_ICE 0x80
#define ICCR1_IICRST 0x40
#define ICCR1_SOWP 0x10
@@ -88,6 +76,25 @@
#define RIIC_INIT_MSG -1
+enum riic_reg_list {
+ RIIC_ICCR1 = 0,
+ RIIC_ICCR2,
+ RIIC_ICMR1,
+ RIIC_ICMR3,
+ RIIC_ICSER,
+ RIIC_ICIER,
+ RIIC_ICSR2,
+ RIIC_ICBRL,
+ RIIC_ICBRH,
+ RIIC_ICDRT,
+ RIIC_ICDRR,
+ RIIC_REG_END,
+};
+
+struct riic_of_data {
+ u8 regs[RIIC_REG_END];
+};
+
struct riic_dev {
void __iomem *base;
u8 *buf;
@@ -95,6 +102,7 @@ struct riic_dev {
int bytes_left;
int err;
int is_last;
+ const struct riic_of_data *info;
struct completion msg_done;
struct i2c_adapter adapter;
struct clk *clk;
@@ -108,12 +116,12 @@ struct riic_irq_desc {
static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset)
{
- writeb(val, riic->base + offset);
+ writeb(val, riic->base + riic->info->regs[offset]);
}
static inline u8 riic_readb(struct riic_dev *riic, u8 offset)
{
- return readb(riic->base + offset);
+ return readb(riic->base + riic->info->regs[offset]);
}
static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
@@ -454,6 +462,8 @@ static int riic_i2c_probe(struct platform_device *pdev)
}
}
+ riic->info = of_device_get_match_data(&pdev->dev);
+
adap = &riic->adapter;
i2c_set_adapdata(adap, riic);
strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
@@ -500,8 +510,24 @@ static int riic_i2c_remove(struct platform_device *pdev)
return 0;
}
+static const struct riic_of_data riic_rz_a_info = {
+ .regs = {
+ [RIIC_ICCR1] = 0x00,
+ [RIIC_ICCR2] = 0x04,
+ [RIIC_ICMR1] = 0x08,
+ [RIIC_ICMR3] = 0x10,
+ [RIIC_ICSER] = 0x18,
+ [RIIC_ICIER] = 0x1c,
+ [RIIC_ICSR2] = 0x24,
+ [RIIC_ICBRL] = 0x34,
+ [RIIC_ICBRH] = 0x38,
+ [RIIC_ICDRT] = 0x3c,
+ [RIIC_ICDRR] = 0x40,
+ },
+};
+
static const struct of_device_id riic_i2c_dt_ids[] = {
- { .compatible = "renesas,riic-rz", },
+ { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
{ /* Sentinel */ },
};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 84/85] i2c: riic: Add support for R9A09G057 SoC
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (82 preceding siblings ...)
2025-03-12 11:23 ` [PATCH 6.1.y-cip 83/85] i2c: riic: Pass register offsets and chip details as OF data Tommaso Merciai
@ 2025-03-12 11:23 ` Tommaso Merciai
2025-03-12 11:23 ` [PATCH 6.1.y-cip 85/85] arm64: dts: renesas: r9a09g047: Add I2C nodes Tommaso Merciai
2025-03-13 10:51 ` [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Pavel Machek
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:23 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit a45f95d7480544fdaa9d566cb4956d0ca5d0dc33 upstream.
Extend the RIIC driver to support the RZ/V2H(P) ("R9A09G057") SoC. It
accomplishes this by appending the compatible string list and passing
the RZ/V2H-specific OF data.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
---
drivers/i2c/busses/i2c-riic.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 3dc806f72b78..9df80c4c2b5b 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -526,8 +526,25 @@ static const struct riic_of_data riic_rz_a_info = {
},
};
+static const struct riic_of_data riic_rz_v2h_info = {
+ .regs = {
+ [RIIC_ICCR1] = 0x00,
+ [RIIC_ICCR2] = 0x01,
+ [RIIC_ICMR1] = 0x02,
+ [RIIC_ICMR3] = 0x04,
+ [RIIC_ICSER] = 0x06,
+ [RIIC_ICIER] = 0x07,
+ [RIIC_ICSR2] = 0x09,
+ [RIIC_ICBRL] = 0x10,
+ [RIIC_ICBRH] = 0x11,
+ [RIIC_ICDRT] = 0x12,
+ [RIIC_ICDRR] = 0x13,
+ },
+};
+
static const struct of_device_id riic_i2c_dt_ids[] = {
{ .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
+ { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },
{ /* Sentinel */ },
};
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 6.1.y-cip 85/85] arm64: dts: renesas: r9a09g047: Add I2C nodes
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (83 preceding siblings ...)
2025-03-12 11:23 ` [PATCH 6.1.y-cip 84/85] i2c: riic: Add support for R9A09G057 SoC Tommaso Merciai
@ 2025-03-12 11:23 ` Tommaso Merciai
2025-03-13 10:51 ` [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Pavel Machek
85 siblings, 0 replies; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-12 11:23 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Biju Das <biju.das.jz@bp.renesas.com>
commit acb247afab5bc2b4462f4dfc17a9d930e1153e52 upstream.
Add I2C{0..8} nodes to RZ/G3E (R9A09G047) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241216120029.143944-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 189 +++++++++++++++++++++
1 file changed, 189 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 15711f9b6038..200e9ea89193 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -175,6 +175,195 @@ scif0: serial@11c01400 {
status = "disabled";
};
+ i2c0: i2c@14400400 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x14400400 0 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x94>;
+ resets = <&cpg 0x98>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@14400800 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x14400800 0 0x400>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x95>;
+ resets = <&cpg 0x99>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@14400c00 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x14400c00 0 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x96>;
+ resets = <&cpg 0x9a>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@14401000 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x14401000 0 0x400>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x97>;
+ resets = <&cpg 0x9b>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@14401400 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x14401400 0 0x400>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x98>;
+ resets = <&cpg 0x9c>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@14401800 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x14401800 0 0x400>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x99>;
+ resets = <&cpg 0x9d>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@14401c00 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x14401c00 0 0x400>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x9a>;
+ resets = <&cpg 0x9e>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@14402000 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x14402000 0 0x400>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x9b>;
+ resets = <&cpg 0x9f>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@11c01000 {
+ compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+ reg = <0 0x11c01000 0 0x400>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
+ clocks = <&cpg CPG_MOD 0x93>;
+ resets = <&cpg 0xa0>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@14900000 {
compatible = "arm,gic-v3";
reg = <0x0 0x14900000 0 0x20000>,
--
2.43.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-12 11:21 [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Tommaso Merciai
` (84 preceding siblings ...)
2025-03-12 11:23 ` [PATCH 6.1.y-cip 85/85] arm64: dts: renesas: r9a09g047: Add I2C nodes Tommaso Merciai
@ 2025-03-13 10:51 ` Pavel Machek
2025-03-13 11:53 ` Tommaso Merciai
85 siblings, 1 reply; 104+ messages in thread
From: Pavel Machek @ 2025-03-13 10:51 UTC (permalink / raw)
To: Tommaso Merciai
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 867 bytes --]
Hi!
> This series add support for RZ/G3E SoC to linux-6.1.y-cip kernel.
> All patches are cherry-picked from mainline kernel.
85 patches, 3000+ lines of code. So we deserve so back story here:
What is RZ/G3E? Is it new generation of something? Is it used
somewhere?
Why is it important? Why is it important for -cip?
Does this add complete support? Or just enough to boot?
Is it in 6.12? If not, what will we do with 6.12-cip?
Do you have it in lab running tests somewhere? When was it released?
What was first mainline kernel to work there?
I'm curious, and, dunno, 50 lines of explanation what this is would
not be out of place for 3000 lines of patches.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread* Re: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-13 10:51 ` [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Pavel Machek
@ 2025-03-13 11:53 ` Tommaso Merciai
2025-03-14 10:06 ` Pavel Machek
0 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-13 11:53 UTC (permalink / raw)
To: Pavel Machek
Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar, tomm.merciai
Hi Pavel,
Thanks for your comments.
On Thu, Mar 13, 2025 at 11:51:29AM +0100, Pavel Machek wrote:
> Hi!
>
> > This series add support for RZ/G3E SoC to linux-6.1.y-cip kernel.
> > All patches are cherry-picked from mainline kernel.
>
> 85 patches, 3000+ lines of code. So we deserve so back story here:
You are completely right.
Let me share with you some details:
>
> What is RZ/G3E? Is it new generation of something? Is it used
> somewhere?
The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55,
single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals.
Here the first introduction to the kernel: [1]
>
> Why is it important? Why is it important for -cip?
>
> Does this add complete support? Or just enough to boot?
At the moment mainline supports only boot. So same backported here.
Going foward will add complete support.
>
> Is it in 6.12? If not, what will we do with 6.12-cip?
We have a plan to port to 6.12, once cip releases 6.12 kernel.
>
> Do you have it in lab running tests somewhere? When was it released?
> What was first mainline kernel to work there?
We have one on the lavalab, but is not up as mainline doesn't have ethernet support.
Eventually RZ/G3E board will be added in lava lab for testing once ethernet support added to mainline.
Does it answers all your questions?
>
> I'm curious, and, dunno, 50 lines of explanation what this is would
> not be out of place for 3000 lines of patches.
>
> Best regards,
> Pavel
>
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[1] https://patchwork.kernel.org/project/linux-clk/cover/20241122124558.149827-1-biju.das.jz@bp.renesas.com/
Thanks & Regards,
Tommaso
^ permalink raw reply [flat|nested] 104+ messages in thread
* Re: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-13 11:53 ` Tommaso Merciai
@ 2025-03-14 10:06 ` Pavel Machek
2025-03-14 11:30 ` Tommaso Merciai
0 siblings, 1 reply; 104+ messages in thread
From: Pavel Machek @ 2025-03-14 10:06 UTC (permalink / raw)
To: Tommaso Merciai
Cc: Pavel Machek, cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar,
tomm.merciai
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Hi!
> > What is RZ/G3E? Is it new generation of something? Is it used
> > somewhere?
>
> The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55,
> single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals.
>
> Here the first introduction to the kernel: [1]
Ok, thanks for pointer, that is useful.
What is relation between RZ/G3E and rzg2l? Because early patches seem
to be for rzg2l support, not RZ/G3E. Splitting those preparations up
would be good.
> > Why is it important? Why is it important for -cip?
> >
> > Does this add complete support? Or just enough to boot?
>
> At the moment mainline supports only boot. So same backported here.
> Going foward will add complete support.
Ok, 85 patches in the series is really a bit hard to work with. It
seems dts is merged quite early in the series, so that should be good
place to split stuff. Could we get smaller series (perhaps 15
patches?) with only stuff that's already in 6.12?
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 104+ messages in thread
* Re: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-14 10:06 ` Pavel Machek
@ 2025-03-14 11:30 ` Tommaso Merciai
2025-03-14 11:39 ` Tommaso Merciai
0 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-14 11:30 UTC (permalink / raw)
To: Pavel Machek
Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar, tomm.merciai
Hi Pavel,
On Fri, Mar 14, 2025 at 11:06:33AM +0100, Pavel Machek wrote:
> Hi!
>
> > > What is RZ/G3E? Is it new generation of something? Is it used
> > > somewhere?
> >
> > The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55,
> > single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals.
> >
> > Here the first introduction to the kernel: [1]
>
> Ok, thanks for pointer, that is useful.
>
> What is relation between RZ/G3E and rzg2l? Because early patches seem
> to be for rzg2l support, not RZ/G3E. Splitting those preparations up
> would be good.
Thanks for your comment.
RZ/G3E and RZ/G2L SoC have some similar IP's.
For that we need some patches for RZ/G2L in preparation to support
RZ/G3E.
>
> > > Why is it important? Why is it important for -cip?
> > >
> > > Does this add complete support? Or just enough to boot?
> >
> > At the moment mainline supports only boot. So same backported here.
> > Going foward will add complete support.
>
> Ok, 85 patches in the series is really a bit hard to work with. It
> seems dts is merged quite early in the series, so that should be good
> place to split stuff. Could we get smaller series (perhaps 15
> patches?) with only stuff that's already in 6.12?
Fully agree.
I will split backporting in smaller patchset as you suggested.
Thanks.
>
> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Regards,
Tommaso
^ permalink raw reply [flat|nested] 104+ messages in thread
* Re: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-14 11:30 ` Tommaso Merciai
@ 2025-03-14 11:39 ` Tommaso Merciai
2025-03-16 19:13 ` Pavel Machek
0 siblings, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-14 11:39 UTC (permalink / raw)
To: Pavel Machek
Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar, tomm.merciai
On Fri, Mar 14, 2025 at 12:30:06PM +0100, Tommaso Merciai wrote:
> Hi Pavel,
>
> On Fri, Mar 14, 2025 at 11:06:33AM +0100, Pavel Machek wrote:
> > Hi!
> >
> > > > What is RZ/G3E? Is it new generation of something? Is it used
> > > > somewhere?
> > >
> > > The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55,
> > > single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals.
> > >
> > > Here the first introduction to the kernel: [1]
> >
> > Ok, thanks for pointer, that is useful.
> >
> > What is relation between RZ/G3E and rzg2l? Because early patches seem
> > to be for rzg2l support, not RZ/G3E. Splitting those preparations up
> > would be good.
>
> Thanks for your comment.
>
> RZ/G3E and RZ/G2L SoC have some similar IP's.
Sorry, to be more precise:
RZ/G3E, RZ/V2H and RZ/G2L SoC have some similar IP's.
> For that we need some patches for RZ/G2L in preparation to support
> RZ/G3E.
>
> >
> > > > Why is it important? Why is it important for -cip?
> > > >
> > > > Does this add complete support? Or just enough to boot?
> > >
> > > At the moment mainline supports only boot. So same backported here.
> > > Going foward will add complete support.
> >
> > Ok, 85 patches in the series is really a bit hard to work with. It
> > seems dts is merged quite early in the series, so that should be good
> > place to split stuff. Could we get smaller series (perhaps 15
> > patches?) with only stuff that's already in 6.12?
>
> Fully agree.
> I will split backporting in smaller patchset as you suggested.
> Thanks.
>
> >
> > Best regards,
> > Pavel
> > --
> > DENX Software Engineering GmbH, Managing Director: Erika Unter
> > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>
> Regards,
> Tommaso
Thanks & Regards,
Tommaso
^ permalink raw reply [flat|nested] 104+ messages in thread
* Re: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-14 11:39 ` Tommaso Merciai
@ 2025-03-16 19:13 ` Pavel Machek
2025-03-17 8:45 ` [cip-dev] " Chris Paterson
2025-03-17 14:32 ` Tommaso Merciai
0 siblings, 2 replies; 104+ messages in thread
From: Pavel Machek @ 2025-03-16 19:13 UTC (permalink / raw)
To: Tommaso Merciai
Cc: Pavel Machek, cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 846 bytes --]
Hi!
> > > What is relation between RZ/G3E and rzg2l? Because early patches seem
> > > to be for rzg2l support, not RZ/G3E. Splitting those preparations up
> > > would be good.
> >
> > Thanks for your comment.
> >
> > RZ/G3E and RZ/G2L SoC have some similar IP's.
>
> Sorry, to be more precise:
> RZ/G3E, RZ/V2H and RZ/G2L SoC have some similar IP's.
Thank you. One day I'd like to understand that naming scheme and how
different SoCs are related to each other.
> > Fully agree.
> > I will split backporting in smaller patchset as you suggested.
> > Thanks.
Thank you. I went through the series up-to 23 or so, and it looked
mostly good.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 104+ messages in thread
* RE: [cip-dev] [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-16 19:13 ` Pavel Machek
@ 2025-03-17 8:45 ` Chris Paterson
2025-03-17 14:32 ` Tommaso Merciai
1 sibling, 0 replies; 104+ messages in thread
From: Chris Paterson @ 2025-03-17 8:45 UTC (permalink / raw)
To: cip-dev@lists.cip-project.org, Tommaso Merciai
Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das, Prabhakar Mahadev Lad,
Tommaso Merciai
Hello Pavel,
As always, thank you for your reviews.
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
> Behalf Of Pavel Machek via lists.cip-project.org
> Sent: 16 March 2025 19:14
>
> Hi!
>
> > > > What is relation between RZ/G3E and rzg2l? Because early patches
> seem
> > > > to be for rzg2l support, not RZ/G3E. Splitting those preparations up
> > > > would be good.
> > >
> > > Thanks for your comment.
> > >
> > > RZ/G3E and RZ/G2L SoC have some similar IP's.
> >
> > Sorry, to be more precise:
> > RZ/G3E, RZ/V2H and RZ/G2L SoC have some similar IP's.
>
> Thank you. One day I'd like to understand that naming scheme and how
> different SoCs are related to each other.
This guide can help from a top level:
https://www.renesas.com/ja/document/gde/rz-family-product-part-number-guide
(note: not all the latest SoCs are in this guide yet)
However, there is no definitive guide as to which SoCs share the same IP blocks.
A lot is shared, a lot is not shared.
We do our best to reuse drivers for the same/similar IP as much as we can :)
Kind regards, Chris
>
> > > Fully agree.
> > > I will split backporting in smaller patchset as you suggested.
> > > Thanks.
>
> Thank you. I went through the series up-to 23 or so, and it looked
> mostly good.
>
> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 104+ messages in thread
* Re: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-16 19:13 ` Pavel Machek
2025-03-17 8:45 ` [cip-dev] " Chris Paterson
@ 2025-03-17 14:32 ` Tommaso Merciai
2025-03-18 19:48 ` Pavel Machek
1 sibling, 1 reply; 104+ messages in thread
From: Tommaso Merciai @ 2025-03-17 14:32 UTC (permalink / raw)
To: Pavel Machek
Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar, tomm.merciai
Hi Pavel,
Thanks for your review.
On Sun, Mar 16, 2025 at 08:13:50PM +0100, Pavel Machek wrote:
> Hi!
>
> > > > What is relation between RZ/G3E and rzg2l? Because early patches seem
> > > > to be for rzg2l support, not RZ/G3E. Splitting those preparations up
> > > > would be good.
> > >
> > > Thanks for your comment.
> > >
> > > RZ/G3E and RZ/G2L SoC have some similar IP's.
> >
> > Sorry, to be more precise:
> > RZ/G3E, RZ/V2H and RZ/G2L SoC have some similar IP's.
>
> Thank you. One day I'd like to understand that naming scheme and how
> different SoCs are related to each other.
>
> > > Fully agree.
> > > I will split backporting in smaller patchset as you suggested.
> > > Thanks.
>
> Thank you. I went through the series up-to 23 or so, and it looked
> mostly good.
Thanks for your feedback.
I've done some investigation/testing here.
I'm going to split the big series into the following for now:
- first series:
serial: sh-sci backpoting patches 65/85 to 76/85
(required for a minimal boot)
- second series:
clock + minimal boot support patches 1/85 to 22/85
(as you suggested)
What do you think? Thanks in advance.
Later:
- pinctrl
- i2c
>
> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Regards,
Tommaso
^ permalink raw reply [flat|nested] 104+ messages in thread
* Re: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
2025-03-17 14:32 ` Tommaso Merciai
@ 2025-03-18 19:48 ` Pavel Machek
0 siblings, 0 replies; 104+ messages in thread
From: Pavel Machek @ 2025-03-18 19:48 UTC (permalink / raw)
To: Tommaso Merciai
Cc: Pavel Machek, cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar,
tomm.merciai
[-- Attachment #1: Type: text/plain, Size: 1416 bytes --]
Hi!
> > > > > What is relation between RZ/G3E and rzg2l? Because early patches seem
> > > > > to be for rzg2l support, not RZ/G3E. Splitting those preparations up
> > > > > would be good.
> > > >
> > > > Thanks for your comment.
> > > >
> > > > RZ/G3E and RZ/G2L SoC have some similar IP's.
> > >
> > > Sorry, to be more precise:
> > > RZ/G3E, RZ/V2H and RZ/G2L SoC have some similar IP's.
> >
> > Thank you. One day I'd like to understand that naming scheme and how
> > different SoCs are related to each other.
> >
> > > > Fully agree.
> > > > I will split backporting in smaller patchset as you suggested.
> > > > Thanks.
> >
> > Thank you. I went through the series up-to 23 or so, and it looked
> > mostly good.
>
> Thanks for your feedback.
>
> I've done some investigation/testing here.
> I'm going to split the big series into the following for now:
>
> - first series:
> serial: sh-sci backpoting patches 65/85 to 76/85
> (required for a minimal boot)
>
> - second series:
> clock + minimal boot support patches 1/85 to 22/85
> (as you suggested)
>
> What do you think? Thanks in advance.
>
> Later:
>
> - pinctrl
> - i2c
That sounds like a good plan.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 104+ messages in thread