[PATCH 5.10.y-cip 10/23] arm64: dts: renesas: r9a09g011: Add watchdog node

Biju Das
2023-05-19T08:21:37Z

From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

commit 753a4ae153788225a30b0ee9dd18da83f1d94447 upstream.

The r9a09g011 (a.k.a. RZ/V2M) comes with two watchdog IPs,
but Linux is only allowed one.

Add a node for the watchdog allowed to Linux to the SoC
specific dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20221103223956.50575-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 460d58a0c304..e037e08026b6 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -145,6 +145,19 @@ uart0: serial@a4040000 {
status = "disabled";
};

+ wdt0: watchdog@a4050000 {
+ compatible = "renesas,r9a09g011-wdt",
+ "renesas,rzv2m-wdt";
+ reg = <0 0xa4050000 0 0x80>;
+ clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
+ <&cpg CPG_MOD R9A09G011_WDT0_CLK>;
+ clock-names = "pclk", "oscclk";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cpg R9A09G011_WDT0_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl@b6250000 {
compatible = "renesas,r9a09g011-pinctrl";
reg = <0 0xb6250000 0 0x800>;
--
2.25.1