* [PATCH 6.1.y-cip 01/15] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 02/15] arm64: dts: renesas: rzg2ul-smarc: Move spi1 pinmux to carrier board DTSI Biju Das
` (14 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 38c042b59af0248a8b13f01b1a09d890997c9f6e upstream.
For half duplex channels we dont have separate interrupts for Tx and Rx
instead we have single interrupt Rt (where the signal for Rx and Tx is
muxed). To handle such a case install a handler in case we have a dma_rt
interrupt specified in the DT for the PIO mode.
Note, for backward compatibility we check if the Rx and Tx interrupts
are present first instead of checking Rt interrupt.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230217185225.43310-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
sound/soc/sh/rz-ssi.c | 63 ++++++++++++++++++++++++++++++-------------
1 file changed, 44 insertions(+), 19 deletions(-)
diff --git a/sound/soc/sh/rz-ssi.c b/sound/soc/sh/rz-ssi.c
index 5d6bae33ae34..d502aa55c5a8 100644
--- a/sound/soc/sh/rz-ssi.c
+++ b/sound/soc/sh/rz-ssi.c
@@ -109,6 +109,7 @@ struct rz_ssi_priv {
int irq_int;
int irq_tx;
int irq_rx;
+ int irq_rt;
spinlock_t lock;
@@ -565,6 +566,17 @@ static irqreturn_t rz_ssi_interrupt(int irq, void *data)
rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
}
+ if (irq == ssi->irq_rt) {
+ struct snd_pcm_substream *substream = strm->substream;
+
+ if (rz_ssi_stream_is_play(ssi, substream)) {
+ strm->transfer(ssi, &ssi->playback);
+ } else {
+ strm->transfer(ssi, &ssi->capture);
+ rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
+ }
+ }
+
return IRQ_HANDLED;
}
@@ -993,26 +1005,39 @@ static int rz_ssi_probe(struct platform_device *pdev)
if (!rz_ssi_is_dma_enabled(ssi)) {
/* Tx and Rx interrupts (pio only) */
ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
- if (ssi->irq_tx < 0)
- return ssi->irq_tx;
-
- ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
- &rz_ssi_interrupt, 0,
- dev_name(&pdev->dev), ssi);
- if (ret < 0)
- return dev_err_probe(&pdev->dev, ret,
- "irq request error (dma_tx)\n");
-
ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
- if (ssi->irq_rx < 0)
- return ssi->irq_rx;
-
- ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
- &rz_ssi_interrupt, 0,
- dev_name(&pdev->dev), ssi);
- if (ret < 0)
- return dev_err_probe(&pdev->dev, ret,
- "irq request error (dma_rx)\n");
+ if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) {
+ ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt");
+ if (ssi->irq_rt < 0)
+ return ssi->irq_rt;
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_rt,
+ &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_tx)\n");
+ } else {
+ if (ssi->irq_tx < 0)
+ return ssi->irq_tx;
+
+ if (ssi->irq_rx < 0)
+ return ssi->irq_rx;
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_tx,
+ &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_tx)\n");
+
+ ret = devm_request_irq(&pdev->dev, ssi->irq_rx,
+ &rz_ssi_interrupt, 0,
+ dev_name(&pdev->dev), ssi);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "irq request error (dma_rx)\n");
+ }
}
ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 02/15] arm64: dts: renesas: rzg2ul-smarc: Move spi1 pinmux to carrier board DTSI
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 01/15] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 03/15] clk: renesas: r9a07g044: Drop WDT2 clock and reset entry Biju Das
` (13 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit affab0af979a331adae2d1f7f86afe8ecf81b5fc upstream.
spi1 is available on the RZ/G2UL SMARC EVK carrier board (PMOD0), hence
moving the spi1 pinmux from SoM to carrier board. This is to keep
consistency with the other SMARC EVKs.
Also while moving the pinmux rename rspi1 to spi1 to be consistent with
other SMARC EVK DTSIs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220921082221.10599-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 7 +++++++
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 7 -------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
index bd8bc858c28c..58923dc83faa 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
@@ -99,6 +99,13 @@ sound_clk_pins: sound_clk {
input-enable;
};
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
+ <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
+ <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
+ <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
+ };
+
ssi1_pins: ssi1 {
pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* BCK */
<RZG2L_PORT_PINMUX(3, 1, 2)>, /* RCK */
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 2a0feb53f0dc..931efc07d6fb 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -221,13 +221,6 @@ sd0_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
-
- spi1_pins: rspi1 {
- pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
- <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
- <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
- <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
- };
};
#if (SW_SW0_DEV_SEL)
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 03/15] clk: renesas: r9a07g044: Drop WDT2 clock and reset entry
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 01/15] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 02/15] arm64: dts: renesas: rzg2ul-smarc: Move spi1 pinmux to carrier board DTSI Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 04/15] clk: renesas: r9a07g043: " Biju Das
` (12 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 772563aef2b46da86120d4c0d6865149e957b02d upstream.
WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if
used from CA55 CPU would result in an unexpected behaviour. Hence drop
WDT2 clock and reset entries.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009231013.14791-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 12b1a83625cb..f5550fccb029 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
};
static const struct {
- struct rzg2l_mod_clk common[77];
+ struct rzg2l_mod_clk common[75];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
@@ -224,10 +224,6 @@ static const struct {
0x548, 2),
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
0x548, 3),
- DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0,
- 0x548, 4),
- DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK,
- 0x548, 5),
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
0x550, 0),
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
@@ -366,7 +362,6 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
- DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 04/15] clk: renesas: r9a07g043: Drop WDT2 clock and reset entry
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (2 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 03/15] clk: renesas: r9a07g044: Drop WDT2 clock and reset entry Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 05/15] arm64: dts: renesas: rzg2l: Drop WDT2 nodes Biju Das
` (11 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 7265521e950ae4c0f475752ba6789688fbabfa44 upstream.
WDT CH2 is specifically to check the operation of Cortex-M33 CPU and if
used from CA55 CPU would result in an unexpected behaviour. Hence drop
WDT2 clock and reset entries.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009231253.15592-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 37475465100d..99f72bf590fa 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -158,10 +158,6 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x548, 0),
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
0x548, 1),
- DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
- 0x548, 4),
- DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
- 0x548, 5),
DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
0x550, 0),
DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
@@ -269,7 +265,6 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
- DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 05/15] arm64: dts: renesas: rzg2l: Drop WDT2 nodes
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (3 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 04/15] clk: renesas: r9a07g043: " Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 06/15] arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes Biju Das
` (10 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit c02734d6e4ceaf4cec3e5ec0aa17ca66e9bc280d upstream.
On members of the RZ/G2L family, WDT CH2 is specifically meant to check
the operation of the Cortex-M33 CPU. Using it from a Cortex-A55 CPU
would result in unexpected behaviour. Hence drop all WDT2 nodes and
their references from the affected SoC and SoM DTSI files.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 15 ---------------
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 15 ---------------
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 15 ---------------
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 5 -----
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 5 -----
5 files changed, 55 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 2c5444cdbd9c..ca937f88406c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -816,21 +816,6 @@ wdt0: watchdog@12800800 {
status = "disabled";
};
- wdt2: watchdog@12800400 {
- compatible = "renesas,r9a07g043-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800400 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
- <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G043_WDT2_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
ostm0: timer@12801000 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 7a62e33eb821..2a613b514d02 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -1066,21 +1066,6 @@ wdt1: watchdog@12800c00 {
status = "disabled";
};
- wdt2: watchdog@12800400 {
- compatible = "renesas,r9a07g044-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800400 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
- <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G044_WDT2_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
ostm0: timer@12801000 {
compatible = "renesas,r9a07g044-ostm",
"renesas,ostm";
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 3211a39e49a9..0f485ccf7fa0 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -1072,21 +1072,6 @@ wdt1: watchdog@12800c00 {
status = "disabled";
};
- wdt2: watchdog@12800400 {
- compatible = "renesas,r9a07g054-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800400 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
- <&cpg CPG_MOD R9A07G054_WDT2_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G054_WDT2_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
ostm0: timer@12801000 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index c4faff092380..fbbb4f03440b 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -351,8 +351,3 @@ &wdt1 {
status = "okay";
timeout-sec = <60>;
};
-
-&wdt2 {
- status = "okay";
- timeout-sec = <60>;
-};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 78e6e2376b01..8a0d56872de7 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -276,8 +276,3 @@ &wdt1 {
status = "okay";
timeout-sec = <60>;
};
-
-&wdt2 {
- status = "okay";
- timeout-sec = <60>;
-};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 06/15] arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (4 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 05/15] arm64: dts: renesas: rzg2l: Drop WDT2 nodes Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 07/15] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Biju Das
` (9 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit eafbed2a4556f90792338630ab6ddf7b2e492e8d upstream.
This fixes the below dtbs_check warning:
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed:
[[2]] is not of type 'object'
From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed:
[[2]] is not of type 'object'
From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed:
[[2]] is not of type 'object'
From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
Drop #address-cells properties from pinctrl nodes as they have no
addressed child nodes.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221107172953.63218-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/r/20221107172953.63218-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 -
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 2a613b514d02..67677a4bd4c7 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -714,7 +714,6 @@ pinctrl: pinctrl@11030000 {
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
- #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-parent = <&irqc>;
interrupt-controller;
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 0f485ccf7fa0..60ad8b05948f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -720,7 +720,6 @@ pinctrl: pinctrl@11030000 {
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
- #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-parent = <&irqc>;
interrupt-controller;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 07/15] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (5 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 06/15] arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 08/15] pinctrl: renesas: Add missing header(s) Biju Das
` (8 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit b9a0be2054964026aa58966ce9724b672f210835 upstream.
Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that
r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC).
Below are the changes due to which SoC specific parts are moved to
r9a07g043u.dtsi:
- RZ/G2UL has Cortex-A55 (ARM64) whereas RZ/Five has AX45MP (RISC-V),
- RZ/G2UL has GICv3 as interrupt controller whereas RZ/Five has PLIC,
- RZ/G2UL has interrupts for SYSC block whereas interrupts are missing
for SYSC block on RZ/Five,
- RZ/G2UL has armv8-timer whereas RZ/Five has riscv-timer,
- RZ/G2UL has PSCI whereas RZ/Five have OpenSBI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 54 +------------------
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 60 +++++++++++++++++++++
2 files changed, 61 insertions(+), 53 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index ca937f88406c..5f534db54d1c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2UL SoC
+ * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
@@ -68,36 +68,8 @@ opp-1000000000 {
};
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a55";
- reg = <0>;
- device_type = "cpu";
- #cooling-cells = <2>;
- next-level-cache = <&L3_CA55>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- L3_CA55: cache-controller-0 {
- compatible = "cache";
- cache-unified;
- cache-size = <0x40000>;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
soc: soc {
compatible = "simple-bus";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -545,12 +517,6 @@ cpg: clock-controller@11010000 {
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
- interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
- <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
- <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
- <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "lpm_int", "ca55stbydone_int",
- "cm33stbyr_int", "ca55_deny";
status = "disabled";
};
@@ -605,16 +571,6 @@ dmac: dma-controller@11820000 {
dma-channels = <16>;
};
- gic: interrupt-controller@11900000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0x11900000 0 0x40000>,
- <0x0 0x11940000 0 0x60000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
- };
-
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
@@ -880,12 +836,4 @@ target: trip-point {
};
};
};
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 96f935bc2d4d..b8bf06b51235 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -10,3 +10,63 @@
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
#include "r9a07g043.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ #cooling-cells = <2>;
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+&soc {
+ interrupt-parent = <&gic>;
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&sysc {
+ interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 08/15] pinctrl: renesas: Add missing header(s)
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (6 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 07/15] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 09/15] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Biju Das
` (7 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
commit 2fb98ab403720f2ddd731cdebdf706c5be3b3c24 upstream.
Do not imply that some of the generic headers may be always included.
Instead, include explicitly what we are direct user of.
While at it, sort headers alphabetically.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 7 +++++--
drivers/pinctrl/renesas/pinctrl-rzn1.c | 8 ++++++--
drivers/pinctrl/renesas/pinctrl-rzv2m.c | 4 +++-
drivers/pinctrl/renesas/pinctrl.c | 8 +++++---
4 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 054073380c15..2399be9314f1 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -8,16 +8,19 @@
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
-#include <linux/io.h>
#include <linux/interrupt.h>
+#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+
+#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
-#include <linux/spinlock.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c
index 849d091205d4..9158c1757492 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzn1.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -7,16 +7,20 @@
*/
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
+
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
+
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c
index 35f382b055e8..357eaab00866 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c
@@ -15,11 +15,13 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/spinlock.h>
+
+#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
-#include <linux/spinlock.h>
#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index b438d24c13b5..b74147800319 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -12,14 +12,16 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
#include "core.h"
#include "../core.h"
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 09/15] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (7 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 08/15] pinctrl: renesas: Add missing header(s) Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 10/15] arm64: dts: renesas: r9a07g043u: Add IRQC node Biju Das
` (6 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 2d4a628cade2fe9cf7aa5629cffe768afe0e7ae1 upstream.
Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each
supported SoC.
While at it, for readability set n_port_pins based on the GPIO pin configs
and not on GPIO names for r9a07g044_data as done for r9a07g043_data.
Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230102221815.273719-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 2399be9314f1..38be83fef3e9 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -1480,6 +1480,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
struct rzg2l_pinctrl *pctrl;
int ret;
+ BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzg2l_gpio_names));
+
+ BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
+ ARRAY_SIZE(rzg2l_gpio_names));
+
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
@@ -1543,7 +1549,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pin_configs = rzg2l_gpio_configs,
.n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common,
- .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
+ .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 10/15] arm64: dts: renesas: r9a07g043u: Add IRQC node
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (8 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 09/15] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 11/15] arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts Biju Das
` (5 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 48ab6eddd8bbcf7e9c8ae27bf42d0b52a777aaba upstream.
Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102221815.273719-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 68 +++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index b8bf06b51235..a6e777aee02e 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -51,6 +51,74 @@ timer {
&soc {
interrupt-parent = <&gic>;
+ irqc: interrupt-controller@110a0000 {
+ compatible = "renesas,r9a07g043u-irqc",
+ "renesas,rzg2l-irqc";
+ reg = <0 0x110a0000 0 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err";
+ clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G043_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_IA55_RESETN>;
+ };
+
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 11/15] arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (9 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 10/15] arm64: dts: renesas: r9a07g043u: Add IRQC node Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 12/15] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Biju Das
` (4 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 85169df721078bf90fb0fc3bf15e4743fea45b2d upstream.
Add required properties in pinctrl node to handle GPIO interrupts.
Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent
is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver
continues without waiting for IRQC to probe.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102221815.273719-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 5f534db54d1c..27c35a657b15 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -526,6 +526,8 @@ pinctrl: pinctrl@11030000 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 152>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A07G043_GPIO_RSTN>,
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index a6e777aee02e..ebaaf82edeca 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -48,6 +48,10 @@ timer {
};
};
+&pinctrl {
+ interrupt-parent = <&irqc>;
+};
+
&soc {
interrupt-parent = <&gic>;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 12/15] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (10 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 11/15] arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 13/15] arm64: dts: renesas: rzg2l: Add missing cache-level properties Biju Das
` (3 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit f4673e52dbab9d890d236ed75264653bcd43bac1 upstream.
The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
ETH1 respectively.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102221815.273719-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 931efc07d6fb..49ecd33aeeb8 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
@@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -104,6 +107,8 @@ phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupt-parent = <&irqc>;
+ interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -151,7 +156,8 @@ eth0_pins: eth0 {
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
- <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
};
eth1_pins: eth1 {
@@ -169,7 +175,8 @@ eth1_pins: eth1 {
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
- <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
};
sdhi0_emmc_pins: sd0emmc {
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 13/15] arm64: dts: renesas: rzg2l: Add missing cache-level properties
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (11 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 12/15] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 14/15] arm64: dts: renesas: r9a07g043u: Add Cortex-A55 PMU node Biju Das
` (2 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Pierre Gondois <pierre.gondois@arm.com>
commit 4662d6e8c9b0035581ffc31cab80ea5963bd9f24 upstream.
The DeviceTree Specification v0.3 specifies that the cache node
'cache-level' property is 'required'. Cf. s3.8 Multi-level and Shared
Cache Nodes.
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-19-pierre.gondois@arm.com
[geert: Update description]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index ebaaf82edeca..9d854706ada5 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -31,6 +31,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 67677a4bd4c7..ee6c384c6933 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -109,6 +109,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 60ad8b05948f..3efd63b0981a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -109,6 +109,7 @@ L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 14/15] arm64: dts: renesas: r9a07g043u: Add Cortex-A55 PMU node
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (12 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 13/15] arm64: dts: renesas: rzg2l: Add missing cache-level properties Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-21 14:37 ` [PATCH 6.1.y-cip 15/15] arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems Biju Das
2023-08-22 8:44 ` [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Pavel Machek
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 805ed6d67b7b39b07fb65d4a76c986a1e49262cf upstream.
Enable the performance monitor unit for the Cortex-A55 core on the
RZ/G2UL (r9a07g043u) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206001133.28776-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 9d854706ada5..1c9d3193e4ff 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -35,6 +35,11 @@ L3_CA55: cache-controller-0 {
};
};
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6.1.y-cip 15/15] arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (13 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 14/15] arm64: dts: renesas: r9a07g043u: Add Cortex-A55 PMU node Biju Das
@ 2023-08-21 14:37 ` Biju Das
2023-08-22 8:44 ` [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Pavel Machek
15 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2023-08-21 14:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Claudiu Beznea
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 8b6a006c914aac1702ef85b4ea42ff566b157c85 upstream.
The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them from GICv3 systems.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[biju: Removed changes for r8a779{a0,f0,g0} ]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 8 ++++----
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++----
arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 7 -------
arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 7 -------
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 8 ++++----
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 7 -------
6 files changed, 12 insertions(+), 33 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 1c9d3193e4ff..2ab231572d95 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -47,10 +47,10 @@ psci {
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index ee6c384c6933..7ee872d4cddd 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -1133,9 +1133,9 @@ target: trip-point {
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
index 1d57df706939..56a979e82c4f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
@@ -15,13 +15,6 @@ cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
-
- timer {
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
};
&soc {
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
index 9d89d4590358..9cf27ca9f1d2 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
@@ -15,11 +15,4 @@ cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
-
- timer {
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 3efd63b0981a..0795346ef709 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -1139,9 +1139,9 @@ target: trip-point {
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
index c448cc6634c1..d85a6ac0f024 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
@@ -15,11 +15,4 @@ cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
};
-
- timer {
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements
2023-08-21 14:37 [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Biju Das
` (14 preceding siblings ...)
2023-08-21 14:37 ` [PATCH 6.1.y-cip 15/15] arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems Biju Das
@ 2023-08-22 8:44 ` Pavel Machek
2023-08-23 8:43 ` Pavel Machek
15 siblings, 1 reply; 18+ messages in thread
From: Pavel Machek @ 2023-08-22 8:44 UTC (permalink / raw)
To: Biju Das; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Claudiu Beznea
[-- Attachment #1: Type: text/plain, Size: 428 bytes --]
Hi!
> This patch series add improvements to RZ/G2{L,UL} SMARC EVKs.
> All the patches are cherry-picked from mainline.
Thanks for patches. They look ok to me, and I can apply them provided
they pass testing and there are no other comments.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements
2023-08-22 8:44 ` [PATCH 6.1.y-cip 00/15] RZ/G2{L,UL} Improvements Pavel Machek
@ 2023-08-23 8:43 ` Pavel Machek
0 siblings, 0 replies; 18+ messages in thread
From: Pavel Machek @ 2023-08-23 8:43 UTC (permalink / raw)
To: Pavel Machek; +Cc: Biju Das, cip-dev, Nobuhiro Iwamatsu, Claudiu Beznea
[-- Attachment #1: Type: text/plain, Size: 461 bytes --]
Hi!
> > This patch series add improvements to RZ/G2{L,UL} SMARC EVKs.
> > All the patches are cherry-picked from mainline.
>
> Thanks for patches. They look ok to me, and I can apply them provided
> they pass testing and there are no other comments.
Thank you, applied.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 18+ messages in thread