Re: [PATCH 6.1.y-cip 03/20] drm: rcar-du: Add RZ/G2L DSI driver

[Pavel Machek <pavel@denx.de>]

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Hi!

> commit 7a043f978ed1433bddb088a732e9bb91501ebd76 upstream.
> 
> This driver supports the MIPI DSI encoder found in the RZ/G2L
> SoC. It currently supports DSI video mode only.

Tiny nits:


> --- /dev/null
> +++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi.c
...
> +static int rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi *dsi)
> +{
> +	u32 vich1set0r;
> +	u32 status;
> +	int ret;
> +
> +	/* Configuration for Blanking sequence and start video input*/

" */".

> +++ b/drivers/gpu/drm/rcar-du/rzg2l_mipi_dsi_regs.h
> @@ -0,0 +1,151 @@
> +/* DPHY Registers */
> +#define DSIDPHYCTRL0			0x00
> +#define DSIDPHYCTRL0_CAL_EN_HSRX_OFS	BIT(16)
> +#define DSIDPHYCTRL0_CMN_MASTER_EN	BIT(8)
> +#define DSIDPHYCTRL0_RE_VDD_DETVCCQLV18	BIT(2)
> +#define DSIDPHYCTRL0_EN_LDO1200		BIT(1)
> +#define DSIDPHYCTRL0_EN_BGR		BIT(0)
...

> +/* HS Clock Set Register */
> +#define HSCLKSETR			0x104
> +#define HSCLKSETR_HSCLKMODE_CONT	(1 << 1)
> +#define HSCLKSETR_HSCLKMODE_NON_CONT	(0 << 1)
> +#define HSCLKSETR_HSCLKRUN_HS		(1 << 0)
> +#define HSCLKSETR_HSCLKRUN_LP		(0 << 0)

Mixing of BIT() and << looks kind of strange. Plus (0 << 0) is kind of
strange way to say 0. Not sure if this is worth fixing, but usually
people would not do special define for "NON_CONT" when it is 0 and
they already have "CONT" defined.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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